KR20040006677A - Current saving device - Google Patents

Abstract

According to an embodiment of the present invention, the current saving device is provided with a chip select signal / CS and outputs a control signal CS_CLKB for determining whether an internal clock ICLK is generated. An internal clock generator for generating an internal clock ICLK is provided to generate an internal clock only when the chip select signal / CS is at a low level. As such, since the internal clock is generated only in the clock cycle to which the command is applied, current consumption due to unnecessary internal clock generation can be prevented.

Description

Current saving device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for saving current in a semiconductor memory, and more particularly, to generate an internal clock only in a specific case by using a chip select signal to cut current consumption due to unnecessary internal clock generation. It is about a saving circuit.

In conventional semiconductor memory, the internal clock of the product is always generated even in a clock cycle in which no command is input.

The role of the internal clock can be largely divided into accepting commands and addresses synchronously with the external clock, and the rest. At this time, the clock should be counted regardless of whether a command and an address have been input for the remaining roles.

As described above, the current consumed to receive commands and addresses in synchronization with the external clock accounts for most of the current consumed by the entire internal clock.

However, even internal clocks are applied to clock cycles without instructions, consuming current that is not necessary.

Accordingly, an object of the present invention to solve the above problem is to synchronize the command and address to the external clock in the chip select signal enabled state by using the rule that the chip select signal must be enabled in the clock cycle in which the command is received. The internal clock is generated to prevent the current consumption due to unnecessary clock operation to save the current.

1 is a block diagram of a current saving device according to the present invention,

2 is a circuit diagram showing a first embodiment of the current saving device according to the present invention;

3 is an operation timing diagram of the first embodiment of the present invention;

4 is a circuit diagram showing a second embodiment of the current saving device according to the present invention;

5 is an operation timing diagram of a second embodiment of the present invention;

6 is a circuit diagram showing a third embodiment of the current saving device according to the present invention;

7 is a circuit diagram showing a fourth embodiment of the current saving device according to the present invention;

The current saving device of the present invention for achieving the above object is controlled with an internal clock control signal generator and an external clock signal CLK for outputting a control signal CS_CLKB for determining whether an internal clock ICLK is generated by receiving a chip select signal / CS. An internal clock generator for generating an internal clock ICLK according to the state of the signal CS_CLKB is provided.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a view showing the configuration of the current saving device of the present invention.

The internal clock control signal generator 10 receives the chip select signal / CS and generates a control signal CS_CLKB that determines whether an internal clock is generated.

The internal clock control signal generator 10 outputs the control signal CS_CLKB at a low level so as not to generate an internal clock when the chip select signal / CS is at a high level, and generates an internal clock when the chip select signal / CS is at a low level. The signal CS_CLKB is output at a high level.

The internal clock generator 20 outputs an internal clock ICLK for synchronizing commands and addresses to the external clock according to the state of the external clock CLK and the control signal CS_CLKB from the internal clock control signal generator 10.

The internal clock generator 20 generates an internal clock ICLK when the control signal CS_CLKB is at a high level and is fixed at a low level without generating an internal clock ICLK when the control signal CS_CLKB is at a low level.

2 is a circuit diagram showing a first embodiment in which the current saving device of the present invention is actually implemented.

The internal clock control signal generator 10 includes an inverter I1 that receives the chip select signal / CS and inverts the output signal. The internal clock generator 20 has an external clock CLK and a control signal CS_CLKB connected to an input terminal to output an output signal. A NAND gate ND1 for outputting CLKB and an inverter I2 for outputting the internal clock ICLK by inverting the output signal CLKB of the NAND gate ND1 are provided.

3 is an operation timing diagram of the first embodiment of the present invention.

When the chip select signal / CS is at a high level, the inverter I1 inverts the output signal and outputs a low level control signal CS_CLKB.

At this time, when the NAND gate ND1 receives the high level external clock CLK and the low level control signal CS_CLKB, the NAND gate ND1 outputs the high level output signal CLKB, which is inverted by the inverter I2 so that the internal clock ICLK is fixed to a low level without being output. .

When the chip select signal / CS transitions to a low level, when the external signal CLK transitions to a high level while the control signal CS_CLKB transitions to a high level and the control signal CS_CLKB remains at a high level, the NAND gate ND1 applies a high level to both input terminals. The low level output signal CLKB is output, which is inverted by the inverter I2 to output the internal clock ICLK to the high level.

Fig. 4 shows a circuit diagram showing a second embodiment of the present invention.

The internal clock control signal generator 30 in the present embodiment inverts the chip select signal / CS to invert the floating of the control signal CS_CLKB of the inverter 32 and the inverter 32 that outputs the control signal CS_CLKB. A latch portion 34 is provided for preventing.

In this case, the inverting unit 32 has a PMOS transistor P1 and two NMOS transistors N1 and N2 connected in series between a power supply voltage and a ground voltage terminal. The gate terminals of the PMOS transistor P1 and the NMOS transistor N1 are commonly connected to receive the chip select signal / CS, and the drain terminals are commonly connected to output the control signal CS_CLKB.

The gate terminal of the NMOS transistor N2 is connected to the output signal CLKB of the NAND gate ND2 of the internal clock generator 40.

The latch unit 34 has two inverters I3 and I4 connected in series, and an input / output terminal is connected to an output terminal of the inverting unit 32 to maintain the level of the control signal CS_CLKB.

The internal clock generator 40 is connected to the NAND gate ND2 in which the external clock CLK and the control signal CS_CLKB are input signals in series, and the inverter I5 is connected in series. The output signal CLKB of the NAND gate ND2 is the gate of the NMOS transistor N2 of the inverter 32. It is applied to the terminal.

5 is an operation timing diagram of the second embodiment of the present invention.

When the chip select signal / CS transitions from the high level to the low level, the PMOS transistor P1 is turned on so that the control signal CS_CLKB transitions to the high level. If the external clock CLK transitions to a high level while the control signal CS_CLKB is held at a high level, the NAND gate ND2 is applied with a high level to both input terminals to output a low level signal CLKB, which is inverted by the inverter I5 so that the internal clock ICLK is inverted. Output is at high level.

Here, even when the chip select signal / CS is transitioned to the high level, the control signal CS_CLKB is maintained by the latch unit 34, which is the previous level. Therefore, the output signal CLKB of the NAND gate ND2 is maintained at a low level until the external clock CLK transitions to a low level, and the internal clock ICLK is maintained at a high level and output.

Therefore, in this embodiment, as in the first embodiment, the waveforms of the external clock CLK are all transmitted to the internal clock ICLK regardless of the time when the chip select signal / CS transitions to the high level.

6 is a view showing a third embodiment of the present invention.

In the present embodiment, the non-inverting part 50 is further provided to output the output signal ICLK2 by non-inverting the external clock CLK to output the external clock CLK to the internal clock ICLK2 without being affected by the chip select signal / CS. The non-inverting unit 50 is connected in series with an inverter I6 inverting the external clock CLK and outputting the signal CLKB2 and an inverter I7 inverting the output signal CLKB2 and outputting the internal clock ICLK2.

FIG. 7 is a diagram illustrating a fourth embodiment of the present invention. A signal CLKB2 obtained by inverting an external clock CLK without using an output signal CLKB for a signal applied to a gate terminal of an NMOS transistor N2 of an internal clock control signal generator 30 is shown. This is the case.

Even in this case, the same internal clock ICLK waveform as in FIG. 5 can be obtained.

As described above, the present invention has the effect that the internal clock is generated only when the chip select signal is at a low level, thereby preventing the current consumption used to generate unnecessary internal clocks.

Claims (9)

An internal clock control signal generator configured to receive a chip select signal and output a control signal for determining whether an internal clock is generated; And And an internal clock generator configured to generate an internal clock according to an external clock and a logic state of the control signal. The method of claim 1, And the internal clock generator provides an internal clock only when the chip select signal is enabled. The method of claim 1, wherein the internal clock generator A logic unit outputting a low level only when both the external clock and the control signal are at a high level; And And a buffer for inverting and outputting the output of the logic unit. The method of claim 3, wherein And the internal clock control signal generator inverts and outputs the chip select signal. The method of claim 4, wherein the internal clock control signal generation unit An inversion unit for inverting and outputting the chip selection signal according to a logic state of a chip selection signal and an output signal of the logic unit; And And a latch portion for holding the output of the inverting portion. The method of claim 5, wherein And the inverting unit outputs a low level when the chip select signal is enabled and the output signal of the logic unit is a high level. The method of claim 5, wherein And the latch unit non-inverts and outputs the output signal of the inverting unit. The method of claim 3, wherein And a non-inverting unit for non-inverting and outputting the external clock. The method of claim 8, And the inversion unit outputs the control signal according to a logic state of the chip selection signal and the inversion signal of the external clock.