KR20030096703A - method for fabricating semicinductor device - Google Patents
method for fabricating semicinductor device Download PDFInfo
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- KR20030096703A KR20030096703A KR1020020033705A KR20020033705A KR20030096703A KR 20030096703 A KR20030096703 A KR 20030096703A KR 1020020033705 A KR1020020033705 A KR 1020020033705A KR 20020033705 A KR20020033705 A KR 20020033705A KR 20030096703 A KR20030096703 A KR 20030096703A
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- 238000000034 method Methods 0.000 title claims abstract description 25
- 238000002955 isolation Methods 0.000 claims abstract description 29
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 229910052786 argon Inorganic materials 0.000 claims abstract description 15
- 239000004065 semiconductor Substances 0.000 claims abstract description 15
- 238000005468 ion implantation Methods 0.000 claims abstract description 11
- 230000001590 oxidative effect Effects 0.000 claims abstract description 3
- 150000002500 ions Chemical class 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 230000001965 increasing effect Effects 0.000 description 5
- -1 argon ions Chemical class 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000002708 enhancing effect Effects 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
- 229940116641 vaginal film Drugs 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
본 발명은 기판의 분리영역에 STI(Shallow Trench Isolation) 공정을 적용할 경우, 웰 간의 격리를 강화시킬 수 있는 반도체소자의 분리방법에 관해 개시한 것으로서, 반도체기판에 트렌치를 형성하는 단계와, 트렌치를 덮는 희생산화막을 형성하는 단계와, 희생산화막을 포함한 트렌치 부분에 아르곤 이온주입을 실시하여 트렌치 하부에 채널스톱영역을 형성하는 단계와, 희생산화막을 제거하는 단계와, 결과물을 열산화하여 트렌치를 덮는 열산화막을 형성하는 단계와, 열산화막을 포함한 트렌치를 매립시키는 소자분리막을 형성하는 단계와, 소자분리막을 포함한 기판에 분리영역을 기준으로 양측에 각각의 제 1및 제 2웰을 형성하는 단계를 포함한다.The present invention relates to a method of separating a semiconductor device that can enhance isolation between wells when a shallow trench isolation (STI) process is applied to an isolation region of a substrate, the method comprising: forming a trench in a semiconductor substrate; Forming a sacrificial oxide film covering the sacrificial oxide, forming a channel stop region under the trench by argon ion implantation into the trench including the sacrificial oxide film, removing the sacrificial oxide film, and thermally oxidizing the resultant trench. Forming a covering thermal oxide film, forming a device isolation film to fill a trench including the thermal oxide film, and forming respective first and second wells on both sides of the substrate including the device isolation film based on the isolation region. It includes.
Description
본 발명은 반도체소자의 분리방법에 관한 것으로, 보다 상세하게는 기판의 격리영역에 STI(Shallow Trench Isolation) 공정을 적용할 경우, 웰 간의 격리를 강화시킬 수 있는 반도체소자의 분리방법에 관한 것이다.The present invention relates to a method of separating a semiconductor device, and more particularly, to a method of separating a semiconductor device that can enhance isolation between wells when a shallow trench isolation (STI) process is applied to an isolation region of a substrate.
실리콘 웨이퍼에 형성되는 반도체 장치는 개개의 회로 패턴들을 전기적으로 분리하기 위한 소자 분리 영역을 포함한다. 상기 소자 분리 영역의 형성은 모든 제조 단계에 있어서 초기 단계의 공정으로서, 활성영역의 크기 및 후공정 단계의 공정마진을 좌우하게 되기 때문에 반도체 장치가 고집적화 되고 미세화 되어감에 따라 각 개별 소자의 크기를 축소시키는 차원에서 소자 분리 영역 및 게이트 전극 길이(length) 축소 뿐만 아니라 웰(well) 간 거리 축소에 대한 연구가 활발히 진행되고 있다.Semiconductor devices formed on silicon wafers include device isolation regions for electrically separating individual circuit patterns. The formation of the device isolation region is an initial step in all manufacturing steps, and depends on the size of the active area and the process margin of the post-process step. As the semiconductor device becomes highly integrated and miniaturized, the size of each individual device is increased. In order to reduce the size, research on the device isolation region and the gate electrode length reduction as well as the distance between the wells are being actively conducted.
이에 따라 웰 간 거리가 줄어들게 되어 웰 펀치(well punch)가 발생할 확률이 커지게 된다. 상기 웰 펀치가 발생하면 디바이스의 누설전류가 증가하여 디바이스의 원하는 특성을 구현하지 못하게 된다. 따라서, 이를 방지하기 위해 트렌치 깊이를 깊게 만들어 격리를 강화하는 방법도 제안되고 있지만 이는 기판에 데미지(damage)를 주어 디스로케이션(dislocation) 등의 디펙트(defect)를 발생시킴으로써 누설 전류를 증가시킨다. 이 외에도 P웰과 N웰이 형성되는 깊이를 다르게 하여 웰 간의 펀치를 막아주는 방법도 있지만 이러한 방법도 기존의 트렌치보다 더 깊은 트렌치를 형성시킴으로써 기판에 과도한 데미지를 줄뿐만 아니라 후속 열처리에 의해 TED(Trensient Enhanced Diffusion)이 발생된다.As a result, the distance between the wells is reduced, thereby increasing the probability of generating a well punch. When the well punch occurs, the leakage current of the device is increased, thereby failing to realize desired characteristics of the device. Therefore, a method of strengthening the isolation by deepening the trench depth has been proposed to prevent this, but this causes damage to the substrate to increase the leakage current by causing defects such as dislocations. In addition, there is a method of preventing the punch between the wells by varying the depth of forming the P well and the N well, but this method also forms a deeper trench than the conventional trench to not only cause excessive damage to the substrate but also to perform TED ( Trensient Enhanced Diffusion) occurs.
이에 본 발명은 상기 종래의 문제점을 해결하기 위해 안출된 것으로, P웰 및 N웰 간의 분리를 강화시키어 웰 펀치를 막을 수 있는 반도체소자의 분리 방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method of separating a semiconductor device capable of preventing well punch by enhancing separation between P wells and N wells.
도 1a 내지 도 1f는 본 발명에 따른 반도체소자의 분리 방법을 설명하기 위해 도시한 공정단면도.1A to 1F are cross-sectional views illustrating a method of separating a semiconductor device in accordance with the present invention.
도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings
10. 반도체기판 11. 트렌치10. Semiconductor Substrate 11.Trench
12,13. 패드 산화막 14,15. 실리콘 질하막12,13. Pad oxide 14,15. Silicone vaginal film
20. 희생산화막 22. 채널스톱영역20. Sacrificial oxide film 22. Channel stop area
24. 열산화막 26. 소자분리막24. Thermal Oxide 26. Device Separator
28.공핍영역 30. 감광막 패턴28. Depletion region 30. Photoresist pattern
40. 아르곤 이온 주입 공정40. Argon ion implantation process
a. P웰 b. N웰a. P well b. N well
상기 목적을 달성하기 위한 본 발명의 반도체소자의 분리 방법은 반도체기판에 트렌치를 형성하는 단계와, 트렌치를 덮는 희생산화막을 형성하는 단계와, 희생산화막을 포함한 트렌치 부분에 아르곤 이온주입을 실시하여 트렌치 하부에 채널스톱영역을 형성하는 단계와, 희생산화막을 제거하는 단계와, 결과물을 열산화하여 트렌치를 덮는 열산화막을 형성하는 단계와, 열산화막을 포함한 트렌치를 매립시키는 소자분리막을 형성하는 단계와, 소자분리막을 포함한 기판에 분리영역을 기준으로 양측에 각각의 제 1 및 제 2웰을 형성하는 단계를 포함한 것을 특징으로 한다.In order to achieve the above object, a semiconductor device isolation method includes forming a trench in a semiconductor substrate, forming a sacrificial oxide film covering the trench, and implanting argon ions into the trench including the sacrificial oxide film. Forming a channel stop region in the lower portion, removing the sacrificial oxide film, forming a thermal oxide film covering the trench by thermally oxidizing the resultant, and forming a device isolation film filling the trench including the thermal oxide film; And forming first and second wells on both sides of the substrate including the device isolation layer on both sides of the isolation region.
상기 아르곤 이온 주입 공정에서, 바람직하게는, 상기 아르곤 이온 도우즈는 2E13 ∼1E14 atoms/Cm2 범위를 가지고, 30∼400eV 에너지 범위를 가진다.In the argon ion implantation step, preferably, the argon ion dose has a range of 2E13 to 1E14 atoms / Cm2 and has an energy range of 30 to 400 eV.
본 발명에서는 P웰과 N웰 사이에서 소자분리막 아래에 형성된 채널스톱영역의 양옆에는 공핍영역이 형성되므로, 상기 공핍영역에 의해 P웰의 P도전형 이온이나 N웰의 N도전형 이온이 이동하는 거리가 길어지게 됨으로서 P웰 및 N웰 간의 격리가 강화되고, 또한 웰 펀치가 방지된다.In the present invention, since a depletion region is formed on both sides of the channel stop region formed under the device isolation layer between the P well and the N well, P depletion ions in the P well or N conductive ions in the N well are moved by the depletion region. Longer distances enhance isolation between P wells and N wells and also prevent well punch.
이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1f는 본 발명에 따른 반도체소자의 분리 방법을 설명하기 위해 도시한 공정단면도이다.1A to 1F are cross-sectional views illustrating a method of separating a semiconductor device according to the present invention.
본 발명에 따른 반도체소자의 분리 방법, 도 1a에 도시된 바와 같이, 먼저 반도체기판(10) 상에 스트레스 완화용 버퍼 역할을 하는 패드 산화막(12) 및 산화를 억제하는 실리콘 질화막(14)을 차례로 증착한다. 이어, 상기 실리콘 질화막(104) 상에 감광막을 도포하고 노광 및 현상하여 소자의 분리영역(미도시)를 노출시키는 제 1감광막 패턴(30)을 형성한다.A method of separating a semiconductor device according to the present invention, as shown in FIG. 1A, first, a pad oxide film 12 serving as a stress relaxation buffer on a semiconductor substrate 10 and a silicon nitride film 14 for inhibiting oxidation are sequentially Deposit. Subsequently, a photoresist layer is coated on the silicon nitride layer 104, and the photoresist layer is exposed and developed to form a first photoresist layer pattern 30 exposing an isolation region (not shown) of the device.
그런 다음, 도 1b에 도시된 바와 같이, 상기 제 1감광막 패턴(30)을 마스크로 하고 실리콘 질화막, 패드 산화막 및 기판의 소정깊이까지 식각하여 트렌치(trench)(11)를 형성한다. 이때, 도면부호 13은 상기 트렌치 형성을 위한 식각 공정 진행 후에 기판에 잔류된 패드 산화막을, 도면 부호 14는 잔류된 실리콘 질화막을 각각 나타낸 것이다.Next, as shown in FIG. 1B, the trench 11 is formed by etching the silicon nitride layer, the pad oxide layer, and the substrate to a predetermined depth using the first photoresist layer pattern 30 as a mask. In this case, reference numeral 13 denotes a pad oxide film remaining on the substrate after the etching process for forming the trench, and reference numeral 14 denotes a silicon nitride film remaining.
이 후, 상기 제 1감광막 패턴을 제거하고 나서, 도 1c에 도시된 바와 같이, 트렌치(11)를 포함한 기판에 열처리를 실시하여 트렌치(11)의 측면 및 바닥면을 덮는 희생산화막(20)을 형성한다.Thereafter, after removing the first photoresist layer pattern, as shown in FIG. 1C, the sacrificial oxide layer 20 covering the side and bottom surfaces of the trench 11 is heat-treated to heat the substrate including the trench 11. Form.
이어, 도 1d에 도시된 바와 같이, 상기 희생산화막(20)을 포함한 기판 전면에 아르곤(Ar)이온 주입 공정(40)을 실시하여 기판의 트렌치(11) 바닥면과 대응된 부분, 즉 희생산화막(20) 하부에 채널스톱영역(22)을 형성한다. 이때, 상기 아르곤 이온 주입 공정(40)은 30∼400eV 범위의 에너지를 공급하고, 아르곤 이온 도우즈는 2E13 ∼1E14 atoms/Cm2 범위를 가진다. 또한, 기판의 트렌치(11) 이외의 부분은 실리콘 질화막(15)에 의해 덮여져 있으므로 아르곤 이온이 주입되지 않는다. 한편, 상기 아르곤 이온 주입 공정(40)에서, 상기 희생산화막(20)은 기판의 트렌치(11) 부분이 직접적으로 노출되는 것을 막아 이온 주입에 의한 데미지를 줄여주는 역할을 한다.Subsequently, as shown in FIG. 1D, an argon (Ar) ion implantation process 40 is performed on the entire surface of the substrate including the sacrificial oxide film 20, that is, the portion corresponding to the bottom surface of the trench 11 of the substrate, that is, the sacrificial oxide film. (20) A channel stop region 22 is formed below. At this time, the argon ion implantation step 40 supplies energy in the range of 30 to 400 eV, and the argon ion dose has a range of 2E13 to 1E14 atoms / Cm2. In addition, since portions other than the trench 11 of the substrate are covered by the silicon nitride film 15, argon ions are not implanted. Meanwhile, in the argon ion implantation process 40, the sacrificial oxide film 20 serves to reduce the damage caused by ion implantation by preventing the trench 11 portion of the substrate from being directly exposed.
그런 다음, 도 1e에 도시된 바와 같이, 상기 희생산화막을 제거하여 기판 표면을 노출시킨 후, 상기 결과물을 열산화하여 트렌치(11)의 바닥면 및 측면을 덮는 열산화막(24)을 형성한다. 이 후, 실리콘 질화막을 제거한다. 이어, 상기 열산화막(24)을 포함한 기판 전면에 HDP(High Density Plasma) 공정에 의해 절연막(미도시)을 형성하고 나서, 상기 절연막을 에치백(etch back)하여 소자분리막(26)을 형성한다.Next, as shown in FIG. 1E, the sacrificial oxide film is removed to expose the surface of the substrate, and the resultant product is thermally oxidized to form a thermal oxide film 24 covering the bottom and side surfaces of the trench 11. Thereafter, the silicon nitride film is removed. Subsequently, an insulating film (not shown) is formed on the entire surface of the substrate including the thermal oxide film 24 by a high density plasma (HDP) process, and the device isolation film 26 is formed by etching back the insulating film. .
그런 다음, 도 1f에 도시된 바와 같이, 기판의 PMOS형성영역(도면에서, 기판의 오른쪽 부분)을 덮고 NMOS 형성영역에 보론 등의 P형이온을 주입하여 P웰(a)을 형성하고 나서, 다시 반대로 기판의 NMOS영역(기판의 왼쪽부분)에 인 등의 N형 이온을 주입하여 N웰(b)을 형성한다.Then, as illustrated in FIG. 1F, the P well a is formed by covering the PMOS forming region (in the figure, the right part of the substrate) of the substrate and injecting P-type ions such as boron into the NMOS forming region. Conversely, N-type ions such as phosphorous are implanted into the NMOS region (left side of the substrate) of the substrate to form the N well b.
본 발명에 따르면, P웰(a) 과 N웰(b) 사이에서 소자분리막(26) 아래에 형성된 채널스톱영역(22)의 양옆에는 공핍영역(28)이 형성되므로, 상기 공핍영역(28)에 의해 P웰의 P형 이온(예로, 보론)이나 N웰(b)의 N형 이온(예로, 인)이 이동하는 거리가 길어지게 됨으로서 P웰 및 N웰 간의 격리가 강화되고, 또한 웰 펀치가 방지된다.According to the present invention, since the depletion region 28 is formed on both sides of the channel stop region 22 formed under the device isolation layer 26 between the P well a and the N well b, the depletion region 28 is formed. This increases the distance between P-type ions (eg, boron) of the P well and N-type ions (eg, phosphorus) of the N well (b), thereby enhancing the isolation between the P well and the N well, and also well punching. Is prevented.
이상에서와 같이, 본 발명은 STI를 이용한 격리 공정에 마스크가 필요없는 블랭킷 아르곤 이온 주입 공정을 추가하여 소자분리막 아래에 채널스톱영역을 형성함으로서, 상기 채널스톱영역 양옆에 다시 공핍영역이 형성됨에 따라 P웰의 P도전형 이온이나 N웰의 N도전형 이온이 이동하는 거리가 길어지게 되어 웰 간 격리를강화할 수 있고, 누설전류 증가에 의한 디바이스의 특성 저하를 방지할 수 있다. 뿐더러 소자분리막의 너비(width)가 축소됨에 따라 발생되는 웰 펀치를 방지하는 잇점이 있다.As described above, the present invention forms a channel stop region under the device isolation layer by adding a blanket argon ion implantation process that does not require a mask to the isolation process using STI, thereby forming a depletion region on both sides of the channel stop region. The distance between the P-conducting ions of the P well and the N-conducting ions of the N well is increased, so that isolation between the wells can be enhanced, and device deterioration can be prevented by increasing leakage current. In addition, there is an advantage of preventing the well punch generated as the width of the device isolation layer is reduced.
기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100714949B1 (en) * | 2005-11-25 | 2007-05-04 | 후지쯔 가부시끼가이샤 | Semiconductor device and manufacturing method thereof |
| WO2015026371A1 (en) * | 2013-08-23 | 2015-02-26 | Intel Corporation | High resistance layer for iii-v channel deposited on group iv substrates for mos transistors |
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| JPS55154748A (en) * | 1979-05-23 | 1980-12-02 | Toshiba Corp | Complementary mos semiconductor device |
| KR19980079630A (en) * | 1997-03-17 | 1998-11-25 | 포맨 제프리 엘 | How to reduce the effects of damage from isolation structures and latch ups |
| KR20000025113A (en) * | 1998-10-08 | 2000-05-06 | 김영환 | Method for forming field oxide of semiconductor device |
| KR20010061041A (en) * | 1999-12-28 | 2001-07-07 | 박종섭 | Forming method for a field oxide of semiconductor device |
| KR20020082283A (en) * | 2001-04-20 | 2002-10-31 | 삼성전자 주식회사 | Method of trench type device isolation in semiconductor device fabrication |
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| JPS55154748A (en) * | 1979-05-23 | 1980-12-02 | Toshiba Corp | Complementary mos semiconductor device |
| KR19980079630A (en) * | 1997-03-17 | 1998-11-25 | 포맨 제프리 엘 | How to reduce the effects of damage from isolation structures and latch ups |
| KR20000025113A (en) * | 1998-10-08 | 2000-05-06 | 김영환 | Method for forming field oxide of semiconductor device |
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| KR100714949B1 (en) * | 2005-11-25 | 2007-05-04 | 후지쯔 가부시끼가이샤 | Semiconductor device and manufacturing method thereof |
| WO2015026371A1 (en) * | 2013-08-23 | 2015-02-26 | Intel Corporation | High resistance layer for iii-v channel deposited on group iv substrates for mos transistors |
| US9882009B2 (en) | 2013-08-23 | 2018-01-30 | Intel Corporation | High resistance layer for III-V channel deposited on group IV substrates for MOS transistors |
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