KR20030095447A - Method for forming dual gate in semiconductor device - Google Patents
Method for forming dual gate in semiconductor device Download PDFInfo
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- KR20030095447A KR20030095447A KR1020020032347A KR20020032347A KR20030095447A KR 20030095447 A KR20030095447 A KR 20030095447A KR 1020020032347 A KR1020020032347 A KR 1020020032347A KR 20020032347 A KR20020032347 A KR 20020032347A KR 20030095447 A KR20030095447 A KR 20030095447A
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- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
- H10D84/85—Complementary IGFETs, e.g. CMOS
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Abstract
본 발명은 NMOS 게이트의 채널링 효과를 억제할 수 있는 반도체 소자의 이중 게이트 형성 방법에 관한 것으로, 반도체 기판상에 게이트 산화막을 형성하는 단계; 상기 게이트 산화막 상면에 주상 구조의 폴리실리콘층을 형성하는 단계; 상기 폴리실리콘층의 표면 일부에 소정의 이온 주입 에너지로써 비소(As) 이온을 주입하는 단계; 및 상기 비소 이온이 주입된 폴리실리콘층을 열처리하는 단계를 포함하는 것을 특징으로 하며, 기존의 인(P)보다 결정립을 성장시키는 특성이 크지 않아 결정립의 조대 성장을 억제할 수 있는 비소(As)를 폴리실리콘층에 주입함으로써 결정립의 조대 성장을 NMOS 게이트 전극 상부에만 국한시킬 수 있다. 따라서, 주상 구조가 NMOS 게이트 전극 하부에 유지되므로 채널링 효과를 억제할 수 있게 되어 소자의 전기적 특성을 향상시킬 수 있는 효과가 있는 것이다.The present invention relates to a method of forming a double gate of a semiconductor device capable of suppressing the channeling effect of an NMOS gate, comprising: forming a gate oxide film on a semiconductor substrate; Forming a polysilicon layer having a columnar structure on an upper surface of the gate oxide film; Implanting arsenic (As) ions into a portion of the surface of the polysilicon layer with a predetermined ion implantation energy; And heat-treating the polysilicon layer into which the arsenic ions are implanted, and the arsenic (As) capable of suppressing coarse growth of the crystal grains because the grain growth is not greater than that of the conventional phosphorus (P). By injecting the polysilicon layer into the polysilicon layer, coarse growth of grains can be limited to only the upper portion of the NMOS gate electrode. Therefore, since the columnar structure is maintained under the NMOS gate electrode, the channeling effect can be suppressed, thereby improving the electrical characteristics of the device.
Description
본 발명은 반도체 소자의 이중 게이트 형성 방법에 관한 것으로, 보다 상세하게는 게이트 채널링 효과를 억제할 수 있는 반도체 소자의 이중 게이트 형성 방법에 관한 것이다.The present invention relates to a method of forming a double gate of a semiconductor device, and more particularly, to a method of forming a double gate of a semiconductor device capable of suppressing a gate channeling effect.
일반적으로 0.35㎛ 공정기술 이하의 고집적 로직 CMOS 소자 제조시에는 이중 게이트 구조가 이용된다. 이러한 이중 게이트 구조를 채택하는 반도체 소자의 이중 게이트 형성 방법을 개략적으로 설명하면 다음과 같다.In general, a double gate structure is used for fabricating highly integrated logic CMOS devices of less than 0.35 탆 process technology. A double gate forming method of a semiconductor device adopting such a double gate structure will be described as follows.
먼저 이중 게이트에서 PMOS 게이트를 형성하는 공정을 개략적으로 설명하면, 반도체 기판에 게이트 산화막을 형성한 후 폴리실리콘층을 순차로 적층한다. 이어서, 상기 결과물을 열처리한 후 붕소(B) 이온을 폴리실리콘층에 주입시키고 다시 열처리하고 식각 공정으로 PMOS 게이트를 형성한다.First, a process of forming a PMOS gate from a double gate is schematically described. After forming a gate oxide film on a semiconductor substrate, polysilicon layers are sequentially stacked. Subsequently, after the heat treatment of the resultant, boron (B) ions are implanted into the polysilicon layer, heat treated again, and a PMOS gate is formed by an etching process.
한편, NMOS 게이트를 형성하는 공정을 살펴보면, 반도체 기판에 게이트 산화막을 형성한 후 폴리실리콘층을 순차로 적층한다. 이후 인(P) 이온을 폴리실리콘층에 주입하고 약 1,000℃ 온도에서의 열처리와 식각 공정으로 NMOS 게이트를 형성한다.Meanwhile, referring to a process of forming an NMOS gate, after forming a gate oxide film on a semiconductor substrate, polysilicon layers are sequentially stacked. Phosphorus (P) ions are then implanted into the polysilicon layer to form an NMOS gate by heat treatment and etching at a temperature of about 1,000 ° C.
그러나, 종래 기술에 따른 반도체 소자의 이중 게이트 형성 방법에 있어서는 다음과 같은 문제점이 있다.However, the conventional method of forming a double gate of a semiconductor device has the following problems.
종래 기술에 있어서는, 폴리실리콘층이 주상(columnar) 구조로 성장하기 때문에 PMOS 게이트 형성을 위한 붕소(B) 이온 주입시 붕소 이온이 결정립계를 타고 기판 하부로 침투되는 채널링 현상이 발생한다. 따라서, 채널링 효과를 방지하기 위해 붕소 이온을 주입하기 전에 비정질 폴리실리콘에 대한 열처리 공정을 실시하여 폴리실리콘을 결정질화시킨다.In the prior art, since the polysilicon layer grows in a columnar structure, a channeling phenomenon in which boron ions penetrate into the lower part of the substrate through grain boundaries when implanting boron (B) ions for forming a PMOS gate occurs. Therefore, in order to prevent the channeling effect, the polysilicon is crystallized by performing a heat treatment process on the amorphous polysilicon before implanting the boron ions.
그러나, 이러한 방법은 PMOS 게이트에서의 붕소 이온 침투를 억제하는 장점이 있는 반면에 NMOS 게이트에서의 비소(As) 이온의 채널링 효과를 유발시키는 문제점이 있다.However, this method has the advantage of suppressing boron ion penetration in the PMOS gate, while causing the channeling effect of arsenic (As) ions in the NMOS gate.
그 이유는 NMOS 게이트를 형성하는데 있어서는 먼저 인(P) 이온을 주입하고 그 후에 열처리 공정을 실시하는데 이때 폴리실리콘층이 인 이온을 주입받아 활성화되면 PMOS 게이트와 비교했을 때 상대적으로 더 높은 열역학적 여기 상태에 있게 된다. 따라서, 후속 열처리시 급격한 결정 성장을 하여, 도 1에 도시된 바와 같이, NMOS 게이트(10)는 매우 큰 크기의 결정립(20)(22)상태가 되는 것이다.The reason for this is that in forming NMOS gates, phosphorus (P) ions are first implanted, followed by a heat treatment process. When the polysilicon layer is implanted with phosphorus ions and activated, a relatively higher thermodynamic excitation state is compared with that of the PMOS gate. Will be in. Therefore, rapid crystal growth during subsequent heat treatment causes the NMOS gate 10 to be in a state of crystal grains 20 and 22 having a very large size.
이러한 조대한 결정립(20)(22) 때문에 소오스/드레인 형성을 위한 비소(As) 이온 주입시 채널링(channeling)을 방지할 수 없게 되고, 이로 인하여 누설전류가 증가되고 펀치쓰루(punchthrough) 현상도 발생하게 되는 문제점이 있다.Due to the coarse grains 20 and 22, channeling can not be prevented during the implantation of arsenic (As) ions for source / drain formation, thereby increasing leakage current and causing punchthrough. There is a problem.
이에, 본 발명은 상기한 종래 기술상의 문제점을 해결하기 위하여 안출된 것으로, 본 발명의 목적은 결정립을 성장시키는 특성이 크지 않아 결정립의 조대 성장을 억제할 수 있는 비소(As)를 폴리실리콘층에 주입함으로써 결정립이 조대화 되는 부위를 폴리실리콘층 상부에 국한시켜 결과적으로 NMOS 게이트 하부를 채널링에 저항력 있는 주상 구조로 유지시킬 수 있는 반도체 소자의 이중 게이트 형성 방법을 제공함에 있다.Accordingly, the present invention has been made to solve the above-mentioned problems in the prior art, an object of the present invention is to increase the grain growth characteristics of the arsenic (As) that can suppress the coarse growth of crystal grains in the polysilicon layer The present invention provides a method for forming a double gate of a semiconductor device in which a region where grains are coarsened by implantation is limited to an upper portion of a polysilicon layer, and as a result, the lower portion of the NMOS gate can be maintained in a columnar structure resistant to channeling.
도 1은 종래 기술에 따른 반도체 소자의 이중 게이트 형성 방법에 있어서, NMOS 게이트의 채널링 효과를 도시한 단면도.1 is a cross-sectional view illustrating a channeling effect of an NMOS gate in a method of forming a double gate of a semiconductor device according to the prior art.
도 2a 내지 도 2d는 본 발명에 따른 반도체 소자의 이중 게이트 형성 방법을 도시한 공정별 단면도.2A through 2D are cross-sectional views illustrating processes of forming a double gate of a semiconductor device according to the present invention.
- 도면의 주요부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawings-
100; 반도체 기판110; 소자분리막100; Semiconductor substrate 110; Device Separator
120; 게이트 산화막130; 주상 조직의 폴리실리콘층120; A gate oxide film 130; Polysilicon layer of columnar tissue
140; 포토레지스트 패턴150; 비정질 조직의 폴리실리콘층140; Photoresist pattern 150; Polysilicon Layer of Amorphous Tissue
160; 조대 결정립 조직의 폴리실리콘층160; Polysilicon layer of coarse grain structure
상기 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 이중 게이트 형성 방법은, 반도체 기판상에 게이트 산화막을 형성하는 단계; 상기 게이트 산화막 상면에 주상 구조의 폴리실리콘층을 형성하는 단계; 상기 폴리실리콘층의 표면 일부에 소정의 이온 주입 에너지로써 비소(As) 이온을 주입하는 단계; 및 상기 비소 이온이 주입된 폴리실리콘층을 열처리하는 단계를 포함하는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of forming a double gate of a semiconductor device, the method including: forming a gate oxide film on a semiconductor substrate; Forming a polysilicon layer having a columnar structure on an upper surface of the gate oxide film; Implanting arsenic (As) ions into a portion of the surface of the polysilicon layer with a predetermined ion implantation energy; And heat treating the polysilicon layer into which the arsenic ions are implanted.
상기 소정의 이온 주입 에너지는 상기 비소 이온이 주입되는 폴리실리콘층의 하부가 주상 구조로 유지될 수 있는 에너지인 것을 특징으로 한다.The predetermined ion implantation energy is characterized in that the lower portion of the polysilicon layer into which the arsenic ions are implanted can maintain the columnar structure.
상기 이온 주입 에너지는 1KeV ~ 30KeV인 것을 특징으로 한다.The ion implantation energy is characterized in that 1KeV ~ 30KeV.
본 발명에 의하면, 결정립의 조대 성장을 억제할 수 있는 비소(As)를 폴리실리콘층에 주입함으로써 결정립의 조대 성장을 NMOS 게이트 전극 상부에만 국한시킬 수 있게 된다.According to the present invention, by injecting arsenic (As) capable of suppressing coarse growth of grains into the polysilicon layer, coarse growth of grains can be limited to only the upper portion of the NMOS gate electrode.
이하, 본 발명에 따른 반도체 소자의 이중 게이트 형성 방법을 첨부한 도면을 참조하여 상세히 설명한다.Hereinafter, a method of forming a double gate of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2d는 본 발명에 따른 반도체 소자의 이중 게이트 형성 방법을 도시한 공정별 단면도이다.2A through 2D are cross-sectional views illustrating processes of forming a double gate of a semiconductor device according to the present invention.
본 발명에 따른 반도체 소자의 이중 게이트 형성 방법은, 도 2a에 도시된 바와 같이, 소자분리막(100)을 사이에 두고 PMOS 영역과 NMOS 영역으로 구분될 반도체 기판(100)상에 상하부 사이를 전기적으로 절연시키기 위한 게이트 산화막(120)을 형성한다. 그런다음, 상기 게이트 산화막(120) 전면상에 주상(Columnar) 구조의 폴리실리콘층(130)을 형성한다.In the method of forming a double gate of a semiconductor device according to the present invention, as shown in FIG. 2A, the device isolation layer 100 is interposed between the upper and lower portions on the semiconductor substrate 100 to be divided into a PMOS region and an NMOS region. A gate oxide film 120 for insulating is formed. Then, a polysilicon layer 130 having a columnar structure is formed on the entire surface of the gate oxide layer 120.
이어서, 도 2b에 도시된 바와 같이, PMOS 영역에 해당하는 폴리실리콘층(130)상에 포토레지스트 패턴(140)을 형성한다. 상기 포토레지스트 패턴(140)을 마스크로 하는 이온 주입 공정을 진행한다.Subsequently, as shown in FIG. 2B, the photoresist pattern 140 is formed on the polysilicon layer 130 corresponding to the PMOS region. An ion implantation process using the photoresist pattern 140 as a mask is performed.
이때, 상기 폴리실리콘층(130) 일부에 주입되는 이온은 NMOS 게이트를 형성하기 위한 비소(As) 이온이며, 상기 비소 이온을 주입하는 에너지는 상기 비소 이온이 주입되는 폴리실리콘층(130)의 하부가 주상 구조로 유지될 수 있는 에너지인 약 1KeV ~ 30KeV이다.In this case, the ions implanted into the polysilicon layer 130 are arsenic (As) ions for forming an NMOS gate, and the energy for injecting the arsenic ions is a lower portion of the polysilicon layer 130 in which the arsenic ions are implanted. Is about 1 KeV to 30 KeV, the energy that can be maintained in the columnar structure.
상기 비소(As) 이온은 기존의 인(P) 이온과는 달리 결정립 성장 특성이 크지 않아 상기 폴리실리콘층(130)이 조대한(coarse) 결정립으로 성장되는 것이 억제된다.Unlike conventional phosphorus (P) ions, the arsenic (As) ions do not have large grain growth characteristics, and thus the polysilicon layer 130 is suppressed from growing into coarse grains.
상기 비소(As) 이온의 주입 공정에 의해서, 도 2c에 도시된 바와 같이, 상기 주상 조직의 폴리실리콘층(130)중에서 NMOS 영역의 폴리실리콘층(150)은 비정질화 된다.As illustrated in FIG. 2C, the polysilicon layer 150 in the NMOS region of the NMOS region is amorphous by the arsenic (As) ion implantation process.
이어서, 도 2d에 도시된 바와 같이, 상기 폴리실리콘층(130)에 대하여 소정의 온도에서 열처리를 하여 재결정화시킨다.Subsequently, as shown in FIG. 2D, the polysilicon layer 130 is recrystallized by heat treatment at a predetermined temperature.
상기와 같은 열처리 공정에 의해 상기 NMOS 영역의 폴리실리콘층(150)은 조대 결정 성장을 하게 되는데, 특히 비소(As) 이온이 주입된 폴리실리콘층 전부가 아닌 일부(160)만이 조대 결정 성장하게 되어, 조대 결정립으로 재결정화된 폴리실리콘층(160) 하부에 채널링에 저항력이 있는 주상 조직이 존재하게 된다.By the heat treatment process as described above, the polysilicon layer 150 of the NMOS region is coarse crystal growth. Particularly, only a part 160 of the polysilicon layer into which arsenic (As) ions are implanted is grown. In addition, a columnar structure resistant to channeling is present under the polysilicon layer 160 recrystallized with coarse grains.
이후, 예정된 후속 공정을 진행하여 NMOS 게이트와 PMOS 게이트로 이루어진 이중 게이트 구조를 완성한다.Subsequently, a predetermined subsequent process is performed to complete a double gate structure consisting of an NMOS gate and a PMOS gate.
본 발명의 원리와 정신에 위배되지 않는 범위에서 여러 실시예는 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 자명할 뿐만 아니라 용이하게실시할 수 있다. 따라서, 본원에 첨부된 특허청구범위는 이미 상술된 것에 한정되지 않으며, 하기 특허청구범위는 당해 발명에 내재되어 있는 특허성 있는 신규한 모든 사항을 포함하며, 아울러 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자에 의해서 균등하게 처리되는 모든 특징을 포함한다.Various embodiments can be easily implemented as well as obvious to those skilled in the art without departing from the spirit and principles of the present invention. Accordingly, the claims appended hereto are not limited to those already described above, and the following claims are intended to cover all of the novel and patented matters inherent in the invention, and are also common in the art to which the invention pertains. Includes all features that are processed evenly by the knowledgeable.
이상에서 설명한 바와 같이, 본 발명에 따른 반도체 소자의 이중 게이트 형성 방법에 의하면, 기존의 인(P)보다 결정립을 성장시키는 특성이 크지 않아 결정립의 조대 성장을 억제할 수 있는 비소(As)를 폴리실리콘층에 주입함으로써 결정립의 조대 성장을 NMOS 게이트 전극 상부에만 국한시킬 수 있다. 따라서, 주상 구조가 NMOS 게이트 전극 하부에 유지되므로 채널링 효과를 억제할 수 있게 되어 소자의 전기적 특성을 향상시킬 수 있는 효과가 있다.As described above, according to the method of forming a double gate of a semiconductor device according to the present invention, since the characteristic of growing crystal grains is not greater than that of conventional phosphorus (P), arsenic (As), which can suppress coarse growth of crystal grains, By implanting into the silicon layer, coarse growth of grains can be limited to only the top of the NMOS gate electrode. Therefore, since the columnar structure is maintained under the NMOS gate electrode, the channeling effect can be suppressed, thereby improving the electrical characteristics of the device.
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| JP2001196469A (en) * | 2000-01-11 | 2001-07-19 | Nec Corp | Method for manufacturing semiconductor device |
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