KR20030080187A - Semiconductor device - Google Patents

Abstract

A semiconductor device having a structure that can be miniaturized by a simple manufacturing process and a method of manufacturing a semiconductor device capable of significantly increasing production efficiency can be obtained. A semiconductor having a semiconductor circuit and an electrode 3 having a predetermined function on one main surface is provided. A chip 1a, a wire 2 having one end connected to the electrode 3 and having a connection terminal 2a connected to the outside at the other end, and at least one insulator covering at least one main surface of the semiconductor chip; The connection terminal 2a at the other end of (2) is a portion formed while maintaining a state in which it is integrated with another portion of the wire, and the connection terminal is exposed from the bottom surface on the opposite side to the upper surface of the insulator on one main surface side. have.

Description

Semiconductor device {SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a miniaturized semiconductor device capable of significantly improving production efficiency and a method of manufacturing the same.

95 is a sectional configuration diagram showing a typical example of a conventional semiconductor device. The semiconductor chip 101a formed on the wafer is mounted on the die pad 105b of the lead frame. The electrode pad 103 of the semiconductor chip is connected by the external lead 105a and the wire 102, which serve as connection terminals with the outside. The wire 102 forms a wire connection terminal 102b at a connection portion with the electrode pad 103 and a wire connection terminal 102a at a connection portion with the external lead 105a. Except for the outer terminal of the outer lead, other portions are sealed by the insulating resin 104 as shown in FIG.

96 to 100 show a method of manufacturing the above semiconductor device. First, as shown in FIG. 96, a plurality of semiconductor circuit regions (semiconductor chip regions) 101a are arranged in a row on the wafer 101, and electrode pads 103 are provided on the surface of each semiconductor chip. Next, as shown in FIG. 97, a wafer is cut | disconnected and separated into units of the semiconductor chip 101a. Then, as shown in FIG. 98, the said separated semiconductor chip is fixed to the die pad 105b of a lead frame. Next, the electrode pad 103 and the external lead 105a disposed on the upper surface of the semiconductor chip are connected by the wire 102 as shown in FIG. 99. Thereafter, as shown in FIG. 100, the resin 104 is sealed except for the terminal of the outer lead 105a. Finally, the portion exposed from the sealing resin of the outer lead 105a is bent inward to make the semiconductor device shown in FIG. 95 smaller in size.

By using the above manufacturing method, a semiconductor device excellent in reliability, for example, a DRAM (Dynamic Random Access Memory) can be obtained.

Since the semiconductor device uses a lead frame, the external lead cannot be located outside of the semiconductor chip in plan view. In order to remove the inhibitory factor of such miniaturization, some proposals have been made so far. For example, as shown in FIG. 101, the resin protrusion 104a covered with the metal film 115a is provided in the bottom part of the semiconductor chip 101a, and the metal film 115a and the electrode pad of the semiconductor chip 101a are provided. A structure for connecting the 103 with the wire 102 has been proposed (Japanese Patent Laid-Open No. 9-162348). According to this structure, since there is no terminal for external connection protruding to the outside of the sealing resin, the semiconductor device can be miniaturized.

Also, as shown in FIG. 102 without using a lead frame, a structure has been proposed in which an external connection means 125a is arranged in close proximity to the semiconductor chip 101a (Japanese Patent Laid-Open No. 10-98133). . In this semiconductor device, the semiconductor chip and the external connection means are sealed with the resin 104 and are exposed from the back surface. Also in this semiconductor device, since the external connection means is located inside the sealing resin in plan view, it can be miniaturized.

However, in the structure shown in FIG. 101 (Japanese Patent Laid-Open No. 9-162348), pattern formation of the metal film 115a covering the resin protrusion 104a is performed. For this reason, a manufacturing process increases and becomes complicated. For this reason, there is a possibility of causing an increase in manufacturing cost and causing a decrease in yield.

In addition, in the structure shown in FIG. 102 (Japanese Patent Laid-Open No. 10-98133), it is necessary to arrange another member called the external connection means 125a during the manufacturing process. For this reason, too, a manufacturing process may become complicated, resulting in the increase of a manufacturing cost, and a yield fall.

In any of the above-described semiconductor devices, when manufactured by the conventional manufacturing method, the semiconductor chips formed through a predetermined processing step are cut for each section of the wafer and separated into individual semiconductor chips. That is, even if there is a difference between using a lead frame and not using it, according to the conventional manufacturing method, the semiconductor device shown in FIGS. 96 to 100 reorganizes the semiconductor chip in a step prior to sealing with any resin. It is manufactured through the process of oxidization.

In the case of wire bonding the electrode pad and the connecting terminal of the semiconductor chip through the step of separating the semiconductor chip, and sealing the resin, it is necessary to perform position alignment or the like for each of the separated semiconductor chips, and the production efficiency is limited. The semiconductor device has a property of lowering the price by mass production and facilitating spreading, but there is a problem in mass production in the method of manufacturing a semiconductor package for each individualized semiconductor chip as described above.

In addition, in the method of manufacturing a semiconductor package for each of the above-described individualized semiconductor devices, handling is difficult when miniaturizing. It is apparent that the above-mentioned miniaturization is aimed at. In the semiconductor devices shown in Figs. 101 and 102, when miniaturization proceeds, handling is also difficult.

In addition, including the miniaturized semiconductor devices of FIGS. 101 and 102 described above, in order to manufacture a semiconductor device in which a plurality of individualized semiconductor chips are stacked, a complicated processing step is required, and the completed semiconductor device is also complicated. It will have a structure. Fig. 103 is a diagram showing a lamination structure in the case of using a lead frame. According to this drawing, it is necessary to reduce the size of the semiconductor chip by the upper layer. For this reason, there was a limit to the number of layers that can be laminated. 104 is a diagram illustrating a case where semiconductor chips of the same size are stacked. According to this drawing, it is understood that when stacking the semiconductor chips of the same size, it must pass through the spacer 111. When the spacer 111 is used, not only the structure is complicated, but also a connection process is required for each layer. For this reason, manufacturing efficiency will also fall.

An object of the present invention is to provide a miniaturized semiconductor device capable of greatly improving production efficiency and a method of manufacturing the semiconductor device.

1 is a cross-sectional configuration diagram of a semiconductor device according to a first embodiment of the present invention.

Fig. 2 is a cross sectional view of a semiconductor device in accordance with the second embodiment of the present invention.

3 is a cross-sectional configuration diagram of a semiconductor device according to a third embodiment of the present invention.

4 is a cross-sectional configuration diagram of a semiconductor device in accordance with a fourth embodiment of the present invention.

FIG. 5 is a cross-sectional view of a step of forming a plurality of circuit patterns of a semiconductor chip on a wafer in the method of manufacturing a semiconductor device according to the fifth embodiment of the present invention. FIG.

6 is a cross-sectional view of the step of bonding the support plate to the back surface of the wafer of FIG.

FIG. 7 is a cross-sectional view illustrating a step of forming grooves by dicing between circuit regions of the semiconductor chip of FIG. 6.

FIG. 8 is a cross-sectional view of a step of forming a bulk connection terminal in the support plate connecting portion when connecting the electrode of the support plate and the semiconductor chip of FIG. 7 with a wire.

FIG. 9 is a view illustrating a situation in which a ball bond is formed by the wire bonding method as the connection terminal of FIG. 8.

FIG. 10 is a cross-sectional view of the semiconductor device in a step of forming a resin pattern covering the semiconductor chip and wire of FIG. 8 with a gap by a screen printing method.

FIG. 11 is a cross-sectional view of the semiconductor device in a step of removing the support plate of FIG. 10 by wet etching.

FIG. 12 is a cross-sectional view of a stage in which the semiconductor device of FIG. 11 is separated.

FIG. 13 is a cross-sectional view of a step in which the semiconductor device of FIG. 12 is mounted on a circuit board.

14 is a cross-sectional view illustrating an example in which the support plate of FIG. 10 is removed by polishing.

15 is a cross-sectional view illustrating another example in which the support plate of FIG. 10 is removed by polishing.

FIG. 16 is a plan view corresponding to FIG. 6 showing a state in which a supporting plate is bonded to the back surface of a wafer after the circuit of the semiconductor chip is formed.

17 is a plan view of a step of providing grooves by dicing between the circuit areas of the wafer of FIG.

FIG. 18 is a plan view of a step of connecting an electrode and a support plate of the semiconductor chip of FIG. 17 with wires.

FIG. 19 is a cross-sectional view of a step in which the semiconductor chip and wire of FIG. 18 are disposed with a gap at the same time and a resin is disposed at a groove intersection and sealed with a resin.

20 is a cross-sectional view of a step of removing the support plate of FIG. 19.

FIG. 21 is a plan view of the semiconductor device of FIG. 20 separated from the semiconductor device of FIG.

Fig. 22 is a cross sectional view of a step of arranging a supporting plate on an upper surface of a resin-sealed semiconductor device in the method of manufacturing a semiconductor device in Embodiment 6 of the present invention.

FIG. 23 is a cross-sectional view of a step of removing the support plate of FIG. 22.

24 is a cross-sectional view of a step of testing an electrical property of a semiconductor device by applying a probe to the exposed connection terminal of FIG. 23.

FIG. 25 is a cross-sectional view of the semiconductor device manufacturing method of Embodiment 7 after forming the connection terminals and connecting the wires, and then forming the upper connection terminals on the connection terminals.

FIG. 26 is a cross-sectional view of a step of forming a resin pattern using a screen printing method so as to cover the semiconductor chip, the wire and the connecting terminal of FIG. 25.

FIG. 27 is a cross-sectional view of a step of removing the support plate of FIG. 26.

FIG. 28 is a diagram showing a semiconductor device obtained by removing resin from the groove intersection portion of the semiconductor device of FIG.

29 is a cross-sectional view illustrating a semiconductor device in which two semiconductor devices of FIG. 28 are stacked in this order.

30 is a cross-sectional view of a step of forming an upper terminal on an electrode of a semiconductor chip after forming connection terminals and connecting wires in the method of manufacturing a semiconductor device according to the eighth embodiment of the present invention.

FIG. 31 is a cross-sectional view of a step of forming a resin pattern so that the upper connection terminal is exposed from the upper surface when the semiconductor chip, the wire and the connection terminal of FIG. 30 are resin-coated.

32 is a cross-sectional view of the step of removing the support plate of FIG.

FIG. 33 is a diagram showing a semiconductor device obtained by removing resin from the groove intersection portion of the semiconductor device of FIG.

FIG. 34 is a cross-sectional view of a semiconductor device having a two-layer structure in which the semiconductor device of FIG. 33 and the semiconductor device (including the case where the semiconductor device itself is applicable) are face-to-face connected to each other.

FIG. 35 is a cross-sectional view of a semiconductor device having a two-layer structure in which the semiconductor device of FIG. 33 and the semiconductor device (including the case where the semiconductor device itself is applicable) are face-to-face connected to each other.

36 is a cross-sectional view illustrating a four-layer semiconductor device formed by stacking two semiconductor devices having a two-layer structure in FIG.

Fig. 37 is a sectional view of a semiconductor device having a three-layer structure in accordance with the eighth embodiment of the present invention.

38 is a cross sectional view of a step of forming a sealing resin pattern so as to expose side portions of the connection terminals in the method of manufacturing a semiconductor device of Example 9 of the present invention;

39 is a plan view of the semiconductor device of FIG.

40 is a cross-sectional view of a step of removing the support plate of FIG. 38.

FIG. 41 is a plan view of the semiconductor device obtained by removing the resin from the groove intersection portion of the semiconductor device of FIG.

FIG. 42 is a cross-sectional view of the step of mounting the semiconductor device of FIG. 41 on a circuit board. FIG.

43 is a cross-sectional view illustrating a multilayer semiconductor device in which the semiconductor device of FIG. 41 is mounted on a wall circuit board.

FIG. 44 shows a multilayer structure in which the semiconductor device of FIG. 41 is arranged on a wall circuit board, wherein at least one side of the multilayer circuit board is arranged so as to protrude outward from the wall circuit board; It is sectional drawing which shows a semiconductor device.

FIG. 45 illustrates a semiconductor device having a multilayer structure in which the heat dissipation plate is disposed so as to protrude outward from at least one side of the multilayer structure in which the semiconductor device of FIG. 41 is disposed on the wall circuit board, and at least one side thereof is not disposed. It is a cross section.

46 is a cross-sectional view of a resin coating step for covering a semiconductor chip and a wire on a wafer without using the resin pattern forming means in the semiconductor device manufacturing method of Embodiment 10 of the present invention.

FIG. 47 is a sectional view of a step of forming a separation groove by a dicing saw to expose the side of the connecting terminal of FIG. 46;

FIG. 48 is a cross-sectional view of the semiconductor device separated by removing the support plate of FIG. 47.

Fig. 49 is a view showing the semiconductor device in Embodiment 11 of the present invention (shown are two semiconductor devices sandwiched with grooves immediately after the supporting plate is removed).

50 is a view showing a state in which an electrode is formed by polishing a wafer in the manufacture of the semiconductor device of FIG. 49.

It is a figure which shows the state which bonded the support plate to the wafer back surface.

It is a figure which shows the state which provided the groove | channel which penetrates a wafer and reaches a support plate.

Fig. 53 is a view showing a state in which a resist pattern is provided.

Fig. 54 shows a state in which metal wirings are formed by a gas deposition method.

55 is a diagram illustrating a state in which a resist pattern is removed.

Fig. 56 shows a state of being sealed with a sealing resin.

Fig. 57 is a diagram showing a modification of the semiconductor device of Example 11 of the present invention.

58 is a diagram showing another modification of the semiconductor device of Example 11 of the present invention.

Fig. 59 is a diagram showing the semiconductor device of Embodiment 12 of the present invention (shown are two semiconductor devices sandwiched in the groove immediately after the supporting plate is removed).

FIG. 60 is a view showing a state in which connection terminals are stacked on the support plate by the gas deposition method in the manufacturing of the semiconductor device of FIG. 59.

Fig. 61 is a diagram illustrating a state in which a resist pattern is removed.

Fig. 62 shows a state of being sealed with a sealing resin.

FIG. 63 shows a modification of the semiconductor device according to the twelfth embodiment of the present invention (shown two semiconductor devices sandwiched with grooves immediately after the supporting plate is removed).

64 is a diagram showing a gas deposition apparatus used in the method of manufacturing a semiconductor device in Example 13 of the present invention.

FIG. 65 shows a method of forming metal wiring using the apparatus shown in FIG. 64.

FIG. 66 is a view showing a method of forming connection terminals of metal wiring using the apparatus shown in FIG.

Fig. 67 is a view showing the semiconductor device in Embodiment 14 of the present invention (shown are two semiconductor devices sandwiched in the groove immediately after the supporting plate is removed).

FIG. 68 is a view showing a state in which an insulating film pattern made of polyimide or the like is formed in the manufacture of the semiconductor device of FIG. 67.

Fig. 69 is a view showing a state in which metal wirings are formed by the gas deposition method.

Fig. 70 is a view showing a state sealed with a sealing resin.

Fig. 71 is a view showing the semiconductor device in accordance with the fifteenth embodiment of the present invention (shown two semiconductor devices sandwiched by a groove immediately after the supporting plate is removed).

FIG. 72 is a view showing a state in which the pattern of the sealing resin is formed by screen printing, for example, in the manufacture of the semiconductor device shown in FIG.

73 is a view showing a state in which metal wirings are formed by a gas deposition method.

74 is a diagram showing a semiconductor device having a two-layer structure in accordance with a sixteenth embodiment of the present invention.

FIG. 75 shows a semiconductor device of Embodiment 17 of the present invention (shown are two semiconductor devices sandwiched between grooves immediately after the supporting plate is removed).

FIG. 76 is a view showing a state in which a metal film is formed by vapor deposition or the like in the manufacture of the semiconductor device shown in FIG. 75.

77 is a view showing a state where a resist pattern is formed.

Fig. 78 is a view showing a state where metal wiring is formed by electroplating.

79 is a diagram illustrating a state in which a resist pattern is removed.

80 is a view showing a state where the metal film is etched away using the metal wiring as a mask.

Fig. 81 shows a state of being sealed with a sealing resin.

Fig. 82 shows a semiconductor device in Embodiment 18 of the present invention (shown are two semiconductor devices sandwiched in a groove immediately after the supporting plate is removed).

FIG. 83 is a view showing a state in which a second resist pattern is formed in the manufacture of the semiconductor device shown in FIG. 82.

FIG. 84 is a view illustrating a state in which an upper electrode terminal is formed by second electroplating in a second resist pattern opening.

85 is a diagram illustrating a state in which a resist pattern is removed.

86 is a view showing a state sealed with a sealing resin.

FIG. 87 is a view showing a modification of the semiconductor device according to the eighteenth embodiment of the present invention (shown are two semiconductor devices sandwiched between grooves immediately after the supporting plate is removed).

88 is a diagram showing the semiconductor device according to the nineteenth embodiment of the present invention.

89 is a diagram showing the first modification of the semiconductor device in Example 19 of the present invention.

90 is a diagram showing the second modification of the semiconductor device in Example 19 of the present invention.

91 is a view showing the third modification to the semiconductor device according to the nineteenth embodiment of the present invention.

92 is a view showing the fourth modification of the semiconductor device of Example 19 of the present invention.

93 is a view showing the fifth modified example of the semiconductor device according to the nineteenth embodiment of the present invention.

94 is a diagram showing the manufacturing method of the semiconductor device of Example 20 of the present invention.

95 is a cross-sectional view showing a conventional semiconductor device using a lead frame.

96 is a cross sectional view of a step of forming circuit regions of a plurality of semiconductor chips on a wafer in the manufacture of the conventional semiconductor device of FIG.

97 is a cross-sectional view of the step of separating the wafer of FIG. 96 into respective semiconductor chips.

98 is a cross-sectional view of the step of mounting the separated semiconductor chip of FIG. 97 in a lead frame.

99 is a cross-sectional view of a step of connecting an electrode and an external lead of the semiconductor chip of FIG. 98.

100 is a cross-sectional view of the resin sealing step of the semiconductor device of FIG.

Fig. 101 is a diagram showing a conventional semiconductor device which has been miniaturized.

Fig. 102 is a diagram showing another conventional semiconductor device aimed at miniaturization.

Fig. 103 is a view showing the stacked structure of a conventional semiconductor device.

Fig. 104 is a diagram showing another stacked structure of the conventional semiconductor device.

The semiconductor device of the present invention includes a semiconductor chip having a predetermined function and a semiconductor chip having an electrode on one main surface, a metal wiring having one end connected to the electrode and the other end connected to the outside, and at least a semiconductor chip. An insulator covering one main surface of the substrate is provided. In this semiconductor device, the connecting terminal at the other end of the metal wiring is a portion formed while maintaining a state of being integrated with the other portion of the metal wiring, and the connecting terminal is formed at the bottom surface on the side opposite to the upper surface of the insulator on one main surface side. Exposed (first phase).

According to the above structure, the connecting terminal which is a part formed integrally with the metal wiring is exposed from the bottom part. For this reason, at the time of manufacture, the said electrode, for example, an imaginary conductive plate or support plate, and the connection terminal integrally formed with the metal wiring are connected by the terminal part continuous with a metal wiring. The connection terminal and the terminal on the electrode are formed integrally with the metal wiring. The connecting terminal and the terminal on the electrode may be formed while maintaining a state of being integrated with other parts of the metal wiring in the step of arranging the metal wiring. In that case, a process may be performed to the part used as a connection terminal, and you may deform | transform. For this reason, (1) there is no seamless connection between a connection terminal and the other part of a metal wiring, and (2) a composition becomes substantially the same as the other part of a connection terminal and a metal wiring. As for the shape, the connecting terminal and the terminal on the electrode may naturally differ from the metal wiring. For example, when metal wiring is used as a wire, the connection terminal is processed in the connection process to form a ball bond, a stitch bond, or the like. In addition, when forming metal wiring by a gas deposition method or a plating method, a connection terminal can be formed in arbitrary shape suitable for a connection part. Said virtual conductive plate or support plate can be removed in a later process.

For example, when metal wiring is comprised by wire, the following processes can be performed in a wire bonding process.

(a) The tip of the wire is joined to the electrode of the semiconductor chip to form a first pressure contact. Subsequently, a second press contact portion may be formed in the virtual conductive plate in the same manner, and the wire continuous to the supply source inside the bonding tool may be cut. When forming the second press contact portion on the virtual conductive plate, the wire is crushed to have a shape wider than the wire state. For this reason, it can be used as a connection terminal. By adjusting the wire bonding conditions, it is also possible to make the width of the wire larger than the pressure contact portion under normal pressure welding conditions. In addition, in the ultrasonic wire bonding of aluminum wire, the same press contact part is formed also in the aluminum wire junction part on a semiconductor chip electrode, and the aluminum wire junction part on a support plate. Also in this case, the aluminum wire of the pressure-contacting portion is simply connected to a virtual conductive plate, but is processed in a wide width. For this reason, it is easy to use as a connection terminal. In addition, it is also possible to adjust the conditions of the ultrasonic wire bonding, and to process a wider than the width of the normal pressure contact portion.

(b) A tip portion of the wire may be melted to form a bulk portion, a ball bond may be formed on a virtual conductive plate, and a stitch bond may then be formed on an electrode of a semiconductor chip.

(c) A tip portion of the wire may be melted to form a bulk portion, a ball bond may be formed on an electrode of a semiconductor chip, and a stitch bond may then be formed on a virtual conductive plate.

In any of the cases (a), (b), and (c), except for the virtual conductive plate in the subsequent step, the end of the metal wiring processed and connected to the conductive plate can be used as a connection terminal.

As a result, a semiconductor device miniaturized by not using a lead frame can be manufactured by a very simple manufacturing process. As a result, it is possible to obtain a miniaturized semiconductor device with high reliability at low cost.

In the semiconductor device of the present invention, the metal wiring is a wire formed by wire bonding, and the connecting terminal can be a bulk connecting terminal in which a portion of the wire is processed as the wire is continuous to form a bulk (second). conjuncture).

In this configuration, the semiconductor device has a connection terminal manufactured in the step (b) above. Since the connection terminal manufactured by the process of said (b) has planar size, it has a wide size, and it is used as a connection terminal, and connection is easy. In addition, by stacking two bulk terminals, it is easy to produce a laminated structure by exposing to an upper surface.

In the semiconductor device of the present invention, the metal wiring and the connecting terminal can be formed by any one of a gas deposition method and a plating method (third phase).

As described above, by using any one of the gas deposition method and the plating method, it is not necessary to process the connection terminal as in the case of using a wire. It can be formed in arbitrary shapes with a connection terminal and the terminal on an electrode. However, in the case of forming the metal wiring by the gas deposition method or the plating method, since it cannot extend in the air like a wire, it is formed on the support layer covering at least one main surface of the semiconductor chip. A durable insulating film may be used for this support layer as it is as a protective layer of a semiconductor chip. As the support layer, a resist film may be disposed to form a metal wiring by the gas deposition method or the plating method, and then the resist film may be removed and a durable insulator may be formed thereafter.

In addition, in the case of forming the metal wiring by the plating method, an electroplating method is usually used, so that a metal film serving as a cathode is formed on the support layer.

In the semiconductor device of the present invention, the surface exposed by the connection terminal can be configured to be positioned to protrude outward from the main surface on the back side opposite to the one main surface of the semiconductor chip.

According to this configuration, the exposed portion of the connection terminal is positioned outside the semiconductor chip. For this reason, when the above-mentioned semiconductor device is assembled into a module or a product, there is no need to increase the height accuracy of the semiconductor chip, and it becomes very easy to connect the connection terminal to the electrode of the circuit board.

In the semiconductor device of the present invention, a plate can be disposed in contact with the main surface of the back surface side opposite to one main surface of the semiconductor chip, and the plate can be exposed from the bottom surface (fifth aspect).

By making the plate material a heat conductor, it is possible to avoid causing heat to dissipate in the semiconductor chip. In addition, the mechanical strength of the semiconductor device can be increased. Therefore, this semiconductor chip can be operated with high reliability. Therefore, after the structure is simplified, the size is reduced, and the price is reduced, it is possible to obtain a highly reliable semiconductor device.

In the semiconductor device of the present invention, the plate can be made of a metal plate (sixth aspect).

By this structure, a board | plate material with high strength can be formed inexpensively. As a result, it is possible to increase the mechanical strength of the semiconductor device so as not to cause heat to get to the semiconductor chip. Aluminum, copper, and their alloys can be used for the material of the metal plate.

In the semiconductor device of the present invention, a solder member can be deposited on the exposed portion of the connection terminal (seventh aspect).

By this structure, connection of a connection terminal and another terminal can be performed more easily, and connection strength can be raised.

In the semiconductor device of the present invention, a solder material can be deposited on an exposed portion of the plate (eighth aspect).

This configuration makes it possible to firmly connect the heat sink to the plate, to dissipate much of the heat of the semiconductor chip, and to improve the reliability of the operation of the semiconductor chip. For this reason, it is possible to obtain a high operational reliability even when a multi-layer structure is formed and high density mounting.

In the semiconductor device of the present invention, by increasing the height of the connection terminal at the other end of the wire, the upper portion on the opposite side to the bottom surface of the connection terminal can be exposed from the upper surface of the insulator. If such a structure can be provided, two or more of these semiconductor devices may be stacked to obtain a semiconductor device having a stacked structure. As a result, it becomes possible to mount the semiconductor device of a simple structure very simply and with high density. In this manner, a semiconductor device in which the top surface, the bottom surface and the terminals are exposed at the same position in plan view is referred to as a semiconductor device with the same vertical position terminal.

In the semiconductor device of the present invention, another upper connection terminal can be provided on the connection terminal (a ninth aspect).

By superimposing two or more semiconductor devices having the above-described structure, that is, semiconductor devices with the same upper and lower positions in the order, a highly compact semiconductor device (semiconductor module) can be obtained.

In the semiconductor device of the present invention, the upper wiring terminal is formed such that the metal wiring and the connecting terminal are formed by any one of the gas deposition method and the plating method, and are continuously formed on the connecting terminal so as to be higher on one main surface side of the semiconductor chip. It can be provided (phase 10).

With the above structure by the gas deposition method, the upper connecting terminal can be formed in the metal wiring forming step without separately providing a step for forming the upper connecting terminal in wire bonding.

In the plating method, a step for forming an upper connection terminal in wire bonding is provided separately. However, in order to form a plating pattern by photolithography, many more fine connection terminals can be formed with higher precision.

In the semiconductor device of the present invention, the above-described stacked structure semiconductor device is a unit semiconductor device, at least two of the unit semiconductor devices are stacked, and the connection terminal of one unit semiconductor device is connected to the other unit semiconductor device. It may be connected to an upper connection terminal (phase 11).

With this configuration, a laminated semiconductor device (layered semiconductor module) having connection terminals on the upper and lower surfaces can be obtained. This laminated semiconductor device has a very dense structure, and therefore, it is possible to manufacture it with high reliability and at low cost. The stacked semiconductor devices stacked in this order are called forward stacked semiconductor devices.

The semiconductor device of the present invention can be provided on another electrode in contact with an electrode (12th aspect).

When the semiconductor device of the above constitution has surface symmetry with respect to the plane mirror parallel to the main surface described above, the laminated semiconductor device is formed by facing the two semiconductor devices of the above constitution with each other or with the upper surfaces. It's simple to get. This semiconductor device is referred to as a semiconductor device with terminal at different positions up and down, regardless of whether the surface symmetry is present or not.

In addition, when the semiconductor device does not have the surface symmetry, a semiconductor device having the arrangement of the surface symmetry relation with respect to the semiconductor device is prepared. The laminated semiconductor device can be obtained simply by bringing the semiconductor device with terminals at different positions up and down and the semiconductor device that is face-symmetric to the bottom surface or the top surface to face each other. The multilayer semiconductor device described above is called an inverted semiconductor device.

In the semiconductor device of the present invention, the metal wiring can be provided by any one of a gas deposition method and a plating method, and can be provided with an electrode terminal on which the electrode is connected in succession (13th aspect).

As described above, when the metal wiring is formed by the gas deposition method, the upper connecting terminal can be formed in the metal wiring forming step without providing a step for forming the upper connecting terminal in wire bonding. have. Moreover, as a plating method, the process for forming the terminal for upper connection in wire bonding is provided separately. However, in order to form a plating pattern by photolithography, more fine connection terminals can be formed with higher precision.

In the semiconductor device of the present invention, in the semiconductor device having the metal wiring formed by any of the gas deposition method and the plating method, the metal wiring can be exposed at the highest position on the surface side opposite to the bottom portion. (Phase 14).

The metal wiring formed by the gas deposition method or the plating method is formed on the supporting layer on which the foundation is based. For this reason, if at least the highest position of the part on a support layer is exposed, it can be used as a terminal for a connection.

The semiconductor device of the present invention comprises a surface symmetric semiconductor device and a unit semiconductor device having a unit semiconductor device and a plane symmetrical arrangement with respect to a plane in which the semiconductor device with terminals above and below different positions is disposed as parallel with one main surface. Equipped. And a top butt connection structure in which the electrode terminal of the surface symmetric semiconductor device is connected and laminated to the electrode terminal of the unit semiconductor device, and a bottom butt connection structure in which the connection terminal of the surface symmetric semiconductor device is connected and laminated to the connection terminal of the unit semiconductor device. Any one of these connection structures can be provided (phase 15).

With this configuration, an inverted stacked semiconductor device can be obtained simply. This inverted semiconductor device is compact, has high reliability, and can be manufactured at low cost. In addition, when at least the highest part of the metal wiring formed by the gas deposition method or the plating method is exposed, the exposed portions may be directly contacted and electrically connected, or electrically connected between the two exposed parts through solder. You may connect.

In addition, in the above-described surface symmetric semiconductor device, when the unit semiconductor device itself has the above-described surface symmetry (phase 16), the inverted stacked semiconductor device can be formed by inverting and stacking the unit semiconductor devices.

In addition, even when two or more inverted stacked semiconductor devices described above are provided, and the connection terminal of the first inverted semiconductor device and the connection terminal of the second inverted semiconductor device are included in the above-described configuration of the present invention. do. In this case, in the case of the top butt structure, the connection terminal of the first inverted semiconductor device and the connection terminal of the second inverted semiconductor device are connected, and in the case of the bottom butt structure, the first terminal of the first inverted semiconductor device is The second auxiliary connection terminal and the second auxiliary connection terminal of the second inverted stacked semiconductor device are connected.

In addition, when the total number of semiconductor devices is an odd number, semiconductor devices which cannot be paired are arranged in the end layer. Such a laminated semiconductor device is also included in the semiconductor device of the present invention. In this case, any one of the first unit semiconductor device and the surface symmetric semiconductor device is further provided as a single layer semiconductor device, and the connection terminal thereof is a layer of the end of the inverted multilayer semiconductor device having a surface symmetry relationship with the end layer semiconductor device. It is connected to the connection terminal.

The semiconductor device of the present invention can be configured to further expose the outer end of the connecting terminal from the side surface of the insulator (phase 17).

This structure makes it possible to easily form a laminated semiconductor device by using a wall circuit board or the like on the side of the semiconductor device. For this reason, it becomes possible to obtain a semiconductor device of a laminated structure without forming a connection terminal separately.

The semiconductor device of the present invention includes at least two semiconductor devices having exposed terminals connected to the side portions with exposed sides, and wall circuit boards intersecting the surface of the semiconductor chip including circuit wiring therein. The exposed side of the connection terminal of the semiconductor device is connected to the wall circuit board, and the semiconductor device can be mounted in a layered manner (S18th aspect).

By this structure, a laminated structure can be obtained simply and it becomes possible to perform high density mounting easily. The wall circuit boards described above are not limited to one, but may be two or more, three or four. It may be arrange | positioned so that the four periphery of a semiconductor device may be enclosed. The wall circuit board is usually arranged in the vicinity where the electrodes are arranged.

In the semiconductor device according to the present invention, the wall-shaped circuit board is not arranged on at least one side surface and the wall-shaped circuit board is not connected. The circuit board according to the laminated surface of the semiconductor device is connected to the connection terminal and the side surface thereof. It can be set as the structure which protrudes in planar form from (19th stage).

With this configuration, the connection using not only the connection through the terminal of the wall circuit board but also the wiring of the circuit board arranged on the above-described flat can be used.

In the semiconductor device of the present invention, the semiconductor device is planar, and at least one side of the semiconductor device does not have a wall circuit board disposed thereon, and the heat sink according to the stacking surface of the semiconductor device is thermally connected with the semiconductor chip. Can be configured to protrude in a flat plate form from the side surface (the twentieth aspect).

By this structure, heat can be dissipated from the semiconductor chip to ensure high reliability operation. In addition, in the above-described configuration, the thermal conductive plate may be disposed in contact with the rear surface of the semiconductor chip, or may not be disposed.

In the method of manufacturing a semiconductor device of the present invention, two or more semiconductor devices are manufactured from a semiconductor substrate having two or more semiconductor circuit regions arranged on one main surface, each having a predetermined function and having an electrode for electrical connection with the outside. That's how. The manufacturing method includes a step of joining a support plate to a main surface side opposite to one main surface of a semiconductor substrate, and a support plate around the semiconductor circuit region so as to divide two or more semiconductor circuit regions into individual semiconductor circuit regions. A step of forming a groove so as to be exposed, a step of connecting the electrode and the support plate exposed in the groove with a metal wiring, and a step of removing the support plate (phase 21).

According to this structure, in the process of connecting with a wire, the semiconductor chips (semiconductor circuit region) are not separated into individual pieces, and each semiconductor chip is connected to the support plate of the groove bottom part while being supported by the support plate. When the above connection process is performed by wire bonding, for example, the electrode and the connection terminal of the semiconductor chip are wire bonded. For this reason, it is not necessary to perform position alignment for every conductor element, and production efficiency can be improved significantly. Therefore, it is very excellent in the point of mass productivity.

Moreover, it is excellent also in the handling at the miniaturization which becomes a problem when manufacturing a semiconductor package for every individual semiconductor device.

In addition, a semiconductor device having a stacked structure can be obtained by stacking semiconductor devices of the same size without requiring complicated processing steps. At this time, there is no need to use a spacer or a special circuit board. For this reason, the semiconductor device of a laminated structure can be obtained which is not limited to the number of layers which can be laminated | stacked.

In the manufacturing method of the semiconductor device of this invention, in the process of connecting an electrode and a support plate with a wire, it can connect the thing made into the bulk by melting the wire of the vicinity of the part connected to a support plate by wire bonding. Phase 22).

By this structure, a bulk connection terminal can be formed simply by forming a ball bond in a support plate at the wire bonding process. Formation of the ball bond is not particularly difficult. In wire bonding, first, a discharge is generated at the wire tip in the wire bonding apparatus, and the wire tip is melted to form a bulk portion (ball). Next, the bulk portion is brought into contact with the support plate to be joined. Thereafter, the wire is connected to the electrode of the semiconductor chip while supplying the wire to form a stitch bond having almost no bulk portion. In the formation of the ball bond, it is common to carry out in the order of first forming the ball bond on the support plate as described above. However, the conditions of the wire bonding may be particularly adjusted to initially form a stitch bond on the electrode of the semiconductor chip, and then a ball bond may be formed as a bulk portion on the support plate while supplying the wire.

This configuration makes it possible to manufacture a compact and compact semiconductor device very simply and inexpensively.

Further, in the step of forming the groove, the groove can be formed in the support plate through the semiconductor substrate. For this reason, the connection terminal of the said wire can be easily connected to a groove bottom part. It is preferable to perform an etching process, a plating process, or a combination of these processes on the surface of the support plate of the groove bottom to facilitate and assure the connection in wire bonding.

In addition, when the supporting plate is removed by etching, the connection terminal can be made to protrude below the semiconductor chip. For this reason, when assembling a laminated semiconductor device (layer semiconductor module) or a product, the said connection terminal can be easily connected to another terminal.

Further, when the holes or through-holes are arranged in advance on the support plate and the end portions of the wires are connected, the end portions of the wires can be pushed down by a torch and sandwiched in the holes or through-holes to be joined. In addition, when connecting simply without providing a hole or a through hole in advance, a part of the wire end can be inserted and joined to a support plate by forcing by a torch. In the case where the above connection method is used, the end of the wire is formed to protrude to the outside of the layer by using etching when the support plate is removed in a later step. As a result, the connection terminal can be connected to another terminal more easily.

Furthermore, in the manufacturing method of the said invention, after removing the predetermined part of a support plate, the process of plating at least one of the connection terminal of a wire exposed to the back surface, and a board | plate material can be further provided. This configuration makes it easy to connect the terminals of the circuit board to the connection terminals or to connect the heat sink to the plate.

In addition, in the manufacturing method of the present invention, the support plate includes a plate material (heat conduction plate) disposed between the semiconductor substrate and the support plate so as to correspond to an area surrounded by the grooves formed in the groove forming step. The step of joining the support plate to the main surface side opposite to the main surface may include a step of joining the plate member and the support plate and a step of joining the plate member and the semiconductor substrate. By this structure, it is possible to increase the mechanical strength of the semiconductor device and to prevent the semiconductor chip from malfunctioning due to the heat of the semiconductor chip. The plate member is connected to a heat sink or the like.

In the method of manufacturing a semiconductor device of the present invention, a step of covering one main surface of the semiconductor substrate with an insulating film is provided before the step of wiring with metal wiring. In the step of connecting the electrode and the support plate with metal wiring, the gas deposition method and By any of the plating methods, the insulating film, the electrode, and the metal film which contact | connects on a support plate can be formed (a twenty-third aspect).

Naturally, the insulating film does not cover the electrodes of the semiconductor chip. This insulating film may be removed after formation of a metal film by a gas deposition method or a plating method, and then an insulating film may be formed, or may be used as a protective insulating film of a semiconductor chip as it is. According to the above method, it becomes easy to make a connection terminal arbitrary shape.

In the manufacturing method of the semiconductor device of the present invention, in the step of joining the support plate to the back surface main surface opposite to one main surface of the semiconductor substrate, the members to be joined can be joined using the anodic bonding method (phase 24). .

According to this structure, a support plate etc. can be joined, without using another material, such as an adhesive agent. For this reason, the fixing structure of a support plate can be formed simply, and manufacturing cost can be reduced.

In addition, by using a metal plate for the support plate and the auxiliary plate, this semiconductor device can be manufactured at low cost. However, as long as the support plate is electrically conductive and the plate material is thermally conductive, it is not limited to the metal plate, and any material may be used.

In the semiconductor device manufacturing method of the present invention, in the step of forming the grooves, the grooves can be formed using a dicing saw (a twenty-fifth aspect).

This configuration makes it possible to form the grooves accurately and inexpensively very efficiently.

In the method of manufacturing a semiconductor device of the present invention, in the process of connecting with metal wiring, the electrode positions of two semiconductor chips facing each other with grooves interposed therebetween are shifted from each other according to the extending direction of the grooves, and one semiconductor chip is provided. The metal wires extending from the electrodes of the electrodes are connected to the support plate at a position close to the other semiconductor chip in the groove, and the metal wires extending from the electrodes of the other semiconductor chip are connected to the support plate at a position close to the other semiconductor chip in the groove. (Phase 26).

With this structure, the semiconductor device of the present invention can be formed even when the space between the semiconductor chips is not widened, that is, even in the case of narrow grooves.

In the method for manufacturing a semiconductor device of the present invention, a step of sealing a semiconductor substrate with an insulator is provided, and in the sealing step, a fluid polymer resin can be coated and coated in a predetermined region by using a screen printing method. Phase 27).

By using the screen printing method, it is possible to precisely form the pattern of the fine polymer resin.

In the method of manufacturing a semiconductor device of the present invention, at the time of formation of the pattern of the polymer resin, the polymer resin is disposed in a gap between the connecting terminal connected to the semiconductor chip in the groove and the semiconductor chip is provided therebetween. Instead, in the step of removing the support plate, each semiconductor device is separated separately according to the gap portion (phase 28).

By this structure, when the semiconductor device is finally divided into pieces, the sealing resin can be easily separated without cutting or deforming the sealing resin.

In the method of manufacturing a semiconductor device of the present invention, in forming a pattern of a polymer resin, a semiconductor chip is provided in a gap portion between a connection terminal connected to a semiconductor chip in a groove and interposed between the semiconductor chip and the semiconductor chip. In the step of removing the support plate without disposing the polymer resin except the corner portions associated with three or more corners, each semiconductor device can be connected by the polymer resin disposed on the corner portion (phase 29).

This configuration makes it possible to transport or store the miniaturized semiconductor device on a wafer basis, thereby facilitating handling.

In the step of removing the support plate, at least one of mechanical polishing and chemical mechanical polishing (CMP) may be used to remove a predetermined portion of the support plate. In addition, when raising the precision of the final position of a support plate removal, in the process of removing the said support plate, the predetermined part of a support plate can also be etched and removed.

In the manufacturing method of the semiconductor device of the present invention, in the step of sealing with an insulator, the entire surface of the semiconductor substrate is covered with an insulator, and then, in one of the steps, a predetermined portion of the insulator is removed by a dicing saw to make the semiconductor circuit. Each area can be separated (Stage 30).

By this structure, insulator sealing can be performed easily, especially without having a resin pattern formation means. As a result, it is possible to obtain a variety of manufacturing methods.

In a method of manufacturing a semiconductor device according to another aspect of the present invention, two or more semiconductors are provided from a semiconductor substrate having two or more semiconductor circuit regions arranged on one main surface, each having a predetermined function and having electrodes for electrical connection with the outside. Method of manufacturing the device. The semiconductor device manufacturing method includes a process of cutting a semiconductor substrate into individual semiconductor circuit regions, a step of joining a support plate to a main surface side opposite to one main surface of the semiconductor substrate, and a support plate exposed in the electrode and the groove. And a step of removing the supporting plate from the metal wiring (phase 31).

By this structure, the electrode and support plate of the separated semiconductor chip can be connected by metal wiring. For this reason, many cases can be manufactured using a conventional manufacturing line as it is.

In the manufacturing method of the semiconductor device according to the other aspect, in the step of connecting the electrode and the support plate by metal wiring, the wire in the vicinity of the portion to be connected to the support plate can be melted and connected to the support plate by wire bonding. (Phase 32).

By this structure, a bulk connection terminal can be easily formed using the universal means of wire bonding.

In the method of manufacturing a semiconductor device according to the other aspect, a step of covering one main surface of the semiconductor substrate with an insulating film before the step of wiring with metal wiring, and in the step of connecting the electrode and the support plate with metal wiring, the gas deposition method And a metal film can be formed in contact with the insulating film, the electrode, and the support plate by either of the plating methods (the thirty-third aspect).

By this method, wirings and connecting terminals can be efficiently formed on the separated semiconductor substrate. Naturally, the insulating film covering one main surface of the semiconductor substrate does not cover the electrode of the semiconductor chip.

In the above-described method of manufacturing a semiconductor device, one of the electrodes and the connection terminal can be melted to form a bulk terminal by melting one end of the metal wiring by the application of the wire bonding method so as to be connected to them. conjuncture).

By this structure, the semiconductor device of a laminated structure can be formed. That is, in the case where the stud bump is formed on the connection terminal, the semiconductor device with the vertical connection terminal of the same position can be obtained. In the case where the stud bumps are formed on the electrodes, semiconductor devices with different connection terminals up and down can be obtained.

In the method for manufacturing a semiconductor device described above, in the step of connecting with a metal wiring, the connection is extended in a direction away from the supporting plate by either the gas deposition method or the plating method so as to be connected to either the electrode or the connection terminal. For use can be formed (phase 35).

By this method, a semiconductor device suitable for assembling a semiconductor module in which a plurality of semiconductor devices are stacked can be easily formed.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising two or more semiconductor circuit regions each having at least two semiconductor circuit regions each having a predetermined function to facilitate electrical connection with the outside. In order to manufacture a semiconductor device, a manufacturing method including a method of inspecting electrical characteristics of the semiconductor circuit region. In this manufacturing method, a step of joining a support plate to a main surface side opposite to one main surface of a semiconductor substrate, and the support plate around the semiconductor circuit region so as to divide two or more semiconductor circuit regions into individual semiconductor circuit regions. And forming a groove so that it is exposed. Moreover, this manufacturing method includes the process of connecting the electrode and the support plate exposed in the groove | wire with a wire, and the process of joining an upper surface support plate to the surface on the opposite side to the surface in which the support plate was arrange | positioned. This manufacturing method includes a step of performing a stylus test on the connection terminal from which the supporting plate is removed and exposed to determine the quality of electrical characteristics (phase 36).

By using this manufacturing method, the semiconductor chip can be inspected independently for each semiconductor chip without being short-circuited by the conductive support plate. In addition, during this inspection, many semiconductor chips can be collectively inspected in the same manner as the semiconductor chips arranged on the wafer.

(Example of the invention)

EMBODIMENT OF THE INVENTION Next, the Example of this invention is described using drawing.

(Example 1)

Referring to FIG. 1, the semiconductor chip 1a and the wire 2 are sealed in the insulator resin 4. One end 2b of the wire 2 is connected to the electrode 3 of the semiconductor chip 1a to form a so-called stitch bond. In addition, the other end of the wire is processed to form a bulk connection terminal 2a, which is exposed from the sealing resin 4. The exposed surface of the connection terminal 2a protrudes outward from the semiconductor chip 1a.

According to this configuration, the connecting terminal can be formed by simply melting the end of the wire. As described above, since the structure is very simplified, (a) downsizing is easy, and (b) production efficiency is greatly improved, and manufacturing cost can be reduced. In addition, since the connection terminal 2a protrudes outward from the semiconductor chip 1a, the connection terminal 2a can be easily and reliably connected without increasing the dimensional accuracy of the semiconductor device by that much. have.

(Example 2)

2, the present embodiment is characterized in that the plate 6 is disposed on the back surface of the semiconductor chip 1a. In many cases, a metal plate can be used for this board | plate material. This sheet material can be easily formed by changing a part of the manufacturing method of the semiconductor device mentioned later.

By arranging the plate, the mechanical strength can be improved, such as increasing the rigidity of the semiconductor device. Moreover, the heat dissipation from a semiconductor chip can be improved by using the board | plate material with good thermal conductivity, such as a metal plate.

(Example 3)

3, the present embodiment is characterized in that the solder coating 7 is formed on the surface exposed on the rear surface of the connecting terminal 2a. By the formation of the solder coating 7, the connection to the terminals of the circuit board and the like can be easily and surely achieved, and high connection strength can be obtained.

(Example 4)

4, the present embodiment is characterized in that the solder coating 8 is also applied to the metal plate 6 disposed on the back surface of the semiconductor chip in addition to the connecting terminal as the metal plate. By forming this solder coating 8, when it is mounted on a circuit board, adhesive strength and heat dissipation can be improved.

(Example 5)

5-20 is a figure explaining the manufacturing method of the semiconductor device of Example 5 of this invention. By this manufacturing method, the semiconductor devices of the first to fourth embodiments can be manufactured. First, as shown in Fig. 5, a pattern in which circuit regions are arranged for each region of the semiconductor chip on the main surface of the wafer (semiconductor substrate) is formed. This circuit region has a predetermined function and includes an electrode 3 for electrical connection with the outside. The back side of the wafer 1 may be ground, may be adjusted to a predetermined thickness, or may not be ground.

6, the support plate 5 is bonded to the back surface of a wafer. As this support plate, a metal plate such as aluminum can be used. It is preferable to use an anodic bonding method for this bonding. However, it is also possible to bond using an adhesive. Subsequently, as shown in FIG. 7, the groove 11 is formed so that the periphery of the circuit area of each semiconductor chip reaches a support plate. For example, a dicing saw can be used for the formation of the groove 11. The groove 11 penetrates the wafer 1 and forms shallow grooves in the support plate 5 and the support plate.

The exposed surface of the supporting plate 5 may be subjected to an etching treatment, a plating treatment, or a combination thereof in order to facilitate connection of the wire in the wire bonding of the next step. The etching treatment to the exposed portion of the support plate, the plating treatment or a combination thereof can be easily performed by a conventional treatment method. The above process is effective not only to facilitate and assure the connection of wires, but also to increase the strength of the connection portion.

Next, the so-called wire bonding method connects the electrode 3 of the semiconductor chip and the supporting plate 5 of the groove bottom to the wire 2 (FIG. 8). Here, a part of the wire connected to the groove bottom part is melted and spliced to form a so-called ball bond. In the wire bonding method, first, a discharge is generated at the tip of the wire in the wire bonding apparatus to melt, thereby forming the bulk portion (ball) 2a. Next, as shown in FIG. 9, it connects to the support plate 5, growing the ball 2a suitably. Next, the wire 2 is connected to the electrode 3 of the semiconductor chip 1a while supplying the wire from the torch 15 to form a stitch bond. Further, the wire bond conditions may be adjusted to initially form a stitch bond on the electrode, and then a ball bond may be formed on the support plate.

Further, a support plate having a through hole arranged at a predetermined position is bonded to each other. At the time of joining to the support plate in the wire bonding, the wire is strongly pushed through the through hole so that the end of the wire is inserted into the support plate and joined. By using such a manufacturing method, after the support plate is removed by etching, the end of the wire protrudes from the back surface of the semiconductor device, so that joining with other connection terminals can be facilitated and assured.

Next, as shown in FIG. 10, a semiconductor chip and a wire are coat | covered with resin which is an insulator. When covering with resin, resin is not arrange | positioned in the clearance gap S of the connection terminal of an adjacent semiconductor chip by screen printing a thermosetting polymer material with fluidity. However, depending on the circumstances, the semiconductor device is not separated into pieces at the intersection of the grooves and the like by removing the support plate. Moreover, you may arrange | position resin in the clearance gap S according to a situation. Thereafter, although not shown, heat treatment is then performed to cure the thermosetting polymer material.

Next, as shown in FIG. 11, the support plate on the back surface of a semiconductor device is removed by wet etching. In addition to wet etching, this support plate may be removed by mechanical polishing or chemical mechanical polishing (CMP). However, when mechanical polishing or CMP is used, the exposed surface of the connecting terminal and the back surface of the semiconductor chip are the same, and the connecting terminal cannot protrude outward.

Next, the resin disposed in the groove intersection and the like is removed to form a semiconductor device that is separated into pieces. However, in the case where the resin is not entirely disposed in the gap S including the groove intersections, the semiconductor device is separated by removing the support plate, so that the step of removing the resins in the groove intersections is not necessary.

Next, as shown in FIG. 12, solder | pewter coating is performed by the plating method to the connection terminal exposed to the back surface. This solder coating can be used as a bonding material. The above solder coating need not be limited to the plating method, and other coating methods can be used. Next, the solder coating 7 is connected to the electrode 13 on the circuit board 12 (Fig. 13).

14 and 15 are cross-sectional views after the process of removing the support plate is performed by mechanical polishing or CMP rather than wet etching. In this case, as shown in FIG. 14, whether the exposed surface of the connection terminal and the back surface of the semiconductor chip are the same, or as shown in FIG. 15, a portion 5a of the support plate is left on the back surface side of the semiconductor chip. This can be used as the board | plate material 6 shown in FIG.

16 is a plan view of a step corresponding to the cross-sectional view of FIG. 6. A circuit region (semiconductor chip region) 1a in which a circuit having a predetermined function including an electrode 3 is arranged is formed on the wafer 1. The support plate 5 is joined to the back surface of the wafer 1 by anodization. After that, as shown in FIG. 17, the grooves 11 are vertically and horizontally drilled so as to penetrate the wafer from the upper surface side, and the intersection portions 11a and the like of the grooves are formed. A dicing saw can be used for formation of this groove.

Next, as shown in FIG. 18, the electrode 3 and the support plate 5 are connected by the wire 2. At this time, the wire bonding conditions are adjusted so that the bulk connection terminal 2a is formed in the connection portion with the support plate. Next, as shown in FIG. 19, it coat | covers with resin 4 except the clearance gap S between the connection terminals 2a of adjacent semiconductor devices. Moreover, resin 4a is arrange | positioned also in the position corresponding to the intersection part 11a of a groove | channel.

Next, when the supporting plate 5 is removed, a semiconductor device sealed with a resin can be obtained as shown in FIG. 20. Each semiconductor device can be connected by the resin 4a of the groove intersection portion. Fig. 21 is a plan view of the semiconductor device formed by removing the resin 4a and being separated into a back surface (I) or the like. Along the vicinity of the semiconductor chip 1a, connection terminals 2a formed from wires are arranged.

By the above manufacturing method, a semiconductor device having a compact and simple structure can be obtained by a very simple manufacturing process. For this reason, it becomes possible to manufacture a semiconductor device with a high degree of integration at a low cost.

(Example 6)

22 to 24 show a method for manufacturing a semiconductor device according to the sixth embodiment of the present invention. In this embodiment, there is a feature in the structure of the semiconductor device when determining the quality of the semiconductor device. After connecting the support plate and the electrodes of the semiconductor chip with wires and sealing them with resin (FIG. 10), as shown in FIG. 22, the inspection support plate 25 is disposed on the surface opposite to the support plate 5. A film may be sufficient as this 2nd support plate.

Next, as shown in FIG. 23, the support plate 5 is removed by wet etching. This wet etching can be substituted by mechanical polishing or CMP. Next, as shown in FIG. 24, the probe 16 is applied to the exposed connection terminal 2a, and the quality of the circuit function of a semiconductor device is judged.

By the above-described method, even after the support plate is removed, each semiconductor chip can maintain its position on the wafer. For this reason, it becomes possible to test in the state arrange | positioned on a wafer like a conventional thing, without conveying and inspecting a semiconductor chip individually. For this reason, it is possible to manufacture a miniaturized semiconductor device with a very simple manufacturing process and to efficiently test the size of the miniaturized semiconductor device in an integrated arrangement as in the prior art.

(Example 7)

25 to 28 are views for explaining the manufacturing method of the semiconductor device according to the seventh embodiment of the present invention. First, after connecting the electrode 3 of the semiconductor chip and the support plate 5 with the wire 2, and forming the connection terminal 2a in the support plate (FIG. 8), as shown in FIG. 25, the connection terminal ( The upper terminal 22 is formed in contact with 2a). The upper terminal 22 can be formed simply by using a wire bonding method. Next, except for the space | interval S, as shown in FIG. 26, resin is arrange | positioned and the semiconductor chip 1a and the wire 2 are sealed. Resin is also arrange | positioned at the intersection part of a groove | channel, and it is set as the structure which connects each semiconductor device. In addition, the upper portion of the upper terminal is exposed from the sealing resin (4).

Next, as shown in FIG. 27, the support plate 5 is removed and the semiconductor device sealed with resin is obtained. Thereafter, the resin disposed in the corner portion is cut, and the like, a semiconductor device separated into pieces is obtained as shown in FIG. 28.

This semiconductor device is a semiconductor device 52 with terminals at the same position above and below. By stacking the semiconductor devices with the same upper and lower terminal positions in order, a multilayer semiconductor device having a multilayer structure capable of miniaturization and high density mounting as shown in FIG. 29 can be obtained. By using the semiconductor device of such a multilayer structure, the integration density can be remarkably improved compared with the prior art.

(Example 8)

30 to 32 are views showing the manufacturing method of the semiconductor device according to the eighth embodiment of the present invention. First, after connecting the electrode 3 of the semiconductor chip and the support plate 5 with the wire 2, and forming the connection terminal 2a in the support plate (FIG. 8), as shown in FIG. 30, the electrode 3 An electrode terminal 23 is formed in contact with the portion of the wire to be connected to the wire. This electrode terminal 23 can also be easily formed using a wire bonding method.

Next, as shown in FIG. 31, resin is arrange | positioned also including a corner part, and a semiconductor chip and a wire are sealed with resin. At this time, the upper surface part of the above-mentioned electrode terminal 23 is exposed from resin. Next, as shown in FIG. 32, the semiconductor device sealed by resin can be obtained by removing the support plate 5. By removing the resin at the groove intersection portion, the semiconductor device can be separated into pieces (Fig. 33). This semiconductor device has upper and lower portions and connecting terminals 2a and 23, and the connecting terminals differ in planar position. Such a semiconductor device is referred to as a semiconductor device 53 with terminals at different positions. This semiconductor device has an arrangement having surface symmetry (face symmetry) with respect to a surface parallel to the main surface of the semiconductor chip.

34 is a sectional view of the structure of a semiconductor device having a two-layer structure in which bottom surfaces of two vertically positioned semiconductor devices 53 with two terminals are joined to each other. In the case of having surface symmetry, the connection terminals 2a are connected to each other in the butt of the bottom surfaces. In the case where the semiconductor device 53 with different terminal positions up and down shown in FIG. 33 does not have surface symmetry, the semiconductor device having a two-layer structure shown in FIG. 34 using two semiconductor devices 53 with different terminal positions up and down. Can't get it. In the case of not having the surface symmetry, it is necessary to prepare another semiconductor device having surface symmetry with respect to the semiconductor device of FIG. 33, and to face the other semiconductor device and the semiconductor device shown in FIG. 33 to have a two-layer structure. Therefore, in the semiconductor device of the two-layer structure shown in FIG. 34, it is preferable that the semiconductor device shown in FIG. 33 has said surface symmetry.

FIG. 35 is a cross-sectional view illustrating the configuration of a two-layer semiconductor device in which two upper and lower positions of semiconductor devices 53 with different terminals are joined to each other. In the case of having the above-mentioned surface symmetry, in the butting of the upper surfaces, the terminals 23 for upper connection are connected. Also in the case of the two-layer structure shown in FIG. 35, the semiconductor device 53 with the terminal at different positions up and down shown in FIG. 33 needs to have surface symmetry.

In the semiconductor device of the two-layer structure shown in FIGS. 34 and 35, as one integrated semiconductor device, the connection terminals to the outside are located at the same position in plan view. For this reason, this semiconductor device of two-layer structure can be superimposed in order, and the semiconductor device of four or more even-layer structure can be manufactured. For example, FIG. 36 is a sectional view of a four-layer semiconductor device in which two semiconductor devices having a two-layer structure shown in FIG. 35 are stacked and assembled in sequence.

As an example of a semiconductor device having an odd layer structure, FIG. 37 shows a sectional view of the structure of a semiconductor device having a three-layer structure. The semiconductor device shown in FIG. 37 can be regarded as (a) that the semiconductor device having the one-layer structure shown in FIG. 33 is connected to the connection terminal 23 on the lower side of the semiconductor device having the two-layer structure shown in FIG. In addition, (b) it can also be considered that the semiconductor device of the one-layer structure shown in FIG. 33 is connected to the connection terminal 2a of the upper side of the semiconductor device of the two-layer structure shown in FIG.

As described above, by providing a connection terminal exposed on the upper surface on the electrode 3 of the semiconductor chip, (A) when the semiconductor device has the above-described surface symmetry, the inverted semiconductor device and the semiconductor device are connected to each other. In addition, a multilayer semiconductor inverted semiconductor device can be obtained. (B) In the case where the semiconductor device does not have the above-mentioned surface symmetry, a semiconductor device having a surface symmetry is prepared, and the semiconductor device of the surface symmetry and the semiconductor device are connected in an inverted relationship, and the multilayer semiconductor device having a multilayer structure is provided. Can be obtained.

The semiconductor device of the multi-layered structure has a very simple configuration and can be manufactured in a small size and also in a simple and low cost.

(Example 9)

38 and 39 are views showing the manufacturing method of the semiconductor device of Example 9 of the present invention. In this embodiment, the resin is formed so that the side portion of the contact terminal 2a is exposed from the sealing resin during or after the resin sealing (Fig. 38). That is, it is good also as a shape which a side part of a connection terminal exposes a resin pattern, and as a resin pattern as shown in FIG. You can also do it. In addition, the side of the connection terminal may be exposed when cutting with a dicing saw to coat the resin on the entire surface of the wafer without dividing the resin pattern and divide the connection terminals of adjacent semiconductor devices.

39 is a plan view of the step of FIG. 38. While the resin of FIG. 19 in Example 5 covered the connection terminal, it is understood that the side of the connection terminal 2a is exposed in the present embodiment. By adopting such a configuration, after removing the support plate as shown in Fig. 40, the bottom surface and the side of the connecting terminal are exposed from the sealing resin. 41 is a plan view of the semiconductor device separated into pieces by dividing the resin in the corner portion, as viewed from the back surface side. By comparing with the top view of FIG. 21, it turns out that the side part of the connection terminal 2a is exposed.

42 is a cross-sectional view of a semiconductor device mounted on a circuit board. The connection terminal 2a of the semiconductor device is connected to the connection terminal 13 of the circuit board 12 via the solder 7.

FIG. 43 is a cross-sectional view showing the structure of the steps in which the semiconductor device shown in FIG. 40 is separated and the separated semiconductor device is mounted on the wall circuit board 32. The wired terminal 33 is provided in the wall circuit board 32, and the side part of the connection terminal 2a is connected to the terminal 33 by the solder 37. The wall circuit board can be arranged on four sides so as to surround four circumferences of the semiconductor device. In addition, it is not necessary to arrange this wall-shaped circuit board in the vicinity as needed.

In the semiconductor device of the above-mentioned multilayer structure, the connection terminal exposed to the upper part of each semiconductor device is not newly arrange | positioned, and the side part of one connection terminal 2a is used for connection with a wall-shaped circuit board. For this reason, according to this embodiment, a semiconductor device having a multi-layered structure having a simplified structure can be obtained by a very simple manufacturing method.

44 is a cross sectional view showing another semiconductor device of Example 9 of the present invention; In this multi-layered semiconductor device, when it has at least one vicinity in which the wall circuit board is not arranged, the circuit board 34 is provided so as to protrude outward from the vicinity thereof. In the vicinity of the above, the connection terminal is usually not disposed. In this semiconductor device of the multilayer structure, the connection terminal 35 wired on the circuit board 34 and the bottom surface of the connection terminal 2a are connected by solder 37. The side part of the connection terminal 2a is used for the connection of the wall-shaped circuit board 32 to the terminal 33. As shown in FIG.

By this structure, a multilayer semiconductor device having a compact and simplified structure can be obtained without further providing a terminal for external connection. This structure is superior in heat dissipation as compared with the structure of Fig. 43, and high reliability operation can be ensured after high density mounting. In addition, it is possible to make various connections with an external circuit in accordance with the structure of the semiconductor device of FIG. 43.

45 is a cross-sectional view showing still another semiconductor device of Embodiment 9 of the present invention. In this semiconductor device, the heat dissipation plate 39 is connected by solder 8 to the plate member 6 on the back surface of the semiconductor chip without arranging the circuit board arranged in the plane in the semiconductor device in FIG. Usually, it is preferable that the heat conduction plate is disposed on the back surface of the semiconductor chip in view of relaxation of processing accuracy, etc., but the heat conduction plate is not necessarily required, and a structure in which the back surface of the semiconductor chip contacts the heat sink may be used.

By this structure, since a high heat dissipation effect can be obtained, it is possible to secure a highly reliable operation after securing a very high mounting density.

(Example 10)

In Example 10 of this invention, resin is coat | covered over the whole surface, as shown in FIG. 46, without using the pattern formation means, such as at the time of resin sealing (FIG. 10) and the screen printing method in Example 5. That is, after connecting the electrode of a semiconductor chip and a support plate with a wire, the clearance gap between semiconductor devices is also included and the semiconductor chip 1a and a wire are embedded with resin. Subsequently, before removing the support plate, as shown in Fig. 47, a dicing saw having a width exposing the side of the connecting terminal 2a is formed by a dicing saw. At this time, some of the connection terminals may be cut. This separation groove is a separation groove at the boundary separated for each semiconductor device and has a depth reaching the support plate 5. Moreover, since this separation groove is formed longitudinally and horizontally, the grooves intersect at the intersection portion. After that, when the supporting plate 5 is removed, each semiconductor device is separated into pieces as shown in FIG. 48. As a result, a miniaturized semiconductor device having a simple structure capable of forming a semiconductor device having a multilayer structure using a wall circuit board can be obtained.

Moreover, the semiconductor device as shown in Examples 1-4 can be obtained by making the width | variety of the groove | channel formed by a dicing saw small in the above-mentioned manufacturing method.

By using the above-mentioned manufacturing method, since the pattern forming means such as the screen printing method is not used for resin sealing, the above-described semiconductor device can be manufactured by various manufacturing methods at low cost. In addition, by using a conductive plate such as a metal plate for the support plate 5, the electrodes are short-circuited in the steps of FIGS. 46 and 47. For this reason, when forming the groove | channel of the width which exposes the side part of an electrode, the electrostatic destruction which may arise by cutting can be prevented.

(Example 11)

Fig. 49 is a view showing the semiconductor device in Example 11 of the present invention. In FIG. 49, since it is a state just after removing a support plate, two semiconductor devices are located facing each other. While the metal wirings in Examples 1 to 10 were formed by wire bonding, in this embodiment, external connection with the electrodes 3 of the semiconductor chip is made by the metal wirings 18 formed by the gas deposition method. The feature is that the points 18a are connected.

The manufacturing method in the case of making the said connection by a gas deposition method is demonstrated below. First, as shown in FIG. 50, the wafer 1 is polished to a predetermined thickness, and then the electrode 3 is formed at a predetermined position on the surface of the wafer. Thereafter, the supporting plate 5 is bonded to the back surface of the semiconductor wafer 1 (Fig. 51). An aluminum plate can be used for the support plate 5. [0044] Further, a groove 11 reaching the support plate 5 is provided in the wafer by dicing, so that the groove divides the semiconductor chip 1a (Fig. 52). ). Subsequently, a predetermined portion of the electrode 3 and the grooves is exposed to form a resist pattern 17 so as to cover the upper surface and side surfaces of the semiconductor chip and the center of the grooves (FIG. 53).

In general, a step of covering one main surface of the semiconductor substrate with an insulating film is provided before the step of connecting with the metal wiring, and in the step of connecting the electrode and the support plate with the metal wiring, the gas deposition method or the plating method is used. , An insulating film, an electrode, and a metal film in contact with the support plate can be formed.

Naturally, the insulating film does not cover the electrodes of the semiconductor chip. This insulating film may be removed after formation of a metal film by a gas deposition method or a plating method, and then an insulating film may be formed, or may be used as a protective insulating film of a semiconductor chip as it is. According to the above method, it becomes easy to make a connection terminal arbitrary shape.

Subsequently, a metal deposition 18 from the electrode 3 to the exposed portion of the groove is formed by the gas deposition method (FIG. 54). One end 18b of the metal wiring 18 formed by the gas deposition method is connected to the electrode 3 and has a shape corresponding to the shape of the electrode 3. The other end 18a to be connected to the outside is in contact with the support plate 5, the contact portion of the support plate is flat, and this connection terminal 18a also has a shape suitable for connection. Note that, in the case of forming the metal wiring by the gas deposition method, similarly to wire bonding, the terminal portion is formed so as to have a shape different from that of the metal wiring other than the terminal portion.

Thereafter, as shown in FIG. 55, the resist pattern 17 is removed. Next, it seals with insulating resin (FIG. 56). Thereafter, the supporting plate 5 is removed to expose the connection terminal 18a of the metal wiring, thereby obtaining the semiconductor device shown in FIG. Fig. 49 shows two semiconductor chips sandwiched with grooves, but not limited to two, and needless to say, many semiconductor chips are separated and formed in the step of removing the support plate.

In addition, the structure of the semiconductor device manufactured by the wire bond can be manufactured by the gas deposition method. For example, the structure shown in FIG. 57 is a device in which a heat conductive plate for heat dissipation is disposed on the back surface of the semiconductor chip 1a. The metal wiring is a metal wiring 18 formed by a gas deposition method, and the connection terminal 18a is also formed by a gas deposition method. 58 shows a structure in which the side surface of the connection terminal 18a of the metal wiring 18 formed by the gas deposition method is exposed from the sealing resin 4. In this manner, a semiconductor device having a structure in which the side surface of the connection terminal 18a of the metal wiring is exposed can also be formed by using the gas deposition method.

As shown in Examples 1 to 10, when wire bonding is used for the formation of the metal wiring, only the cross section of the wire which is the metal wiring can be obtained. In addition, only the bulk shape of the size which can be obtained by heat-straining a wire in a wire bonding process can also be obtained also about a connection terminal. However, by using the gas deposition method instead of wire bonding as in the present embodiment, it is very easy to change the size of the connection terminal 18a and the cross-sectional area of the metal wiring electric circuit according to the bonding strength and the current density.

As described above, by using any one of the gas deposition method and the plating method, it is not necessary to process the connection terminal as in the case of using a wire. It can be formed in arbitrary shapes with a connection terminal and the terminal on an electrode. However, in the case of forming the metal wiring by the gas deposition method or the plating method, since it cannot be extended to the air like a wire, it is formed on the support layer so as to cover at least one main surface of the semiconductor chip. A durable insulating film can be used for this support layer, and it may be used as a protective film of a semiconductor chip as it is. As the support layer, a resist film may be disposed to form a metal wiring by the gas deposition method or the plating method, and then the resist film may be removed, and then a durable insulator may be formed.

In the case of forming the metal wiring by the plating method, since the electroplating method is usually used, a metal film serving as an electrode is formed on the support layer.

(Example 12)

The state of FIG. 59 is also in the state immediately after removing the support plate, similarly to FIG. 49, so that the two semiconductor devices face each other. The present embodiment is characterized in that the connection terminal 18c of the metal wiring 18 formed by the gas deposition method is exposed from the sealing resin not only at the bottom but also at the top.

In the manufacture of the semiconductor device described above, the processes up to the process shown in FIG. 53 in the eleventh embodiment are the same as those in the eleventh embodiment. That is, the same procedure as in the eleventh embodiment is performed until the step (Fig. 53) of forming the resist pattern 17 so as to expose the electrode 3 and the predetermined portion of the groove to cover the upper surface, the side surface and the center of the groove. Thereafter, the metal wiring 18 is formed by the gas deposition method. Connection terminal 18c of a bimetallic wiring is piled up so that it may protrude upwards (FIG. 60). The formation method of the metal wiring by the gas deposition method including the formation of the connection terminal 18c is described in Example 13. FIG.

Thereafter, the resist pattern is removed (FIG. 61), and then sealed with a sealing resin 4 (FIG. 62). When sealing with sealing resin, the part which protrudes upward of the connection terminal 18c is made to protrude from the sealing resin 4. As shown in FIG. After that, when the support plate 5 is removed, the semiconductor device can be obtained as shown in FIG. 59.

In the semiconductor device shown in FIG. 59, in a semiconductor device with a terminal at the same position as above and below, the semiconductor device can be obtained by stacking such semiconductor devices in the forward direction as they are. On the other hand, the connection terminal which protrudes upward can also be provided in the position of the electrode 3.

FIG. 63 is a diagram illustrating a semiconductor device provided with a connection terminal protruding upward at a position of an electrode. The semiconductor device shown in FIG. 63 is a semiconductor device with terminals at different positions up and down. In the case of such a semiconductor device with a terminal in another position, as shown in Fig. 35, the upper surfaces of the semiconductor devices in Fig. 63 are assembled with each other to form a two-layer semiconductor device. In the case of the semiconductor device having a two-layer structure as one semiconductor device, since the semiconductor device with the same upper and lower terminals is positioned as above, the stacked semiconductor device can be obtained by overlapping it in the forward direction by the intended number. However, even-numbered semiconductor devices shown in FIG. 63 are stacked.

As described above, by forming the connecting terminal protruding upward by the gas deposition method, the processing step can be simplified as compared with the case of forming two bulk terminals by the wire bonding method.

(Example 13)

In FIG. 64, in this apparatus, the evaporation raw material is introduce | transduced into the crucible 61 in the vapor deposition source chamber 66, and the evaporation source 56 heated and melted by the heating apparatus is arrange | positioned. Helium gas is introduced into the deposition source chamber 66 and filled. Since helium gas is filled, the evaporated raw material becomes very fine particles and is introduced by the pressure difference into the sample chamber 64 made of vacuum through the transport pipe 63. The fine particles are ejected from the nozzle 67 attached to the sample chamber side end of the transport pipe and adsorbed to the sample 55 disposed on the x-y-θ stage 65.

FIG. 65 is a view showing a step of blowing the deposition source from the nozzle 67 onto the sample 55 to form the metal wiring 18. Thus, when forming metal wiring by the gas deposition method, what is necessary is just to move the stage 65 relatively along parallel planes according to the nozzle 67 and the sample 55. As shown in FIG.

In addition, in order to form the connecting terminal 18c which protrudes upward, as shown in FIG. 66, the movement of the nozzle 67 and the stage 65 is stopped, and a vapor deposition source is adsorb | sucked. As a result, the connecting terminal which protrudes upwards can be formed easily.

(Example 14)

The state of FIG. 67 also shows a state immediately after the support plate is removed, and two semiconductor devices with grooves interposed therebetween. In this embodiment, when the metal wiring is formed by the gas deposition method, the electrode 3 of the semiconductor chip is exposed and the insulating film 27 covering the other portion is left in the semiconductor device. There is a characteristic. In Examples 11-13, although the resist pattern 17 played the same role, all the resist patterns were removed and it sealed by the sealing resin 4 after that.

In the manufacture of the semiconductor device described above, the processes up to the process shown in FIG. 52 in the eleventh embodiment are the same as those in the eleventh embodiment. In other words, the same operation as in the eleventh embodiment is performed until the single layer in which the groove 11 reaching the support plate 5 is provided on the wafer by dicing (Fig. 52) so as to divide the semiconductor chip 1a. Subsequently, as shown in FIG. 68, the center of the width | variety of the electrode 3 and the groove | channel is exposed, and it coat | covers with the insulating pattern 27 which consists of polyimide, for example. Next, the metal wiring 18 is formed by the gas deposition method so that the electrode 3 and the support plate of the groove bottom part are connected. Thereafter, the insulating pattern 27 is sealed with the sealing resin 4 in a state of being left. In addition, by removing the support plate, a semiconductor device can be obtained that is separated into pieces as shown in FIG. 67.

According to this embodiment, instead of the photoresist pattern, after forming a pattern of an insulating film having good physical stability and chemical stability such as polyimide or silicon oxide film, as shown in FIG. 69, metal wiring is formed by the gas deposition method. do. Thereafter, as shown in Fig. 70, the resin is sealed. According to this manufacturing method, the process of removing a resist pattern can be skipped compared with the manufacturing method using a photoresist pattern. In addition, since the periphery of wiring does not become an intermediate space before sealing with resin, the wiring is supported by polyimide or the like forming the insulating pattern 27. For this reason, it becomes possible to stably produce a semiconductor device with high yield. In addition, by the formation of the insulating pattern it is possible to finely fine wiring.

(Example 15)

FIG. 71 also shows a state immediately after removing the support plate, and shows two semiconductor devices sandwiched between the grooves. In the present embodiment, when the metal wiring is formed by the gas deposition method, the electrode 3 of the semiconductor chip is exposed to leave the sealing resin film 28 covering the other portions in the semiconductor device. It is characterized by.

In the manufacture of the semiconductor device described above, the processes up to the process shown in FIG. 52 in the eleventh embodiment are the same as those in the eleventh embodiment. That is, the same operation as in the eleventh embodiment is carried out until the step of providing the groove 11 reaching the support plate 5 in the wafer 8 by dicing (Fig. 52) so as to divide the semiconductor chip 1a. 72, the sealing resin pattern 28 is formed by screen printing, for example, by exposing the center of the width | variety of the electrode 3 and the groove | channel. Next, the metal wiring 18 is comprised by the gas deposition method so that the electrode 3 and the support plate of a groove bottom part may be connected (FIG. 73). Thereafter, the sealing resin pattern 28 is naturally left as it is, and by removing the support plate, as shown in FIG. 71, a semiconductor device can be obtained.

According to this embodiment, a sealing resin pattern is used in place of an insulating film pattern such as a photoresist pattern or polyimide. By using this sealing resin pattern, it can manufacture by a process process shorter than using any other pattern. However, the sealing resin pattern can be formed only by the screen printing method in which the dimensional accuracy is relatively inferior at the present time. For this reason, at the present time, the miniaturization of the electrode cannot be supported. In addition, since only the metal wiring formed by the gas deposition method is used for the upper part of the electrode, reliability and durability are inferior to those of the semiconductor device in the other embodiments.

(Example 16)

According to FIG. 74, the upper surface of the semiconductor device shown in FIG. 71 is opposed, the metal wiring exposed by the solder 37 is connected, and a laminated structure is formed. When the semiconductor device having this two-layer structure is regarded as one semiconductor device, there are connecting terminals at the same position at the top and bottom. Therefore, by stacking in this order, even-numbered multilayer semiconductor devices can be easily obtained. In addition, since the metal wiring is covered by the solder 37, the reliability and durability can also be improved.

(Example 17)

FIG. 75 also shows a state immediately after removing the support plate, and shows two semiconductor devices sandwiched between the grooves. This embodiment is characterized in that the metal wiring is formed by electroplating.

In the production of the semiconductor device described above, the processes shown in FIG. 72 in the fifteenth embodiment are the same. In other words, the center of the widths of the electrodes 3 and the grooves are exposed to form the same until the insulating film pattern 28 made of, for example, polyimide is formed (FIG. 72). Subsequently, a metal film 31 or the like, which is a cathode of electroplating, is formed by vapor deposition (FIG. 76). Subsequently, a resist pattern 17 is formed except for a portion in which metal wiring is formed and connected by electroplating (FIG. 77).

Thereafter, the metal film 31 which is not covered with the resist pattern 17 is used as the cathode to form a wiring pattern of metal wiring by electroplating (Fig. 78). Next, the resist pattern 17 is removed (FIG. 79). Further, using the wiring pattern of the metal film 38 formed by electroplating as a mask, the metal film used as the cathode of the electroplating is etched and removed (FIG. 80). Subsequently, when the resin is sealed by the sealing resin 4 (FIG. 81) and the support plate 5 is removed, the semiconductor device can be separated into pieces as shown in FIG.

By performing the metal wiring by the electroplating method as described above, the number of processing steps increases, but since the photolithography is used, finer processing can be performed compared to the wire bonding method or the gas deposition method.

(Example 18)

FIG. 82 also shows a state immediately after removing the support plate, and shows two semiconductor devices sandwiched between the grooves. This embodiment is characterized in that the metal wiring is formed by electroplating.

In the manufacturing of the semiconductor device described above, the steps up to the steps shown in FIG. 79 in the seventeenth embodiment are the same. That is, after forming the wiring pattern of metal wiring by electroplating using the metal film 31 which is not coat | covered with the resist pattern 17, it is the same until the process of removing the resist pattern 17. FIG. Thereafter, as shown in FIG. 83, a second resist pattern 57 is formed by opening the upper portion of the electrode 3 of the semiconductor chip. Subsequently, an electrode terminal 41 is formed in the opening by second electroplating (Fig. 84).

Thereafter, as shown in FIG. 85, the second resist pattern 57 is removed. Next, the sealing resin 4 seals the resin so as to expose the electrode terminal 41 (FIG. 86). After that, when the supporting plate 5 is removed, the semiconductor device can be obtained as shown in FIG. 82. The separated semiconductor device shown in FIG. 82 is a semiconductor device with terminals at different positions up and down.

As a modification of the semiconductor device shown in FIG. 82, the semiconductor device shown in FIG. 87 is shown. In the semiconductor device of FIG. 87, the upper connection terminal 58 is formed on the connection terminal 38a formed on the support plate of the groove bottom portion. The structure of the semiconductor device of FIG. 87 can be formed by providing an opening on the connection terminal 38a for the second resist pattern.

The semiconductor device shown in FIG. 82 and FIG. 87 can basically be achieved by performing two degrees of photolithography and electroplating, respectively. When the terminal for multi-layer connection is formed by the electroplating method, it is not only excellent in fine workability but also easy to control the size of the connection terminal exposed on the upper surface as compared with the wire bonding method or the gas deposition method. On the other hand, in the wire bonding method, the diameter of the wire is restricted, and in the gas deposition method, when the vapor deposition is piled up to form the connection terminal part, the diameter becomes smaller than the bottom part by the upper part. For this reason, the size of the connection terminal exposed from the upper surface of the sealing resin 4 is restricted. According to the electroplating method, the connection terminal can be formed without changing the size by increasing the resolution of the resist pattern regardless of the height itself stacked on the upper side.

(Example 19)

88 to 93 show the semiconductor device and its modification example in Example 19 of the present invention. In this embodiment, an example in which a structure that can be formed by the wire bonding method and the gas deposition method is formed by the electroplating method is shown.

In the semiconductor device shown in FIG. 88, instead of the insulating film pattern 17 made of polyimide, for example, a photoresist pattern is disposed to form metal wiring by electroplating. The photoresist pattern is removed after etching the metal film 31 used for the cathode as a mask using the metal wiring 38 formed by electroplating before sealing with a sealing resin. After the photoresist pattern is removed, it is sealed with a sealing resin (4).

As described above, by arranging the same sealing resin on the front side and the back side of the metal wiring, it is possible to reduce the possibility that the metal wiring is disconnected due to the stress caused by thermal distortion.

In the semiconductor device shown in FIG. 89, a part of the connection terminal 38a is exposed on the side surface of the semiconductor device. According to this structure, the bonding strength can be improved as in the case of the wire bonding method, the gas deposition method, or the like.

The semiconductor device shown in FIG. 90 is characterized in that a step is provided between the semiconductor chip 1a and an insulating film pattern 27 such as polyimide on the back surface of the semiconductor device including metal wiring formed by electroplating. There is this. By providing such a step, since the connection terminal 38a protrudes, connection becomes easy. Easy connection by the projecting structure of the connecting terminal can be obtained by any metal wiring forming method regardless of the metal wiring manufacturing method.

In the semiconductor device shown in FIG. 91, in the semiconductor device including metal wiring formed by electroplating, a plate 6 excellent in thermal conductivity is disposed on the back surface of the semiconductor chip for heat dissipation. By disposing the plate 6, the heat dissipation of the semiconductor chip can be improved. The improvement of heat dissipation by the arrangement of the plate 6 can be obtained by any method of forming metal wiring, regardless of the method of forming metal wiring.

In the semiconductor device shown in FIG. 92, in the semiconductor device including the metal wiring 38 formed by electroplating, the upper, side, and lower surfaces of the upper connection terminal 58 provided on the connection terminal 38a are sealed. It is characteristic in that it exposed from resin. By exposing the upper connection terminal 58 as described above, connection can be made to a large portion of the upper connection terminal, and mounting on various circuit boards is possible. This effect can be obtained by any method of forming metal wiring, regardless of the method of forming metal wiring.

The semiconductor device shown in FIG. 93 can be formed by shifting the opening of the second resist pattern outward of the first electroplating pattern in the manufacture of the semiconductor device shown in FIG. 87. The semiconductor device of FIG. 93 differs from the semiconductor device of FIG. 92 and does not expose the entire side surface of the upper terminal 58 for connection. The upper part of the side surface of the upper terminal 58 is covered with a sealing resin 4.

According to the semiconductor device shown in FIG. 93, after obtaining the bonding strength and various bonding properties on the exposed portions of the side surfaces and the lower surfaces, it is possible to prevent creeping up of the bonding material such as solder to the upper surface of the upper connection terminal.

(Example 20)

Referring to Fig. 94, in the present embodiment, the positions of the metal wirings 2, 18, 38 for connecting the electrodes of the semiconductor chip and the support plate are shifted between the adjacent semiconductor chips, thereby connecting to the support plate of the groove bottom portion. It is characterized by alternating points. By arranging the metal wiring as described above, the width of the groove can be narrowed.

It goes without saying that the manufacturing method of this embodiment can be any of the wire bonding method, the gas deposition method and the plating method. In particular, the plating method using a photo plate is excellent in micromachinability, and thus a semiconductor device can be manufactured without expanding the electrode pitch of the semiconductor chip as compared with the other two methods. In the other two methods, since the micromachinability is relatively inferior to the plating method, the electrode pitch must be enlarged by narrowing the grooves, and this is not advantageous in semiconductor chips having many electrodes.

As mentioned above, although the Example of this invention was described, the Example of this invention disclosed above is an illustration to the last, The scope of the present invention is not limited to the Example of these invention. The scope of the present invention is indicated by the description of the claims, and further includes the description of the claims and their equivalents and all modifications within the scope.

By using the semiconductor device and its manufacturing method of the present invention, it is possible to provide a semiconductor device which has been miniaturized by a simple manufacturing process that has greatly increased production efficiency in the past. In addition, since the semiconductor device can easily form a multilayer structure, a high-density miniaturized multilayer semiconductor device can be obtained at low cost.

Claims (3)

A semiconductor chip having a semiconductor circuit and an electrode having a predetermined function on one main surface; A metal wire having one end connected to the electrode and the other end connected to the outside; An insulator covering at least said one main surface of said semiconductor chip, The connection terminal at the other end of the metal wiring is a portion formed while maintaining a state in which it is integrated with other parts of the metal wiring, and the connection terminal is exposed from the bottom surface on the opposite side to the upper surface of the insulator on the one main surface side. A semiconductor device, characterized in that. The method of claim 1, And the metal wiring is a wire formed by wire bonding, and the connecting terminal is a bulk connecting terminal which is processed in a state where a part of the wire is continuous to the wire and becomes a bulk type. The method of claim 1, The metal wiring and the connection terminal are formed by any one of a gas deposition method and a plating method.