KR20030060514A - Method for manufacturing semiconductor device having triple gate and semiconductor device made by the same - Google Patents

Abstract

The present invention relates to a method of manufacturing a semiconductor memory device having a triple gate, and a semiconductor device having a triple gate manufactured thereby. The present invention provides a method of manufacturing a semiconductor device having a triple gate including three threshold voltage regions of high voltage, medium voltage, and low voltage on a semiconductor substrate. First, an element isolation oxide film is formed on a semiconductor substrate to form a device. Define the area. A gate insulating film for high voltage formed of a plurality of films of a silicon oxide film / silicon nitride film / silicon oxide film is formed over the semiconductor substrate including the high voltage region. The high voltage gate insulating film is removed in the medium voltage region and the low voltage region to form a medium voltage gate insulating film. The medium voltage gate insulating film is removed in the magnetic voltage region, and a low voltage gate insulating film is formed. Then, a gate conductive film is formed on the high, medium, and low voltage gate insulating film, and then a gate pattern is formed on the gate conductive film.

When the gate insulating film for high voltage is formed by applying a plurality of silicon insulating films in this way, when forming a multi-gate insulating film having different thicknesses and automatic voltages, the photo process can be reduced, thereby simplifying the process and reducing the production cost. There is an advantage.

Description

A method for manufacturing a semiconductor device having a triple gate and a semiconductor device having a triple gate manufactured by the same hereinafter [Method for manufacturing semiconductor device having triple gate and semiconductor device made by the same}

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having a triple gate.

Among semiconductor devices, there are semiconductor devices having multiple gates having different operating voltages. Some logic products and digital signal processors (DSPs) are typical examples of employing multiple gates having a plurality of threshold voltages. In particular, products using triple gates have emerged in semiconductor devices.

These multi-gate products are formed in different thicknesses by adjusting the thickness of the gate insulating film to control the threshold voltage (Vt) of each gate when manufacturing a semiconductor device. 9 to 12 are cross-sectional views showing a conventional technique step by step with respect to the manufacturing method of a semiconductor device having a plurality of gates, in particular having a triple gate. 9 to 10, a mask insulating film 1110 composed of a silicon oxide film 1111, a silicon nitride film 1113 and a silicon nitride film 1115 is formed on the entire surface of the semiconductor substrate 100, and a predetermined photo and etching process is performed. The mask insulating film 1110 in the high voltage region H is removed through the process. Then, a silicon oxide film is deposited on the high voltage region H where the surface of the known silicon 100 is exposed to form the thickest high voltage gate insulating film 1120. As shown in FIG. 11, the mask insulating film 1110 of the medium and low voltage regions M and L is removed through photo and dry etching, and the medium voltage region M on which the known silicon 100 is exposed. ) And the low voltage region L to form a gate insulating film 1130 for medium voltage using a silicon oxide film having a medium thickness in the medium voltage M and the low voltage region L. Finally, as shown in FIG. After the etching process, the gate insulating film 1130 for the medium voltage in the low voltage region L is removed and the thin film for the low voltage gate insulating film 1140 is formed. Subsequently, when the process is completed using a conventional method for manufacturing a semiconductor, a semiconductor device having a triple gate is completed. In the drawings, 1310, 1320, and 1330 are patterned photoresist patterns.

However, in the conventional method of manufacturing a semiconductor device having a triple gate, the photoresist 310, 320, 330 and the base silicon of the device regions M and L on which the gate insulating film is to be formed are directly contacted while forming the gate insulating film. There is a possibility that heavy metal impurities including carbon contained in the photoresist penetrate into the known silicon and degrade the reliability of the gate insulating layers 1120, 1130, and 1140. In addition, a photo and dry etching process is included every time the gate insulating layer is formed, and thus manufacturing cost is relatively high.

Accordingly, the technical problem to be achieved by the present invention is to simplify the process of forming the triple gate insulating film, to reduce the process cost by reducing the photo process during the process of forming the triple gate, and to reduce the number of contact between the substrate silicon and the photoresist. It is to provide a method of manufacturing a semiconductor device having a triple gate that can improve the electrical characteristics of the triple gate.

1 is a cross-sectional view of a semiconductor device having a triple gate manufactured by the present invention.

2 to 8 are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device having a triple gate according to the present invention.

9 to 12 are cross-sectional views illustrating a method of manufacturing a semiconductor device having a triple gate according to the related art.

In order to achieve the above technical problem, a method of manufacturing a semiconductor device having a triple gate of the present invention, first, forming an oxide film for isolation on the semiconductor substrate to include three threshold voltage regions of high voltage, medium voltage, low voltage Define the device formation region. A gate insulating film for high voltage formed of a plurality of films of a silicon oxide film / silicon nitride film / silicon oxide film is formed over the semiconductor substrate including the high voltage region. Then, the high voltage gate insulating film formed in the medium voltage region and the low voltage region is removed to form a medium voltage gate insulating film. The medium voltage gate insulating film formed in the low voltage region is removed and a low voltage gate insulating film is formed. A gate conductive film is formed on the high, medium, and low voltage gate insulating films thus formed, and a gate pattern is formed on the gate conductive film.

Here, in the device isolation process, a trench is formed by recessing a predetermined depth of a semiconductor substrate, and a silicon oxide film is deposited as a silicon insulating film in the trench, and the silicon oxide film is left only in the trench through a predetermined planarization process. Fill the oxide film.

Then, the silicon oxide is oxidized in the element formation region of the front surface of the semiconductor substrate to form a lower oxide film on the surface. Again, a silicon nitride film is formed on the entire surface of the semiconductor substrate by low pressure chemical vapor deposition (LP CVD). A silicon oxide film is formed on the silicon nitride film by chemical vapor deposition to form a high voltage gate insulating film formed of a triple film of a silicon oxide film / silicon nitride film / silicon oxide film including a high voltage region on the entire surface of the semiconductor substrate. The lower oxide film may be a silicon oxide film formed using a chemical vapor deposition method.

By using the photo process, the high voltage region is covered with the photoresist and the medium voltage and the low voltage region are exposed to remove the high voltage gate insulating film in the medium voltage and the low voltage region. At this time, it may be removed by a dry etching method using a plasma, or by wet etching using a photoresist as a hard mask. Then, the silicon is formed in the element formation region of the medium voltage and the low voltage region where the known silicon is exposed to form a gate insulating film for medium voltage using the silicon oxide film.

Only the high voltage and medium voltage regions are exposed to the photoresist through a predetermined photo process while only the low voltage region is exposed, and the medium voltage gate insulating film formed in the element formation region of the low voltage region is removed by using dry etching or wet etching to expose the known silicon. . The low-voltage gate insulating film formed of the silicon oxide film is formed by oxidizing the known silicon in the low-voltage region exposed to the surface.

Then, a gate conductive film is formed over the entire semiconductor substrate on which each gate insulating film is completed, and a gate pattern is formed on the gate conductive film through a predetermined photo process. In this case, the gate conductive layer includes conductive polysilicon doped with impurities, and further includes a metal silicide layer such as tungsten silicide (WSi), titanium silicide (TiSi), or molybly silicide (MoSi) to improve the conductivity of the gate. You may.

Thus, in the method of manufacturing a semiconductor device having a triple gate of the present invention, a high voltage and medium voltage are formed by forming a multilayer insulating film having a three-layer film structure of a silicon oxide film / silicon nitride film / silicon oxide film, which is mainly applied as a mask insulating film as a high voltage gate insulating film. And a photo process can be reduced by one when forming a low voltage gate. When the high voltage gate insulating film is formed, the photoresist does not come into contact with the high voltage region, thereby preventing the introduction of impurities into the known silicon, thereby improving the reliability of the high voltage gate insulating film. In addition, since the number of photo processes is reduced, the process of forming the triple gate can be simplified and the manufacturing cost of the semiconductor device can be reduced.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention; However, embodiments of the present invention illustrated below may be modified in various other forms, and the scope of the present invention is not limited to the embodiments described below. The embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art.

1 is a cross-sectional view of a semiconductor device having a triple gate fabricated in accordance with the present invention, and FIGS. 2 to 3 are cross-sectional views of each step shown in detail to explain a method of manufacturing a semiconductor device having a triple gate of the present invention.

Referring to FIG. 1, a semiconductor memory device having a triple gate according to an embodiment of the present invention includes a device forming region including a high voltage region H, a medium voltage region M, and a low voltage region L on a semiconductor substrate 100. An element isolation oxide film 101 formed for definition, a high voltage gate insulating film 110 formed in the element formation region of the high voltage region H, a medium voltage gate insulating film 120 formed in the medium voltage region M, The gate insulating layer 130 for the low voltage formed in the low voltage region L and the gate conductive layer 150 formed on the high, medium and low voltage gate insulating layers 110, 120, and 130 and gated are formed.

In this case, the high voltage gate insulating film 110 includes a silicon oxide film 111 formed by oxidizing matrix silicon at a portion in contact with the matrix silicon 100, and a silicon nitride film 113 formed thereon by low pressure chemical vapor deposition (LP CVD). And the three-layer film of the silicon oxide film 115 formed by chemical vapor deposition (CVD). In addition, the gate conductive layer 150 is formed of a conductive polysilicon layer doped with impurities, and has a low resistivity of tungsten silicide (WSi), titanium silicide (TiSi), or molybly silicide (MoSi) to improve conductivity of the gate line. Or a polysilicon film formed by combining a metal silicide film and polysilicon together. The gate mask insulating layer 160 may be further included on the gate conductive layer to protect the gate line.

2 to 9 are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device having a triple gate of FIG. 1.

Referring to FIG. 2, first, a mask insulating film (not shown) is formed over the entire semiconductor substrate 100, and a trench pattern is formed in the mask insulating film, and then the patterned mask insulating film is used as a mask. The trench is formed by etching the known silicon of the semiconductor substrate 100 to a predetermined depth by a dry etching method. In addition, a trench insulating device isolation insulating film 101 is formed on the entire surface of the semiconductor substrate by filling a predetermined silicon insulating film to form a device forming region including a high voltage region H, a medium voltage region M, and a low voltage region L. FIG. define.

Referring to FIGS. 3 and 4, after a predetermined cleaning process is performed to expose the base silicon 100 of the device formation region, the lower oxide film 111 is formed by oxidizing the base silicon 100 of the device formation region. . On the semiconductor substrate 100 on which the lower oxide film 111 is formed, the silicon nitride film 113 and the silicon oxide film 115 formed by chemical vapor deposition are sequentially formed to form a multilayer of silicon oxide film / silicon nitride film / silicon oxide film. The gate insulating layer 110 is formed. Then, the photoresist 310 is coated on the high voltage gate insulating layer 110, and a pattern is formed in which the medium voltage region M and the low voltage region L are opened in the photoresist 310 through a predetermined alignment exposure. do. Using the patterned photoresist 310 as a mask, the upper silicon oxide film 115 and the silicon nitride film 113 are etched and removed by dry etching. The lower oxide layer 111 exposed on the surface is etched using wet etching, so that the gate insulating film 110 for high voltage is formed only in the high voltage region H, and the high voltage for the medium voltage M and the low voltage region L is formed. The gate insulating layer 110 is removed to expose the matrix silicon 100.

5 and 6, the photoresist is removed by ashing and wet cleaning, and the base silicon 100 is disposed in the medium voltage M and the low voltage region L where the base silicon 100 is exposed. ) Is oxidized to form the gate insulating film 120 for the medium voltage. At this time, the oxidation reaction may also occur in the matrix silicon under the high voltage gate insulating layer 110, but the silicon nitride film interposed therebetween prevents the penetration of the element oxide into the matrix silicon so that the oxide film formation reaction does not occur. The photoresist 320 is applied to the entire surface of the semiconductor substrate 100, and the low voltage region L is applied to the photoresist 320 so that the medium voltage gate insulating layer 120 formed in the low voltage region L is exposed through a predetermined alignment exposure. Form an open pattern. Using the patterned photoresist 320 as a mask, the gate insulating film 120 for medium voltage is removed in the low voltage region L. FIG. At this time, the medium voltage silicon oxide film 120 is etched by a wet etching method. This is a measure for minimizing damage to the base silicon 100 during the etching process, and it is possible to improve the reliability of the low voltage gate insulating film 130 (see FIG. 7) to be formed in the low voltage region L later. There is an advantage.

Referring to FIG. 7, the low voltage gate insulating layer 120 is removed to form the low voltage gate insulating layer 130 formed of the silicon oxide layer using the oxidation method in the low voltage region L where the known silicon 100 is exposed. At this time, the medium voltage region M and the high voltage region H are both exposed to an oxidizing atmosphere, but the low voltage gate oxide film 130 is very thin, and thus the process time is short. In the case of the gate insulating film 120 for the medium voltage of the increase of the thickness is very small and does not affect. However, such a slight influence may have an effect when the device is highly integrated and the line width is narrowed. Therefore, the low voltage gate insulating film 130 is formed to have a thickness of the medium voltage gate insulating film 120 in the medium voltage region M. It grows and grows as little as it grows. Then, the thickness error of the middle voltage gate insulating layer 120 due to the formation of the low voltage gate insulating layer 130 may be completely compensated for.

Referring to FIG. 8, the gate conductive layer 150 is formed on the entire surface of the semiconductor substrate 100 on which the gate insulating layers 110, 120, and 130 for high voltage are formed. Thereafter, the photoresist 330 is coated on the gate conductive layer 150, and a gate pattern is formed on the photoresist 330 through a predetermined alignment exposure. When the gate conductive layer 150 is etched by dry etching using the patterned photoresist 330 as a mask, a gate pattern is formed on the gate conductive layer 150. In this case, the gate conductive layer 150 is formed of polysilicon doped with impurities, and in order to improve the conductivity of the gate line, tungsten silicide (WSi), titanium silicide (TiSi), molybly silicide (MoSi), and cobalt having low resistivity are improved. Metal silicides such as silicide (CoSi) may be formed of polycide formed by combining with doped polysilicon. In this case, the gate mask insulating layer 160 may be further formed on the gate conductive layer to reduce damage due to plasma etching during the gate pattern. Subsequently, the subsequent step is a step of manufacturing a conventional semiconductor device to complete a semiconductor device having a triple gate.

As described above, in the method of manufacturing a semiconductor device having a triple gate according to the present invention, a multi-layer gate insulating film composed of a silicon oxide film 111 / silicon insulating film 113 / silicon oxide film 115 as the high voltage gate insulating film 110. In addition, the gate insulating films 120 and 130 serve to mask the occurrence of the oxide film reaction in the high voltage region H when the intermediate and low voltage gate insulating films 120 and 130 are subsequently formed. The number of photo masks required can be reduced by one. Therefore, the process for manufacturing a semiconductor device can be simplified, and the effect of reducing process cost can be achieved. In addition, when the gate insulating film 110 for high voltage is formed, since the base silicon 100 does not contact the photoresist 310, the reliability of the gate insulating film can be improved.

As described above, the method of manufacturing a semiconductor device having a triple gate according to the present invention can reduce one photo process, thereby simplifying the process and thus reducing production costs.

When the gate insulating film for high voltage is formed, the known silicon of the region does not come into contact with the photoresist, thereby preventing the reliability of the gate insulating film from being contaminated with impurities, thereby improving the electrical reliability.

Claims (14)

A method of manufacturing a semiconductor device having a triple gate including three threshold voltage regions of a high voltage, a medium voltage, and a low voltage on a semiconductor substrate, a) forming an isolation layer on the semiconductor substrate to define a device formation region; b) forming a gate insulating film for high voltage formed of a plurality of films of a silicon oxide film / silicon nitride film / silicon oxide film in the high voltage region; c) forming a middle voltage gate insulating layer in the middle voltage region and the low voltage region; d) forming a low voltage gate insulating layer in the low voltage region; and e) forming a gate conductive film on the high, medium, and low voltage gate insulating film, and forming a gate pattern on the gate conductive film. The method of claim 1, wherein step a) comprises: Recessing the matrix silicon of the semiconductor substrate to a predetermined depth to form a trench; And filling the trench with a silicon insulating film. The method of claim 1, wherein b), Forming a lower oxide film on the device formation region of the front surface of the semiconductor substrate; Forming a silicon nitride film over the entire semiconductor substrate; And forming a silicon oxide film on the silicon nitride film by chemical vapor deposition. 4. The method of claim 3, wherein the lower oxide film is formed by oxidizing matrix silicon of the semiconductor substrate. 4. The method of claim 3, wherein the silicon nitride film is formed by low pressure chemical vapor deposition. The method of claim 1, wherein step c) Covering the high voltage region with a photoresist and removing the high voltage gate insulating layer of the medium voltage and the low voltage region; And forming a gate insulating film for a medium voltage in the element formation regions of the medium voltage and the low voltage region. 7. The method of claim 6, wherein the gate insulating film for increasing voltage is a silicon oxide film formed by oxidizing known silicon in the low voltage and medium voltage regions. The method of claim 1, wherein step d) Covering the high and medium voltage regions with a photoresist, and removing the medium voltage gate insulating layer formed in the element formation region of the low voltage region; And forming a low voltage gate insulating film in the low voltage region. 10. The method of claim 8, wherein the gate insulating film for low voltage is a silicon oxide film formed by oxidizing known silicon in a low voltage region. 2. The method of claim 1, wherein in the step e), the gate conductive layer comprises conductive polysilicon doped with an impurity. A device isolation insulating layer formed on the semiconductor substrate and separating the device region into low voltage, medium voltage, and high voltage regions; A high voltage gate insulating film formed of at least three layers of a lower oxide film formed of a silicon oxide film in the high voltage region, a silicon insulating film formed of a chemical vapor deposition method, and a silicon oxide film; A medium voltage gate insulating layer formed on the medium voltage region and formed on the silicon of the semiconductor substrate; A low voltage gate insulating layer formed in the low voltage region and formed in matrix silicon of the semiconductor substrate; And And a gate conductive film having a predetermined gate pattern formed on said high voltage, said medium voltage, and said low voltage gate insulating films. 12. The semiconductor device according to claim 11, wherein the lower oxide film is a silicon oxide film formed by oxidizing known silicon in the high voltage region. 12. The semiconductor device according to claim 11, wherein the medium voltage gate insulating film and the low voltage gate insulating film are silicon oxide films formed by oxidizing known silicon. 12. The semiconductor device of claim 11, wherein the gate conductive film comprises conductive polysilicon doped with an impurity.