KR20030057187A - Module on chip package - Google Patents
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- KR20030057187A KR20030057187A KR1020010087564A KR20010087564A KR20030057187A KR 20030057187 A KR20030057187 A KR 20030057187A KR 1020010087564 A KR1020010087564 A KR 1020010087564A KR 20010087564 A KR20010087564 A KR 20010087564A KR 20030057187 A KR20030057187 A KR 20030057187A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group subclass H10D
- H01L25/072—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group subclass H10D the devices being arranged next to each other
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
- H01L25/0655—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00 the devices being arranged next to each other
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/71—Means for bonding not being attached to, or not being formed on, the surface to be connected
- H01L2224/72—Detachable connecting means consisting of mechanical auxiliary parts connecting the device, e.g. pressure contacts using springs or clips
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
이 발명은 모듈 온 칩 패키지에 관한 것으로, 사용중 불량이 발생된 반도체칩을 간단하게 교체할 수 있고, 제조 공정을 단축시킬 수 있도록, 다수의 요홈이 형성되고, 상기 요홈의 바닥면에는 다수의 리드가 형성된 대략 직사각판 형태의 기판과; 하면에 다수의 본딩패드가 형성되고, 상기 각 본딩패드는 상기 요홈의 리드에 전기적으로 연결된 다수의 반도체칩과; 상기 각각의 반도체칩 및 요홈을 상부에서 덮는 다수의 커버와; 상기 각각의 커버 내측에서 상기 각 반도체칩의 상면을 가압하는 플레이트와; 상기 각 플레이트와 각 커버 사이에 형성된 다수의 스프링을 포함하여 이루어진 것을 특징으로 함.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a module-on-chip package, in which a plurality of grooves are formed to easily replace a semiconductor chip in which a defect occurs during use and to shorten a manufacturing process, and a plurality of leads are formed on the bottom surface of the grooves. A substrate having a substantially rectangular plate shape formed thereon; A plurality of bonding pads are formed on a bottom surface, each bonding pad comprising: a plurality of semiconductor chips electrically connected to the leads of the grooves; A plurality of covers covering each of the semiconductor chips and grooves thereon; Plates for pressing upper surfaces of the semiconductor chips inside the respective covers; It characterized in that it comprises a plurality of springs formed between each plate and each cover.
Description
본 발명은 모듈 온 칩 패키지에 관한 것으로, 더욱 상세하게 설명하면 사용중 불량이 발생된 반도체칩을 간단하게 교체할 수 있고, 제조 공정을 단축시킬 수 있는 모듈 온 칩 패키지에 관한 것이다.The present invention relates to a module-on-chip package, and more particularly, to a module-on-chip package that can easily replace a semiconductor chip in which a failure occurs during use and shorten a manufacturing process.
도1a는 종래의 모듈 온 칩 패키지(100')를 도시한 평면도이고, 도1b는 도1a에서 I-I선을 도시한 단면도이다.FIG. 1A is a plan view illustrating a conventional module-on-chip package 100 ', and FIG. 1B is a cross-sectional view of the I-I line of FIG. 1A.
도시된 바와 같이 대략 직사각판 형태의 기판(2')이 형성되어 있고, 상기 기판(2')에는 다수의 반도체패키지(101')가 솔더(18')에 의해 실장되어 있다.As shown, a substrate 2 'having a substantially rectangular plate shape is formed, and a plurality of semiconductor packages 101' are mounted on the substrate 2 'by solder 18'.
상기 각 반도체패키지(101')는 도시된 바와 같이 중앙에 칩탑재판(6')이 구비되어 있고, 상기 칩탑재판(6')의 상면에는 접착제(8')로 반도체칩(20')이 접착되어 있으며, 상기 반도체칩(20') 및 칩탑재판(6')의 외주연에는 다수의 리드(10')가 배열되어 있다. 또한, 상기 각 반도체칩(20')의 상면에는 다수의 본딩패드(14')가 형성되어 있으며, 상기 본딩패드(14')와 상기 리드(10') 사이에는 도전성와이어(12')가 상호 연결되어 있다. 더불어, 상기 칩탑재판(6'), 반도체칩(20'), 도전성와이어(12') 및 리드(10')는 봉지재(16')로 봉지되어 있으며, 상기 리드(10')는 상기 봉지재(16')의 하면으로 절곡됨으로써, 상기 리드(10')가 상기 기판(2')에 전기적으로 접속되어 있다.Each semiconductor package 101 'is provided with a chip mounting plate 6' at the center as shown, and a semiconductor chip 20 'with an adhesive 8' on the top surface of the chip mounting plate 6 '. Are bonded, and a plurality of leads 10 'are arranged on the outer periphery of the semiconductor chip 20' and the chip mounting plate 6 '. In addition, a plurality of bonding pads 14 'are formed on an upper surface of each of the semiconductor chips 20', and conductive wires 12 'are mutually connected between the bonding pads 14' and the leads 10 '. It is connected. In addition, the chip mounting plate 6 ', the semiconductor chip 20', the conductive wire 12 'and the lead 10' are encapsulated with an encapsulant 16 ', and the lead 10' is The lead 10 'is electrically connected to the substrate 2' by bending the lower surface of the encapsulant 16 '.
도면중 미설명 부호 4'는 상기 모듈 온 칩 패키지(100')가 외부 장치에 전기적으로 연결되도록 하는 도전성 패턴이다.In the figure, reference numeral 4 'is a conductive pattern for allowing the module on chip package 100' to be electrically connected to an external device.
한편, 상기 기판에 실장되는 각 반도체패키지의 제조 방법은 다수의 반도체칩이 형성된 웨이퍼를 접착성 테이프에 접착하는 웨이퍼 마운트 단계와, 상기 마운트된 웨이퍼에서 낱개의 반도체칩으로 상호 분리시키는 웨이퍼 소잉 단계와, 상기 소잉된 개별 반도체칩을 리드프레임에 접착시키는 다이 본딩 공정과, 상기 반도체칩과 리드프레임의 리드를 도전성와이어로 상호 연결하는 와이어 본딩 단계와, 상기 반도체칩, 리드, 도전성와이어 등을 봉지재로 봉지하는 봉지 단계와, 상기 봉지재 표면에 제품명, 제조회사명 등을 마킹하는 마킹 단계와, 상기 리드프레임에서 봉지재 등이 외측으로 유출되지 않도록 형성된 댐바를 제거하는 트림 단계와, 상기 리드프레임에서 리드를 소정 형상으로 구부리는 폼 단계로 이루어져 있다.Meanwhile, a method of manufacturing each semiconductor package mounted on the substrate may include a wafer mounting step of bonding a wafer on which a plurality of semiconductor chips are formed to an adhesive tape, and a wafer sawing step of separating the semiconductor wafers from the mounted wafer into individual semiconductor chips. A die bonding step of bonding the sawed individual semiconductor chips to a lead frame, a wire bonding step of interconnecting the leads of the semiconductor chip and the lead frame with conductive wires, and encapsulating the semiconductor chips, leads, conductive wires, and the like. An encapsulation step of encapsulating the encapsulation step, a marking step of marking a product name, a company name, etc. on the encapsulant surface, a trim step of removing a dam bar formed in the lead frame such that encapsulant does not leak outward, and the lead frame Consists of a foam step of bending the lead into a predetermined shape.
그러나, 이러한 종래의 구조 및 제조 방법에 의하면, 상기 기판에서 어느 한 반도체칩 또는 반도체패키지가 고장났을 경우에 그 고장난 반도체칩 또는 반도체패키지만을 교체하기는 어렵고 따라서 전체적인 모듈 온 칩 패키지 자체를 교체해야 하는 비효율적인 문제가 있다.However, according to such a conventional structure and manufacturing method, when any one of the semiconductor chip or semiconductor package in the substrate is broken, it is difficult to replace only the failed semiconductor chip or semiconductor package and thus the entire module-on-chip package itself must be replaced. There is an inefficient problem.
더불어, 하나의 반도체패키지를 제조하기 위한 방법이 너무 복잡하고, 또한 많아서 반도체패키지의 수율이 떨어질 뿐만 아니라 제조 비용도 증가하는 문제가 있다.In addition, the method for manufacturing a single semiconductor package is too complicated, and there are many problems in that the yield of the semiconductor package not only decreases but also the manufacturing cost increases.
따라서 본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출한 것으로, 사용중 불량이 발생된 반도체칩을 간단하게 교체할 수 있고, 제조 공정이 간단한 모듈 온 칩 패키지를 제공하는데 있다.Accordingly, the present invention has been made to solve the above-mentioned conventional problems, and to provide a module-on-chip package that can easily replace a semiconductor chip in which a defect occurs during use, and a simple manufacturing process.
도1a는 종래의 모듈 온 칩 패키지를 도시한 평면도이고, 도1b는 도1a에서 I-I선을 도시한 단면도이다.FIG. 1A is a plan view illustrating a conventional module-on-chip package, and FIG. 1B is a cross-sectional view of the I-I line of FIG. 1A.
도2a는 본 발명에 의한 모듈 온 칩 패키지를 도시한 평면도이고, 도2b는 도2a에서 II-II선을 도시한 단면도이다.Figure 2a is a plan view showing a module-on-chip package according to the present invention, Figure 2b is a cross-sectional view taken along the line II-II in Figure 2a.
도3a는 본 발명에 의한 모듈 온 칩 패키지에서 반도체칩과 기판과의 결합 상태를 도시한 단면도이고, 도3b는 기판을 도시한 평면도이며, 도3c는 커버를 도시한 사시도이다.3A is a cross-sectional view illustrating a bonding state between a semiconductor chip and a substrate in a module-on-chip package according to the present invention, FIG. 3B is a plan view of the substrate, and FIG. 3C is a perspective view of the cover.
- 도면중 주요 부호에 대한 설명 --Description of the main symbols in the drawings-
100; 본 발명에 의한 모듈 온 칩 패키지100; Module on chip package according to the present invention
2; 기판4; 도전성 패턴2; A substrate 4; Conductive pattern
6; 요홈8; 리드6; Groove 8; lead
10; 돌출턱12; 반도체칩10; Protruding jaw 12; Semiconductor chip
14; 본딩패드16; 도전성범프14; Bonding pads 16; Conductive Bump
18; 플레이트20; 스프링18; Plate 20; spring
22; 커버22; cover
상기한 목적을 달성하기 위해 본 발명에 의한 모듈 온 칩 패키지는 다수의 요홈이 형성되고, 상기 요홈의 바닥면에는 다수의 리드가 형성된 대략 직사각판 형태의 기판과; 하면에 다수의 본딩패드가 형성되고, 상기 각 본딩패드는 상기 요홈의 리드에 전기적으로 연결된 다수의 반도체칩과; 상기 각각의 반도체칩 및 요홈을 상부에서 덮는 다수의 커버와; 상기 각각의 커버 내측에서 상기 각 반도체칩의 상면을 가압하는 플레이트와; 상기 각 플레이트와 각 커버 사이에 형성된 다수의 스프링을 포함하여 이루어진 것을 특징으로 한다.In order to achieve the above object, the module-on-chip package according to the present invention includes a substrate having a substantially rectangular plate shape in which a plurality of grooves are formed, and a plurality of leads are formed on the bottom surface of the groove; A plurality of bonding pads are formed on a bottom surface, each bonding pad comprising: a plurality of semiconductor chips electrically connected to the leads of the grooves; A plurality of covers covering each of the semiconductor chips and grooves thereon; Plates for pressing upper surfaces of the semiconductor chips inside the respective covers; It characterized in that it comprises a plurality of springs formed between each plate and each cover.
여기서, 상기 반도체칩은 본딩패드에 상기 리드와 전기적으로 접속되는 도전성범프가 더 형성될 수 있다.The semiconductor chip may further include a conductive bump electrically connected to the lead on a bonding pad.
또한, 상기 기판은 리드에 상기 반도체칩의 본딩패드가 용이하게 접속되도록 돌출턱이 더 형성될 수 있다.In addition, the substrate may further include a protrusion jaw so that a bonding pad of the semiconductor chip is easily connected to a lead.
상기와 같이 하여 본 발명에 의한 모듈 온 칩 패키지에 의하면, 기판에 다수의 요홈을 형성하고, 상기 각 요홈에 반도체칩을 플립칩 형태로 위치시킨 후, 플레이트 및 커버로 상기 반도체칩을 가압하여 상기 기판에 전기적으로 연결되도록 함으로써, 특정한 반도체칩에 불량이 발생되었을 경우, 그 반도체칩만을 용이하게 교체할 수 있는 장점이 있다.According to the module-on-chip package according to the present invention as described above, a plurality of grooves are formed in the substrate, the semiconductor chip is placed in each of the grooves in the form of a flip chip, and then pressing the semiconductor chip with a plate and a cover to the By being electrically connected to a substrate, when a defect occurs in a specific semiconductor chip, only the semiconductor chip can be easily replaced.
또한, 종래와 같은 다이본딩, 와이어 본딩 및 몰딩 공정 등이 필요없음으로써, 제조 공정이 단순해지고 제조 비용이 작아지는 장점이 있다.In addition, since the conventional die bonding, wire bonding, molding process, etc. are not necessary, the manufacturing process is simplified and the manufacturing cost is reduced.
(실시예)(Example)
이하 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 용이하게 실시할 수 있을 정도로 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세하게 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings such that those skilled in the art can easily implement the present invention.
도2a는 본 발명에 의한 모듈 온 칩 패키지(100)를 도시한 평면도이고, 도2b는 도2a에서 II-II선을 도시한 단면도이다.Figure 2a is a plan view showing a module-on-chip package 100 according to the present invention, Figure 2b is a cross-sectional view showing a line II-II in Figure 2a.
또한, 도3a는 본 발명에 의한 모듈 온 칩 패키지(100)에서 반도체칩(12)과 기판(2)과의 결합 상태를 도시한 단면도이고, 도3b는 기판(2)을 도시한 평면도이며, 도3c는 커버(20)를 도시한 사시도이다.3A is a cross-sectional view illustrating a bonding state between the semiconductor chip 12 and the substrate 2 in the module-on-chip package 100 according to the present invention, and FIG. 3B is a plan view illustrating the substrate 2. 3C is a perspective view of the cover 20.
도시된 바와 같이 다수의 요홈(6)이 일정 간격을 두고 형성되고, 상기 각 요홈(6)의 바닥면에는 다수의 리드(8)가 배열된 직사각판 형태의 기판(2)이 구비되어 있다. 또한, 상기 기판(2)의 일측에는 다수의 도전성 패턴(4)이 형성되어 있다. 여기서, 상기 도전성 패턴(4)은 주지된 바와 같이 상기 기판(2)이 외부 장치에 전기적으로 연결되는 영역이다. 물론, 상기 도전성 패턴(4)과 상기 리드(8)는 도시되지 않은 패턴을 통하여 서로 연결되어 있다.As shown, a plurality of grooves 6 are formed at regular intervals, and the bottom surface of each of the grooves 6 is provided with a substrate 2 having a rectangular plate shape in which a plurality of leads 8 are arranged. In addition, a plurality of conductive patterns 4 are formed on one side of the substrate 2. Here, the conductive pattern 4 is a region in which the substrate 2 is electrically connected to an external device as is well known. Of course, the conductive pattern 4 and the lead 8 are connected to each other through a pattern not shown.
또한, 상기 기판(2)의 각 요홈(6)에는 반도체칩(12)이 위치되어 있다. 즉, 상기 반도체칩(12)은 하면에 다수의 본딩패드(14)가 형성되어 있고, 이 본딩패드(14)는 상기 요홈(6)의 바닥면에 형성된 리드(8)에 접속되어 있다.In addition, a semiconductor chip 12 is positioned in each recess 6 of the substrate 2. That is, a plurality of bonding pads 14 are formed on the bottom surface of the semiconductor chip 12, and the bonding pads 14 are connected to leads 8 formed on the bottom surface of the groove 6.
여기서, 상기 반도체칩(12)의 본딩패드(14)에는 골드 또는 솔더 등에 의해도전성범프(16)가 형성될 수 있다.The conductive bumps 16 may be formed on the bonding pads 14 of the semiconductor chip 12 by gold or solder.
또한, 상기 리드(8)에는 상부로 돌출되어 상기 본딩패드(14) 또는 도전성범프(16)에 보다 용이하게 접속될 수 있도록 일정 길이의 돌출턱(10)이 형성될 수 있다.In addition, a protruding jaw 10 of a predetermined length may be formed in the lead 8 so that the lead 8 may be more easily connected to the bonding pad 14 or the conductive bump 16.
따라서, 상기 반도체칩(12)의 본딩패드(14)는 도전성범프(16)가 융착되어 상기 리드(8)에 전기적으로 연결되거나, 또는 상기 반도체칩(12)의 본딩패드(14)가 리드(8)의 돌출턱(10)과 단순하게 직접 접촉되어 전기적으로 연결될 수 있다.Accordingly, the bonding pads 14 of the semiconductor chip 12 may be electrically connected to the leads 8 by welding the conductive bumps 16, or the bonding pads 14 of the semiconductor chip 12 may be connected to the lead pads 14. 8 may be electrically connected to the protruding jaw 10 simply by direct contact.
이때, 상기 돌출턱(10)은 상단에 일정 반경(R)을 주어 상기 반도체칩(12)의 본딩패드(14)가 손상되지 않도록 함이 바람직하다.In this case, the protruding jaw 10 is preferably given a radius (R) at the top so that the bonding pad 14 of the semiconductor chip 12 is not damaged.
이어서, 상기 각각의 반도체칩(12) 및 요홈(6)의 상부에는 커버(22)가 형성되어 있으며, 상기 커버(22)의 하부에는 다수의 스프링(20)이 결합되어 있다. 또한, 상기 스프링(20)의 하단에는 대략 판상의 플레이트(18)가 결합되어 있으며, 이 플레이트(18)는 상기 반도체칩(12)의 상면을 가압하도록 되어 있다. 즉, 상기 커버(22)를 상기 기판(2)에 고정하게 되면, 상기 커버(22) 하부의 플레이트(18)가 스프링(20)의 탄성력에 의해 상기 반도체칩(12)을 가압하게 된다. 그러면, 상기 각 반도체칩(12)의 본딩패드(14)는 상기 요홈(6) 내측의 리드(8)에 더욱 강하게 접속된다.Subsequently, a cover 22 is formed on each of the semiconductor chip 12 and the recess 6, and a plurality of springs 20 are coupled to the bottom of the cover 22. In addition, an approximately plate-shaped plate 18 is coupled to the lower end of the spring 20, and the plate 18 is configured to press the upper surface of the semiconductor chip 12. That is, when the cover 22 is fixed to the substrate 2, the plate 18 under the cover 22 presses the semiconductor chip 12 by the elastic force of the spring 20. Then, the bonding pads 14 of the semiconductor chips 12 are more strongly connected to the leads 8 inside the grooves 6.
또한, 상기 플레이트(18) 및/또는 커버(22)가 도전성 금속(예를 들면, 알루미늄)일 경우, 상기 플레이트(18) 및/또는 커버(22)가 상기 반도체칩(12)의 열을 외부로 신속히 방출하는 역할을 함으로써, 상기 반도체칩(12)의 전기적 성능이 더욱 향상된다.In addition, when the plate 18 and / or the cover 22 is a conductive metal (for example, aluminum), the plate 18 and / or the cover 22 outside the heat of the semiconductor chip 12 By acting as a quick release, the electrical performance of the semiconductor chip 12 is further improved.
물론, 상기 커버(22)는 상기 기판(2)에 접착제 또는 볼트 등과 같은 결합수단에 의해 결합 및 고정된다.Of course, the cover 22 is coupled and fixed to the substrate 2 by a coupling means such as an adhesive or a bolt.
또한, 제품명, 제조 회사명 등은 상기 반도체칩(12)의 상면에 직접 마킹되거나 또는 상기 커버(22)의 상면에 마킹될 수 있다.In addition, a product name, a manufacturing company name, etc. may be directly marked on the upper surface of the semiconductor chip 12 or may be marked on the upper surface of the cover 22.
이러한 모듈 온 칩 패키지(100)의 제조 방법을 설명하면 다음과 같다.The manufacturing method of the module on chip package 100 will be described below.
먼저 다수의 반도체칩(12)이 형성된 웨이퍼를 구비하고, 상기 웨이퍼의 각 반도체칩(12)에 형성된 본딩패드(14)에 골드(예를 들면 골드와이어) 또는 솔더를 이용하여 도전성 범프(16)를 형성한다.First, a wafer having a plurality of semiconductor chips 12 formed thereon, and a conductive bump 16 using gold (for example, gold wire) or solder on a bonding pad 14 formed on each semiconductor chip 12 of the wafer. To form.
이어서, 상기 웨이퍼를 접착성 테이프에 접착하는 웨이퍼 마운트 공정을 수행한 후, 상기 웨이퍼에서 낱개의 반도체칩(12)을 분리하는 웨이퍼 소잉 공정을 수행한다.Subsequently, after performing a wafer mounting process of adhering the wafer to the adhesive tape, a wafer sawing process of separating the individual semiconductor chips 12 from the wafer is performed.
한편, 외부 장치에 결합될 수 있도록 다수의 도전성 패턴(4)이 일측에 형성되어 있고, 일렬로 다수의 요홈(6)이 일정 간격을 두고 형성되어 있으며, 상기 요홈(6)의 바닥면에는 다수의 리드(8)가 형성된 기판(2)을 구비한다.Meanwhile, a plurality of conductive patterns 4 are formed at one side so as to be coupled to an external device, and a plurality of grooves 6 are formed at regular intervals in a row, and a plurality of conductive patterns 4 are formed on the bottom surface of the groove 6. The board | substrate 2 with which the lead 8 of is formed is provided.
이때, 상기 리드(8)에는 상부로 일정 길이 돌출된 돌출턱(10)을 더 형성할 수 있다.In this case, the lead 8 may further include a protruding jaw 10 protruding a predetermined length upward.
이어서, 상기 소잉된 낱개의 반도체칩(12)을 플립칩 형태로 상기 요홈(6)에 위치시킨다. 이때, 상기 반도체칩(12)의 본딩패드(14) 또는 도전성범프(16)가 상기리드(8) 또는 리드(8)의 돌출턱(10)에 정확히 접촉하도록 배열한다.Subsequently, the sawed individual semiconductor chips 12 are placed in the recesses 6 in the form of flip chips. At this time, the bonding pads 14 or the conductive bumps 16 of the semiconductor chip 12 are arranged to be in contact with the protruding jaw 10 of the lead 8 or the lead 8.
물론, 상기 도전성범프(16)를 리플로우함으로써, 상기 도전성범프(16)에 의해 상기 반도체칩(12)의 본딩패드(14)가 리드(8) 또는 돌출턱(10)에 완전히 기계적 및 전기적으로 고착되도록 할 수 있다.Of course, by reflowing the conductive bumps 16, the bonding pads 14 of the semiconductor chip 12 are completely mechanically and electrically connected to the leads 8 or the protruding jaws 10 by the conductive bumps 16. Can be fixed.
계속해서, 하부에 대략 판상의 플레이트(18)가 다수의 스프링(20)으로 결합된 커버(22)를 구비한후, 이를 상기 반도체칩(12)의 상면에 위치시키는 동시에 상기 기판(2)에 접착 또는 고정시킨다. 이때, 상기 플레이트(18)가 상기 반도체칩(12)의 상면을 가압하도록 함으로써, 상기 반도체칩(12)의 본딩패드(14)가 상기 리드(8)의 돌출턱(10)과 강하게 접촉되도록 한다. 즉, 상기 반도체칩(12)의 본딩패드(14)에 도전성범프(16)가 없다고 해도 상기 반도체칩(12)이 상기 리드(8)에 전기적으로 접속되도록 함으로써, 본 발명에 의한 모듈 온 칩 패키지(100)를 완성한다.Subsequently, the cover plate 22 having the plate-like plate 18 coupled to the plurality of springs 20 is provided at a lower portion thereof, and then placed on the upper surface of the semiconductor chip 12 and simultaneously placed on the substrate 2. Glue or fix. In this case, the plate 18 presses the upper surface of the semiconductor chip 12 so that the bonding pad 14 of the semiconductor chip 12 is in strong contact with the protruding jaw 10 of the lead 8. . That is, even when the bonding pad 14 of the semiconductor chip 12 does not have the conductive bumps 16, the semiconductor chip 12 is electrically connected to the lead 8, thereby providing a module-on-chip package according to the present invention. Complete 100.
이상에서와 같이 본 발명은 비록 상기의 실시예에 한하여 설명하였지만 여기에만 한정되지 않으며, 본 발명의 범주 및 사상을 벗어나지 않는 범위내에서 여러가지로 변형된 실시예도 가능할 것이다.As described above, although the present invention has been described with reference to the above embodiments, the present invention is not limited thereto, and various modified embodiments may be possible without departing from the scope and spirit of the present invention.
따라서 본 발명에 의한 모듈 온 칩 패키지에 의하면, 기판에 다수의 요홈을 형성하고, 상기 각 요홈에 반도체칩을 플립칩 형태로 위치시킨 후, 플레이트 및 커버로 상기 반도체칩을 가압하여 상기 기판에 전기적으로 연결되도록 함으로써, 특정한 반도체칩에 불량이 발생되었을 경우, 그 반도체칩만을 용이하게 교체할 수 있는 효과가 있다.Therefore, according to the module-on-chip package according to the present invention, a plurality of grooves are formed in the substrate, and the semiconductor chip is placed in each of the grooves in the form of a flip chip, and then the semiconductor chip is pressed with a plate and a cover to electrically In this case, when a defect occurs in a specific semiconductor chip, only the semiconductor chip can be easily replaced.
또한, 종래와 같은 다이본딩, 와이어 본딩 및 몰딩 공정 등이 필요없음으로써, 제조 공정이 단순해지고 제조 비용이 작아지는 효과가 있다.In addition, since the conventional die bonding, wire bonding, and molding processes are not required, the manufacturing process is simplified and the manufacturing cost is reduced.
Claims (3)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020010087564A KR20030057187A (en) | 2001-12-28 | 2001-12-28 | Module on chip package |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020010087564A KR20030057187A (en) | 2001-12-28 | 2001-12-28 | Module on chip package |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5866347A (en) * | 1981-10-16 | 1983-04-20 | Nec Corp | Composite semiconductor pellet |
| JPH0435310A (en) * | 1990-05-28 | 1992-02-06 | Nippon Dempa Kogyo Co Ltd | Crystal resonator for surface mount |
| JPH08213428A (en) * | 1995-11-20 | 1996-08-20 | Rohm Co Ltd | Semiconductor device mounting method |
| KR19990010620A (en) * | 1997-07-18 | 1999-02-18 | 문정환 | Semiconductor Package Mounting Device |
| US6094058A (en) * | 1991-06-04 | 2000-07-25 | Micron Technology, Inc. | Temporary semiconductor package having dense array external contacts |
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2001
- 2001-12-28 KR KR1020010087564A patent/KR20030057187A/en not_active Ceased
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5866347A (en) * | 1981-10-16 | 1983-04-20 | Nec Corp | Composite semiconductor pellet |
| JPH0435310A (en) * | 1990-05-28 | 1992-02-06 | Nippon Dempa Kogyo Co Ltd | Crystal resonator for surface mount |
| US6094058A (en) * | 1991-06-04 | 2000-07-25 | Micron Technology, Inc. | Temporary semiconductor package having dense array external contacts |
| JPH08213428A (en) * | 1995-11-20 | 1996-08-20 | Rohm Co Ltd | Semiconductor device mounting method |
| KR19990010620A (en) * | 1997-07-18 | 1999-02-18 | 문정환 | Semiconductor Package Mounting Device |
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