KR20030027317A - Test Device for Semiconductor Memory Device - Google Patents

Abstract

PURPOSE: A mode test circuit of a semiconductor memory device is provided to access a specific test mode individually when a plurality of test modes are entered. CONSTITUTION: A test mode entry signal generating part(100) receives a mode register setting signal(MRS) and the first address signal(add_7) to generate a test mode entry command signal(tmregset). An address latch part(200) for specific test mode selection generates a latched address signal(tmreg_x) in response to the test mode entry command signal, a specific address signal(add_x), and a power supply confirm signal(pwrup) indicating supply of a power supply voltage into a semiconductor memory device. A test mode exit signal generating part(300) outputs a test mode exit signal(tmregset) for completing all test modes in response to a precharge command signal(PCG), a test mode progress confirm signal(testmode), and the second address signal(add_10). A test mode control part(400) outputs the test mode progress confirm signal(testmode) in response to a test mode exit signal(tmexit), the specific test mode progress confirm signal, the power supply confirm signal, and the test mode access signal. A specific test mode exit signal generating part(600) outputs a specific test mode exit signal(dis_tm_x) for exiting a specific test mode in response to the mode register setting signal, the first address signal, the specific test mode progress confirm signal, the power supply confirm signal, and the test mode exit signal. A specific test mode control part(500) outputs the specific test mode process confirm signal in response to the latched address signal, the test mode progress confirm signal, and the specific test mode exit signal.

Description

Test device for each mode of semiconductor memory device {Test Device for Semiconductor Memory Device}

The present invention relates to a mode-specific test device of a semiconductor memory device for testing a semiconductor memory device for each mode.

In the semiconductor memory device, various test modes are set according to a test purpose. Such test modes may be applied independently, or a plurality of test modes may be applied in combination. However, in order to reduce the test cost of the semiconductor memory device, it is necessary to reduce the test time by applying a combination of test modes.

1 is a block diagram of a test apparatus for each mode of a semiconductor memory device according to the related art.

The test device block diagram for each mode of the conventional semiconductor memory device generates a test mode entry command signal (tmregset) for inputting the mode register setting signal MRS and the first address signal add_7 to enter the semiconductor memory device into the test mode. The test mode entry signal generator 100, the test mode entry command signal tmregset, a specific address (add_x) signal corresponding to a specific test mode, and a power supply confirmation signal pwrup informing the supply of power to the semiconductor memory device. Address latch unit 200 for generating a specific address signal (tmreg_x) latched by inputting a signal, a precharge (PCG) command signal, and a test mode progress confirmation signal (testmode) indicating whether the test mode is in progress. ) And a test mode exit signal tmexit for ending the test mode of the semiconductor memory device in response to the input of the second address signal add_10. The test mode exit signal generating unit 300 to output the test mode exit signal tmexit, the test mode entry command signal tmregset, and the power supply confirmation signal pwrup are inputted. Outputting a specific test mode progress confirmation signal (tm_x) indicating whether a specific test mode is in progress by inputting the test mode control unit 400 and the latched specific address signal tmreg_x and the test mode progress confirmation signal testtest. The specific test mode control unit 500 is configured.

2 is a detailed circuit diagram of the test mode entry signal generator 100 of FIG. 1.

In order to enter the test mode, the mode register setting signal MRS, which is a positive pulse signal, and the first address add_7 signal of the 'H' state are input, so that the output of the NAND gate 101 becomes a negative pulse signal. The signal passes through the inverter 103 to become a test mode entry command signal tmregset, which is a positive pulse signal.

3 is a detailed circuit diagram of the address latch unit 200 for selecting a specific test mode of FIG. 1.

Initially, since the power supply confirmation signal pwrup is in the 'L' state, the output of the inverter 205 having the input thereof becomes the 'H' state, and the NMOS transistor 207 is turned on so that the output of the inverter latch 209 is' H 'state, and the specific address signal tmreg_x latched through the inverter 211 after the inverter latch 209 is kept in the' L 'state, and after a predetermined time, the power supply confirmation signal pwrup is' H'. When transitioning to the state, the output of the inverter 205 is changed to the 'L' state, the NMOS transistor 207 is turned off, the output of the inverter latch 209 remains in the 'H' state, the rear end of the inverter latch 209 The latched specific address signal tmreg_x that has passed through the inverter 211 maintains the 'L' state.

At this time, if the specific address signal add_x corresponding to the specific test mode transitions to the 'H' state, the test mode entry command signal tmregset opens the transmission gate 203 to open the 'H' state of the specific address signal add_x. The output of the inverter latch 209 transitions to the 'L' state by passing through, and the specific address signal tmreg_x latched through the inverter 211 transitions to the 'H' state.

4 is a detailed circuit diagram of the test mode exit signal generator 300 of FIG. 1.

In order to exit the test mode, the positive charge signal precharge command signal PCG and the second address signal add_10 are transferred to the 'H' state. At this time, since the test mode progress confirmation signal (testmode) is entered, the state remains 'H'. Accordingly, the input node of the inverter 311 becomes a negative pulse equal to the precharge command signal pulse width, and the test mode exit signal tmexit becomes a positive pulse signal through the inverter 311. Here, the PMOS transistor 309 which receives the output of the inverter 311 is for stably maintaining the test mode exit signal tmexit in the 'L' state before and after a positive pulse.

5 is a detailed circuit diagram of the test mode controller 400 of FIG. 1.

Initially, since the power supply confirmation signal pwrup is in the 'L' state, as shown in FIG. 3, the test mode progress confirmation signal (testmode) remains in the 'L' state, and when the test mode enters the test mode entry command signal ( When tmregset is inputted, the output of the inverter 401 becomes a negative pulse signal, and the PMOS transistor 403 is turned on by the pulse width to shift the output of the inverter latch 411 to the 'L' state, and then again The test mode progress confirmation signal (testmode) that passes through the inverter 413 maintains the 'H' state while testing the semiconductor memory device.

After all the tests of the semiconductor memory device are completed, the test mode exit signal (tmexit), which is a positive pulse signal, is turned on to turn on the NMOS transistor 405 to transfer the output of the inverter latch 411 to the 'H' state, and the inverter at the end The test mode progress confirmation signal (testmode) passed through (413) remains 'L' until the next test.

FIG. 6 is a detailed circuit diagram of the specific test mode controller 500 of FIG. 1.

When the test is performed in a specific mode, the test mode progress confirmation signal (testmode) is maintained in the 'H' state, and when the specific address (add_x) signal corresponding to the specific test mode transitions to the 'H' state, the latched specific address signal ( tmreg_x) transitions to the 'H' state. The outputs of the NAND gates 501-1, which are inputted to them, transition to the 'L' state, and then, through the inverter 503, the specific test mode progress confirmation signal tm_x transitions to the 'H' state to perform a specific test mode. Will be performed.

When exiting the test mode, the test mode progress confirmation signal (testmode) transitions to the 'L' state, so the output of the NAND gate 501-1 transitions to the 'H' state, and then passes the inverter 503 to the specific test. The mode progress confirmation signal tm_x transitions to the 'L' state to exit the specific test mode.

Eventually, the specific test mode is divided into the latched specific address signal (tmreg_x), and the test mode progress confirmation signal (testmode) is used for all the specific test mode controllers in common, so that when the test mode enters, the latched specific address signal (tmreg_x) Depending on the values, different test modes can be used, either individually or in combination, but all exits are exits.

The test mode method as described above may enter a plurality of test modes simultaneously or successively, but when a specific test mode is exited for the next test, all other test modes are also exited. This often leads to unsatisfactory switching between test modes, which in turn increases test time and increases test costs.

In order to solve the above problems, an object of the present invention is to provide a test device for each mode of a semiconductor memory device which can individually exit only a specific test mode desired when a plurality of test modes are entered.

1 is a block diagram of a test apparatus for each mode of a semiconductor memory device according to the related art;

2 is a detailed circuit diagram of a test mode entry signal generator of FIG. 1;

3 is a detailed circuit diagram of an address latch unit for selecting a specific test mode of FIG. 1;

4 is a detailed circuit diagram of a test mode exit signal generator of FIG. 1;

5 is a detailed circuit diagram of the test mode controller of FIG. 1;

6 is a detailed circuit diagram of a specific test mode controller of FIG. 1;

7 is a block diagram of a test device for each mode of the semiconductor memory device according to the present invention;

8 is a detailed circuit diagram of a specific test mode exit signal generator of FIG. 7;

FIG. 9 is a detailed circuit diagram of a specific test mode controller of FIG. 7. FIG.

<Description of the symbols for the main parts of the drawings>

100: test mode entry signal generator

200: address latch part for selecting a specific test mode

300: test mode exit signal generator

400: test mode control unit

500: specific test mode control unit

600: specific test mode exit signal generator

In order to achieve the above object, the test device for each mode of the semiconductor memory device of the present invention receives a mode register setting signal and a first address signal to generate a test mode entry command signal for entering the semiconductor memory device into a test mode. Entry signal generating means; An address latch for a specific test mode selection that generates a latched specific address signal by inputting the test mode entry command signal, a specific address signal for selecting a specific test mode, and a power supply confirmation signal informing power supply to a semiconductor memory device. Way; A test mode exit signal generating means for receiving a precharge command signal, a test mode progress confirmation signal indicating whether the test mode is in progress, and a second address signal and outputting a test mode exit signal for ending all of the test modes of the semiconductor memory device; Test mode control means for inputting the test mode exit signal, the test mode entry command signal and the power supply confirmation signal to output a test mode progress confirmation signal; A specific test outputting a specific test mode exit signal that receives only the mode register setting signal, the first address signal, the specific test mode progress confirmation signal, the power supply confirmation signal, and the test mode exit signal, and exits only a specific test mode. Mode exit signal generating means; And specific test mode control means for inputting the latched specific address signal, the test mode progress confirmation signal, and the specific test mode exit signal to output a specific test mode progress confirmation signal indicating whether a specific test mode is in progress. It is characterized by.

Preferably, the test mode entry signal generating means of the present invention, the NAND gate for receiving the mode register setting signal and the first address signal; And an inverter outputting a test mode entry signal by inverting the output of the NAND gate.

Preferably, the specific test mode selection address latch means of the present invention comprises: a first inverter for inverting and outputting the test mode entry signal; A transmission gate configured to receive an input signal and an output signal of the first inverter as a gate control signal to receive and transmit the specific address signal; A second inverter for inverting and outputting the power supply confirmation signal; An NMOS transistor receiving an output of the second inverter, a source connected to ground, and a drain connected to the output of the transmission gate; An inverter latch for inverting and outputting an output of the transmission gate; And a third inverter for inverting the output of the inverter latch and outputting a latched specific address.

Preferably, the test mode exit signal generating means of the present invention comprises: a first PMOS transistor receiving the precharge command signal and having a source connected to an external voltage; A first NMOS transistor receiving the test mode progress confirmation signal and having a drain connected to the drain of the first PMOS transistor; A second NMOS transistor receiving the precharge command signal and having a drain connected to a source of the first NMOS transistor; A third NMOS transistor receiving the second address signal and having a source connected to ground and a drain connected to a source of the second NMOS transistor; An inverter outputting the test mode exit signal by inverting the drain of the first PMOS transistor; And a second PMOS transistor connected to the output of the inverter and having a source connected to an external voltage and a drain connected to an input of the inverter.

Preferably, the test mode control means of the present invention, the first inverter for inverting and outputting the test mode entry signal; A first NMOS transistor receiving an output of the first inverter and having a source connected to an external voltage; A first NMOS transistor configured to receive the test mode exit signal, a source connected to ground, and a drain connected to the drain of the first PMOS transistor; A second inverter for inverting and outputting the power supply confirmation signal; A second NMOS transistor receiving an output of the second inverter, a source of which is connected to ground, a drain of which is connected to the drain of the first PMOS transistor; An inverter latch for inverting and outputting a drain of the first PMOS transistor; And a third inverter for inverting the output of the inverter latch and outputting the test mode progress confirmation signal.

Preferably, the specific test mode exit signal generating means of the present invention comprises: a first inverter for inverting and outputting the first address signal; A second inverter for inverting and outputting the specific test mode progress confirmation signal; A third inverter for inverting and outputting the specific address signal; A NAND gate as an input of the mode register setting signal and an output of the first inverter; A first PMOS transistor receiving an output of the NAND gate and having a source connected to an external voltage; A second PMOS transistor connected to the drain of the first PMOS transistor; A third PMOS transistor receiving an output of the third inverter and having a source connected to a drain of the second PMOS transistor; A first NMOS transistor configured to receive the test mode exit signal, a source connected to ground, and a drain connected to the third PMOS transistor; A fourth inverter for inverting and outputting the power supply confirmation signal; A second NMOS transistor receiving an output of the fourth inverter, a source connected to ground, and a drain connected to the drain of the third PMOS transistor; And an inverter latch for inverting the drain of the third PMOS transistor and outputting the specific test mode exit signal.

Preferably, the specific test mode control means of the present invention comprises: a NAND gate for inputting the latched specific address signal, the test mode progress confirmation signal, and the specific test mode exit signal; And an inverter outputting the specific test mode progress confirmation signal by inverting the output of the NAND gate.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

7 is a block diagram of a test device for each mode of the semiconductor memory device according to the present invention.

According to the present invention, the test mode entry signal generation unit 100 receives the mode register setting signal MRS and the first address signal add_7 and generates a test mode entry command signal tmregset for entering the test mode into the test mode. And a specific address signal latched by inputting the test mode entry command signal tmregset, a specific address signal add_x corresponding to a specific test mode, and a power supply confirmation signal pwrup informing the supply of power to the semiconductor memory device. a specific test mode selection address latch unit 200 for generating (tmreg_x), a precharge command signal PCG, a test mode progress confirmation signal testmode indicating whether the test mode is in progress, and a second address signal add_10 A test mode exit signal generation unit 300 which receives a input of a and outputs a test mode exit signal tmexit for ending all test modes of the semiconductor memory device; A test mode control unit 400 which outputs a test mode progress confirmation signal testmode by inputting a test mode exit signal tmexit, a test mode entry command signal tmregset and the power supply confirmation signal pwrup, and a mode. A register setting signal MRS, a first address signal add_7, a specific test mode progress confirmation signal tm_x, a power supply confirmation signal pwrup, and a test mode exit signal tmexit are input to exit only a specific test mode. Input a specific test mode exit signal generator 600 for outputting a specific test mode exit signal dis_tm_x, a latched specific address signal tmreg_x, a test mode progress confirmation signal testmode, and a specific test mode exit signal dis_tm_x. The specific test mode control unit 500 outputs a specific test mode progress confirmation signal tm_x indicating whether the specific test mode is in progress.

FIG. 8 is a detailed circuit diagram of the specific test mode exit signal generator 600 of FIG. 7.

Initially, since the power supply confirmation signal pwrup is in the 'L' state, the output of the inverter 609 is in the 'H' state, and the NMOS transistor 619 is turned on so that the specific test mode exit signal is the output of the inverter latch 621. (dis_tm_x) keeps 'H' state. After that, when the power supply confirmation signal pwrup transitions to the 'H' state, the output of the inverter 609 is transitioned to the 'L' state, and the NMOS transistor 619 is turned off.

When the semiconductor memory device enters the test mode, since the first address signal add_7 is in the 'H' state, the output of the inverter 601 is in the 'L' state, and the output of the NAND gate 603 is in the 'H' state, thereby causing the PMOS. Transistor 611 is in a turn off state. On the other hand, since the test mode exit signal tmexit also maintains the 'L' state, the NMOS transistor 617 is also turned off. Therefore, the specific test mode exit signal dis_tm_x continues to maintain the 'H' state set by the initial power supply confirmation signal pwrup.

If you want to exit all test modes, use the test mode exit signal (tmexit) as shown in FIG. Meanwhile, in order to exit only a specific test mode, the mode register setting command signal MRS and the first address signal add_7 which are positive pulse signals are set to 'L' state, and the specific address signal corresponding to the specific exit mode to be exited ( add_x) is set to 'H' state.

That is, since the first address signal add_7 is in the 'L' state, the output of the inverter 601 is in the 'H' state, and the output of the NAND gate 603 becomes a negative pulse signal to mode the PMOS transistor 611. The pulse width of the register setting signal MRS is turned on.

At this time, the specific test mode progress confirmation signal tm_x is maintained at the 'H' state, the output of the inverter 605 is at the 'L' state, and the PMOS transistor is turned on. In addition, since the specific address signal add_x is also in the 'H' state, the PMOS transistor 615 is also turned on. As a result, the input node of the inverter latch 621 is in the 'H' state, and the specific test mode exit signal dis_tm_x, which is the output of the inverter latch 621, is maintained in the 'L' state.

When all test processes are completed and the test mode exit signal (tmexit), which is a positive pulse signal, is turned on to exit all test modes, the NMOS transistor 617 is turned on by the pulse width and the inverter latch 621 input node is turned to 'L' state. Transition, and the specific test mode exit signal dis_tm_x, which is the output of the inverter latch, remains at the 'L' state.

FIG. 9 is a detailed circuit diagram of the specific test mode controller 500 of FIG. 7.

Unlike in FIG. 6, the three-input NAND gate 501-2 is used instead of the two-input NAND gate as one input of the specific test mode exit signal dis_tm_x.

When entering the test mode, the specific test mode exit signal dis_tm_x maintains the 'H' state, and thus, as in FIG. 6, the specific test mode progress confirmation signal tm_x maintains the 'H' state.

When the test mode exit is performed, a specific test mode exit signal corresponding to a specific test mode is used in addition to disabling all specific test mode progress confirmation signals (tm_x) using the test mode progress confirmation signal (testmode). dis_tm_x) to exit. That is, the test mode progress confirmation signal testmde maintains the 'H' state, but only the specific test mode exit signal dis_tm_x becomes the 'L' state, thereby transferring the output of the NAND gate 501-2 to the 'H' state. The specific test mode progress confirmation signal tm_x may be set to the 'L' state via the inverter 503.

The present invention described above is capable of various substitutions, modifications, and changes without departing from the technical spirit of the present invention for those skilled in the art to which the present invention pertains, and the foregoing embodiments and the accompanying drawings. It is not limited to.

According to the above configuration, the present invention can reduce the time taken to test the semiconductor echo device by allowing the individual exit of only a specific test mode desired when a plurality of test modes are entered.

Claims (7)

Test mode entry signal generation means for receiving a mode register setting signal and a first address signal to generate a test mode entry command signal for entering the semiconductor memory device into a test mode; An address latch for a specific test mode selection that generates a latched specific address signal by inputting the test mode entry command signal, a specific address signal for selecting a specific test mode, and a power supply confirmation signal informing power supply to a semiconductor memory device. Way; A test mode exit signal generating means for receiving a precharge command signal, a test mode progress confirmation signal indicating whether the test mode is in progress, and a second address signal and outputting a test mode exit signal for ending all of the test modes of the semiconductor memory device; Test mode control means for inputting the test mode exit signal, the test mode entry command signal and the power supply confirmation signal to output a test mode progress confirmation signal; A specific test outputting a specific test mode exit signal that receives only the mode register setting signal, the first address signal, the specific test mode progress confirmation signal, the power supply confirmation signal, and the test mode exit signal, and exits only a specific test mode. Mode exit signal generating means; And A specific test mode control means for inputting the latched specific address signal, the test mode progress confirmation signal, and the specific test mode exit signal to output a specific test mode progress confirmation signal indicating whether a specific test mode is in progress Mode-specific test device of a semiconductor memory device comprising a. According to claim 1, wherein the test mode entry signal generating means, A NAND gate configured to receive the mode register setting signal and the first address signal; And An inverter that inverts the output of the NAND gate and outputs a test mode entry signal Mode-specific test device of a semiconductor memory device comprising a. The address latch means for selecting a specific test mode according to claim 1, wherein A first inverter for inverting and outputting the test mode entry signal; A transmission gate configured to receive an input signal and an output signal of the first inverter as a gate control signal to receive and transmit the specific address signal; A second inverter for inverting and outputting the power supply confirmation signal; An NMOS transistor receiving an output of the second inverter, a source connected to ground, and a drain connected to the output of the transmission gate; An inverter latch for inverting and outputting an output of the transmission gate; And A third inverter that inverts the output of the inverter latch and outputs a latched specific address Mode-specific test device of a semiconductor memory device comprising a. The method of claim 1, wherein the test mode exit signal generating means, A first PMOS transistor receiving the precharge command signal and having a source connected to an external voltage; A first NMOS transistor receiving the test mode progress confirmation signal and having a drain connected to the drain of the first PMOS transistor; A second NMOS transistor receiving the precharge command signal and having a drain connected to a source of the first NMOS transistor; A third NMOS transistor receiving the second address signal and having a source connected to a ground and a drain connected to a source of the second NMOS transistor; An inverter outputting the test mode exit signal by inverting the drain of the first PMOS transistor; And A second PMOS transistor connected to the output of the inverter and having a source connected to an external voltage and a drain connected to an input of the inverter; Mode-specific test device of a semiconductor memory device comprising a. The method of claim 1, wherein the test mode control means, A first inverter for inverting and outputting the test mode entry signal; A first NMOS transistor receiving an output of the first inverter and having a source connected to an external voltage; A first NMOS transistor configured to receive the test mode exit signal, a source connected to ground, and a drain connected to the drain of the first PMOS transistor; A second inverter for inverting and outputting the power supply confirmation signal; A second NMOS transistor receiving an output of the second inverter, a source of which is connected to ground, a drain of which is connected to the drain of the first PMOS transistor; An inverter latch for inverting and outputting a drain of the first PMOS transistor; And A third inverter that inverts the output of the inverter latch and outputs the test mode progress confirmation signal Mode-specific test device of a semiconductor memory device comprising a. The method of claim 1, wherein the specific test mode exit signal generating means comprises: A first inverter for inverting and outputting the first address signal; A second inverter for inverting and outputting the specific test mode progress confirmation signal; A third inverter for inverting and outputting the specific address signal; A NAND gate as an input of the mode register setting signal and an output of the first inverter; A first PMOS transistor receiving an output of the NAND gate and having a source connected to an external voltage; A second PMOS transistor configured to receive an output of the second inverter, and a source connected to a drain of the first PMOS transistor; A third PMOS transistor receiving an output of the third inverter and having a source connected to a drain of the second PMOS transistor; A first NMOS transistor configured to receive the test mode exit signal, a source connected to ground, and a drain connected to the third PMOS transistor; A fourth inverter for inverting and outputting the power supply confirmation signal; A second NMOS transistor receiving an output of the fourth inverter, a source connected to ground, and a drain connected to the drain of the third PMOS transistor; And An inverter latch for inverting the drain of the third PMOS transistor to output the specific test mode exit signal Mode-specific test device of a semiconductor memory device comprising a. The method of claim 1, wherein the specific test mode control means, A NAND gate inputting the latched specific address signal, the test mode progress confirmation signal, and the specific test mode exit signal; And An inverter that inverts the output of the NAND gate and outputs the specific test mode progress confirmation signal Mode-specific test device of a semiconductor memory device comprising a.