KR20030023040A - Direct chip attaching package, manufacturing method thereof and stacked direct chip attaching package - Google Patents

Abstract

PURPOSE: A direction chip attaching package, a method for fabricating the same, and a stacked direct chip attaching package are provided to reduce an area of a package on a board by stacking two or three semiconductor chips. CONSTITUTION: A wafer(110) including a semiconductor chip having a bonding pad(150) is prepared. A conductive line(220) is formed on a scribe line of the wafer(110). An upper rearranging line(230) for connecting the conductive line(220) with the bonding pad(150) is formed. The bonding pad(150) and the upper rearranging line(230) are molded. A lower face of the wafer(110) is grinded. A lower rearranging line(240) is formed. The lower rearranging line(240) is connected with the conductive line(220). The lower rearranging line(240) is molded. A solder ball is formed on the lower rearranging line(240) or the upper rearranging line(230).

Description

Direct chip attach package, manufacturing method and stacked direct chip attach package TECHNICAL FIELD

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor packages, and more particularly to a direct chip attach package (DCAP) that is advantageous for a stack.

In recent years, electronic products have been increasing in size while being smaller in size. Therefore, the semiconductor chip package used for this also tends to be light and thin. As a result, it has evolved from a ball grid array (BGA) package to a wafer level chip scale package (WL-CSP).

1 is a cross-sectional view illustrating a wafer level chip scale package according to the prior art. Referring to FIG. 1, a nitride layer 20 is formed on an upper surface of a semiconductor chip, and a bonding pad 50 is formed between the nitride layers 20. A redistribution line is connected to the bonding pad 50 of the semiconductor chip, and another portion of the redistribution line is connected to the solder ball 70. A first insulating layer 30 is formed between the nitride layer 20 and the repositioning line 60, and a second insulating layer is disposed on the repositioning line 60 and the first insulating layer 30. 40) is formed.

The relocation line 60 performs a function of electrically connecting the semiconductor chip 10 and the solder ball 70, and may be appropriately disposed according to the position of the solder ball 70. The solder ball 70 connected to the semiconductor chip 10 through the rearrangement line 60 functions as an external connection terminal.

The wafer-level chip scale package can be easily adjusted to position the solder ball 70 by appropriately disposing the repositioning line 60 and is useful for forming a package of a semiconductor chip size. However, when mounted on a board (Board, not shown), the solder ball 70, the relocation line 60 and the actual circuit due to the coefficient of thermal expansion (CTE: Coefficient of Thermal Expansion) may be damaged, the solder ball Reliability is lowered by alpha ray which is a kind of radiation contained in. In addition, the wafer level CSP including a micro surface mount device (uSMD), an ultra chip scale package (UlCSP), a mini ball grid array (MiniBGA), etc., is difficult to construct a stack package. And if a wafer level CSP without a redistribution line is desired, the position of the solder ball 70 should be consistent with the position of the bond pad. This is because at least 500um of spacing is required to attach the solder balls 70 to the board.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a semiconductor package capable of securing protection and reliability of an actual circuit and stacking chips at a wafer level.

Another object of the present invention is to provide a method of manufacturing the semiconductor package.

Another object of the present invention is to provide a stacked semiconductor package of the semiconductor package.

1 is a cross-sectional view illustrating a wafer level chip scale package according to the prior art.

2 to 9 are diagrams for explaining a method of manufacturing a direct chip attach package according to an embodiment of the present invention.

10 is a cross-sectional view illustrating a structure of a direct chip attach package according to an embodiment of the present invention.

11 is a cross-sectional view illustrating a structure of a direct chip attach package according to a modified example of the embodiment of the present invention.

12 is a cross-sectional view illustrating a stacked structure of a direct chip attach package according to an embodiment of the present invention.

<Description of Signs of Major Parts of Drawings>

120: nitride layer, 150: bonding pad, 160: semiconductor chip, 220: conductive line,

230: top redistribution line, 240: bottom relocation line,

310,320 insulation material, 330 epoxy molding compound,

410: solder ball, 515: bump

In order to solve the above technical problem, a direct chip attach package according to the present invention includes a semiconductor chip having a bonding pad on an upper surface thereof, a conductive line filled with a conductive material in a via hole formed in a scribe line at an edge of the semiconductor chip, the bonding pad, and the A relocation line including an upper surface relocation line electrically connecting one end of the conductive line on the upper surface of the semiconductor chip and a lower surface relocation line connected to one end of the conductive line on the lower surface of the semiconductor chip, the bonding pad, a molding material for molding the relocation line, and the It includes solder balls formed on the relocation line.

The solder balls are preferably formed on the lower surface relocation line.

In addition, the diameter of the conductive wire is preferably formed in the range of 0.02mm to 0.3mm, the depth of the conductive wire is preferably formed in the range of 60um to 300um.

As the molding material, it is preferable to use any one material selected from the group consisting of BCB, polyimide, and a developable dielectric material.

In the method of manufacturing a direct chip attach package according to the present invention for solving the above technical problem, a conductive line is formed on a scribe line of the wafer after preparing a wafer having a semiconductor chip having a bonding pad on an upper surface thereof. Subsequently, an upper surface rearrangement line connecting the conductive line and the bonding pad is formed on the upper surface of the wafer, and the bonding pad and the upper surface rearrangement line are molded. Subsequently, the lower surface of the wafer is ground, a lower surface redistribution line connected to the conductive line is formed on the lower surface of the wafer, and the lower surface redistribution line of the lower surface of the wafer is molded. Then, solder balls are formed on the lower surface relocation line or the upper surface relocation line to unify the semiconductor chip.

The forming of the conductive line may include forming a plurality of via holes formed in a pair in the scribe line and filling the via holes with a conductive material.

In addition, the thickness of the ground wafer is preferably formed in the range of 50um to 300um.

The stack direct chip attach packages according to the present invention for solving the above technical problem have a structure in which the direct chip attach packages are stacked up and down.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present embodiment is not limited to the embodiments disclosed below, but will be implemented in various forms, and only this embodiment is intended to complete the disclosure of the present invention, and to those skilled in the art to fully understand the scope of the invention. It is provided to inform you. Shapes of the elements in the drawings may be exaggerated parts to emphasize a more clear description, elements denoted by the same reference numerals in the drawings means the same element.

2 to 9 illustrate a method of manufacturing a direct chip attach package according to an embodiment of the present invention. First, as shown in FIG. 2, a plurality of semiconductor chips having a bonding pad 150 on an upper surface thereof are illustrated. The prepared wafer 110 is prepared. The nitride layer 120 is formed on an upper surface of the semiconductor chip, and the nitride layer 120 has a bonding pad 150 that is a passage through which an electrical signal when the semiconductor chip operates. In addition, the semiconductor chips are divided based on the scribe line 170. Subsequently, as shown in FIG. 3, a plurality of via holes 210 formed as a pair are formed in the scribe line 170. The via hole 210 is formed using an etching technique or a laser system. Subsequently, as shown in FIG. 4, the conductive layer 220 is formed in the scribe line 170 of the wafer 110 by filling the via hole 210 of FIG. 3 with a conductive material. As the conductive material, it is preferable to use silver epoxy paste, solder paste, or Ag, Au, or Ni. The paste material may be filled into the via hole using a screen printing apparatus, and the Ag, Au, and Ni may be coated on the via hole surface using sputtering, electroless planting, or electroless plating. .

5A is a cross-sectional view illustrating a step of forming a top rearrangement line 230 connecting the conductive line 220 and the bonding pad 150 to an upper surface of the wafer 110, and FIG. 5B is a plan view of FIG. 5A. will be. 5A and 5B, the rearrangement line 230 is connected to the bonding pad 150 of the upper surface of the semiconductor chip to electrically connect the semiconductor chip and the conductive line 220. In addition, when a plurality of semiconductor chips are stacked, they may function as portions connected with solder balls (not shown) and appropriately disposed according to the positions of the solder balls. Refer to the description of FIG. The material used as the upper surface repositioning line 230 is preferably an alloy of TiW and Cu, an alloy of Cr and Cu Al and Ni, or an alloy of Al, Ni and Cu.

Subsequently, as illustrated in FIG. 6, the bonding pad 150, the nitride layer 120, the top rearrangement line 310, and the conductive line 220 are formed on the semiconductor chip. As the molding material 310, it is preferable to use any one material selected from the group consisting of BCB, polyimide, and a developing dielectric material. After coating the wafer using the material, a mask is used to develop a spot and a scribe line to which the bump is attached.

As the molding material, an epoxy molding compound (EMC), which is more effective for protecting an active circuit, may be used. In this case, an epoxy molding compound may be transferred to the entire surface of the wafer and then sawed in a subsequent process. As the work progresses, the work process is simple and production cost can be reduced. However, when molded with epoxy, although it can be used as a single semiconductor chip package, there is a disadvantage in that semiconductor chips cannot be stacked. This is because epoxy is difficult to etch.

Subsequently, in order to reduce the thickness of the wafer 110 as illustrated in FIG. 7, the process of grinding the lower surface of the wafer is performed. The thickness of the ground wafer is preferably formed in the range of 50um to 300um, and the conductive line 220 is guided to the bottom surface of the wafer after grounding. By going through this process, the thickness when the DCAP is stacked becomes very thin.

Subsequently, as shown in FIG. 8, a lower surface rearrangement line 240 connected to the conductive line 220 is formed on the lower surface of the wafer. The lower rearrangement line 240 is a portion in electrical contact with the solder ball (not shown), and is appropriately disposed according to the position of the solder ball. The material used as the lower surface rearrangement line 230 is preferably the same as the upper surface rearrangement line.

FIG. 9 is a cross-sectional view illustrating a process of molding the lower surface rearrangement line and the conductive line on a lower surface of a wafer and forming a solder ball. Referring to FIG. 9, BCB, polyimide, or a developable dielectric material, which is an insulating material, is used to mold the bottom rearrangement line 240 and the bottom surface of the semiconductor chip. Subsequently, when the insulating material is developed at the position where the solder ball is to be attached, a portion of the relocation line is exposed. Subsequently, a solder ball is attached to the exposed lower surface redistribution line 240. The solder ball attaching method may be performed using a solder ball mounting apparatus or a screen printing process. Subsequently, the wafer sawing process is performed along the scribe line of the wafer, thereby forming a DCAP as shown in FIG. 10.

10 is a cross-sectional view illustrating a structure of a direct chip attach package according to an embodiment of the present invention. Referring to FIG. 10, a DCAP according to the present invention includes a semiconductor chip 160 having a bonding pad 150 on an upper surface thereof, a conductive line 220 at an edge of the semiconductor chip, and a bonding pad 150 and a conductive line 220. A redistribution line consisting of an upper surface redistribution line 230 electrically connecting the lower surface redistribution line and a lower surface rearrangement line 240 connected to the conductive end of the lower surface of the semiconductor chip, a solder ball 410 and a molding material connected to the lower surface rearrangement line 240. (310,320).

The conductive line 220 is formed by forming a via hole in the scribe line at the edge of the semiconductor chip and then filling the via hole with a conductive material. The diameter of the conductive wire is preferably formed in the range of 0.02mm to 0.3mm, the depth of the conductive wire is preferably formed in the range of 60um to 300um.

The redistribution lines 230 and 240 perform a function of electrical connection means and have a proper arrangement structure according to the position of the solder ball. When the solder ball 410 is attached to the lower surface of the semiconductor chip in order to secure reliability by protection of the physical circuit and -ray protection, the solder ball 410 is attached to the lower surface redistribution line 240. On the other hand, when the direct chip attach package is configured in a plurality of stacked forms, bumps 515 of FIG. 12 may be attached to the top rearrangement line 230 as necessary. As the material of the relocation vessel, refer to the above-mentioned contents in the method for manufacturing a DCAP according to the present invention.

The molding members 310 and 320 mold the upper and lower surfaces of the semiconductor chip to insulate the semiconductor chip and reduce impact from the outside. That is, the bonding pad 150, the nitride layer 120, and the upper surface rearrangement line 230 of the upper surface of the semiconductor chip are molded, and the lower surface rearrangement line 240 of the lower surface of the semiconductor chip is molded. As the material of the molding material, it is preferable to use BCB, polyimide, or developable dielectric material.

The solder ball 410 is attached to the bottom rearrangement line 240. However, in the stacked DCAP to be described with reference to FIG. 12, bumps 515 of FIG. 12 may be attached to the top repositioning line 230 as necessary. The bump functions as an external terminal. It is preferable to use solder or a conductive material such as Au or Ni as the material of the bump.

FIG. 11 is a cross-sectional view illustrating a structure of a direct chip attach package according to a modification of an embodiment of the present invention, and will be described with respect to differences from the structure of the direct chip attach package according to an embodiment of the present invention. Compared with the direct chip attach package according to the exemplary embodiment of the present invention, epoxy is used as the molding material 330 for molding the upper surface of the semiconductor chip 110. Epoxy has the advantage of excellent insulation and protection from external impact and short work time compared to BCB or polyimide. However, it cannot be used as a stacked structure, and can only be used as a single package. This is because epoxy is difficult to etch.

12 is a cross-sectional view illustrating a stacked structure of a direct chip attach package according to an embodiment of the present invention. Referring to FIG. 12, two DCAPs are stacked. The lower DCAP 520 is attached to the relocation line if the solder ball, the upper DCAP 510 is attached to the relocation line if the bump 515. However, the bump 515 attached to the lower surface relocation line of the upper DCAP 510 may be stacked on the lower DCAP 520 in a structure attached to the upper surface rearrangement line.

As a method of stacking DCAP, two wafers having a plurality of DCAPs can be stacked at a wafer level, and then a sawing process may be performed using a blade (not shown). Alternatively, the DCAP may be stacked by a sawing process.

As described above, the DCAP according to the present invention is capable of stacking two semiconductor chips or three semiconductor chips, so that the occupied space occupied by the package on the board is small, so that it is easy to perform board design. In addition, the stacked DCAP is very thin because it uses background technology after the relocation line process.

Claims (10)

A semiconductor chip having a bonding pad on the top surface thereof; A conductive line filled with a conductive material in a via hole formed in a scribe line at an edge of the semiconductor chip; A relocation line including an upper surface relocation line electrically connecting the bonding pad and one end of the conductive line on the upper surface of the semiconductor chip and a lower surface relocation line connected to one end of the conductive line on the lower surface of the semiconductor chip; A molding material molding the bonding pad and the relocation line; And Direct chip attach package comprising a solder ball attached to the relocation line. The direct chip attach package of claim 1, wherein the solder balls are formed on a bottom surface relocation line. The direct chip attach package of claim 1, wherein the conductive wire has a diameter ranging from 0.02 mm to 0.3 mm. The direct chip attach package of claim 1, wherein a depth of the conductive line is in a range of 60 μm to 300 μm. The direct chip attach package of claim 1, wherein the molding material is any one selected from the group consisting of BCB, polyimide, and a dielectric material capable of developing. (a) preparing a wafer having a semiconductor chip having a bonding pad on the top surface thereof; (b) forming a conductive line on the scribe line of the wafer; (c) forming an upper surface rearrangement line connecting the conductive line and the bonding pad of the upper surface of the wafer; (d) molding the bonding pad and the upper surface repositioning line; (e) grinding the bottom surface of the wafer; (f) forming a bottom rearrangement line connected to the conductive line on the bottom surface of the wafer; (g) molding the lower surface relocation line on the lower surface of the wafer; (h) forming a solder ball on the bottom relocation line or the top relocation line; and (i) unifying the semiconductor chip; and manufacturing a direct chip attach package. 7. The direct chip attach package of claim 6, wherein the step (b) comprises forming a plurality of via holes formed in a pair in the scribe line and filling the via holes with a conductive material. Manufacturing method. The method of claim 7, wherein the via hole is processed using etching or laser equipment. The method of claim 6, wherein the ground wafer has a thickness in a range of 50 μm to 300 μm. The stacked direct chip attach package of claim 1, wherein the direct chip attach packages are stacked up and down.