KR20030016401A - Fast switching input buffer - Google Patents

Abstract

An input buffer circuit 300 for a semiconductor device including a PMOS transistor 306, an NMOS transistor 308, and a pull-up circuit 314. The pull-up circuit 314 applies a voltage to the bulk region of the PMOS transistor 306 to positively lower the absolute value of the threshold voltage of the PMOS transistor 306 when the input buffer 300 is switched. Causes This allows the input buffer 300 to switch faster than the conventional input buffer. The input buffer 300 is an inverter, NOR, NAND or other input buffer.

Description

Fast Switching Input Buffer {FAST SWITCHING INPUT BUFFER}

Complementary metal oxide semiconductor (CMOS) input buffers have long been used in semiconductor devices. An important characteristic of the input buffer is the switching time, which is the time required to transition from high to low or vice versa.

1 shows an example of a conventional CMOS inverter input buffer 100 for a semiconductor device. CMOS inverter input buffer 100 includes a P-channel MOSFET transistor 106, also referred to as a PMOS transistor, and an N-channel MOSFET transistor, also referred to as an NMOS transistor, in a complementary configuration. The gates of the PMOS and NMOS transistors 106 and 108 are connected to an input node 102, also called an input terminal. Since both gates are connected to the input node 102, the input signal is also called the gate voltage (Vg). The output signal is transmitted from an output node 110, also called an output terminal. The output node 110 is connected to the drains of the PMOS and NMOS transistors 106 and 108. When a low signal near zero volts is applied to the input node 102, the PMOS transistor 106 is on and the NMOS transistor 108 is off to make the output node 110 high. When a high signal close to the supply voltage is applied to the input terminal 102, the PMOS transistor 106 is turned off and the NMOS transistor 108 is turned on to bring the output node low. Since one of the PMOS and NMOS transistors is off, the consumption is very small even if there is a DC current.

2 shows an example of a conventional CMOS NOR input buffer 200. The CMOS NOR input buffer 200 includes first and second PMOS transistors 210 and 212 and first and second NMOS transistors 214 and 216. Gates of the second PMOS transistor 212 and the first NMOS transistor 214 are connected to the input node 202. The output signal is transmitted from an output node 220 connected to the drain of the second PMOS transistor and the drains of the first and second NMOS transistors 214 and 216. The control signal "Power down" is received at the control node 218. The control node 218 is connected to the gates of the first PMOS transistor 210 and the second NMOS transistor 216.

The present invention relates to a CMOS input buffer for a semiconductor device.

The invention has been described with reference to the accompanying drawings. Reference numerals in the drawings denote the same or functionally similar components. In addition, the leftmost digit of the reference numeral is the same as the reference numeral.

1 illustrates a conventional CMOS inverter input buffer.

2 illustrates a conventional CMOS NOR input buffer.

Figure 3 illustrates an embodiment of the invention with respect to a CMOS inverter input buffer.

4 illustrates an embodiment of the invention with respect to a CMOS NOR input buffer.

Fig. 5 shows a cross-sectional view of a PMOS transistor incorporating the components of the present invention.

Input buffer circuits for semiconductor devices include PMOS transistors, NMOS transistors, and pull-up circuits. The pull-up circuit supplies a voltage to the bulk region of the PMOS transistor to cause a positive substrate bias effect that temporarily lowers the absolute value of the threshold voltage of the PMOS transistor when the input buffer is switched. This switches the input buffer at a higher speed than the conventional input buffer. Input buffers include inverters, NOR, NAND, or other input buffers.

Input devices for semiconductor devices, such as memory devices such as SRAM and DRAM, provide fast switching between high and low states. Input devices have low current leakage and operate at low supply voltages. The present invention temporarily lowers the absolute value of the threshold voltage to reduce switching time without generating substantial current leakage.

The input buffer monitors the input node of the signal and switches the output node based on this input node. Circuits other than this input buffer and output node operate between the supply voltage Vcc and ground, while the signals received at the input may be in a narrow range (eg Vih and Vil). Vih represents the "high" signal and Vil represents the "low" signal. Due to line capacitance and other factors, Vil is often above ground and Vih is often below supply voltage.

PMOS transistors tend to switch at very slow speeds when operating at low supply voltages. A low supply voltage means a supply voltage less than 3.3 volts, such as 1.8 volts or 1.6 volts. For many applications, it is desirable to have the switches operate as soon as possible.

The principle of CMOS design is that PMOS transistors are "weak" than NMOS transistors. This is due to the mobility factor. Since the absolute value of the threshold voltage (| Vt |) of the PMOS transistor is high compared to the threshold voltage of the NMOS transistor, the switching time from "high" to "low" of the input buffer is generally higher than the switching time from "low" to "high". fast. The threshold voltage is used to determine whether the signal on the input line is high or low. If the absolute value of the threshold voltage of the PMOS transistor is lowered to reduce the switching speed, the current leakage of the PMOS transistor is increased, which is undesirable. The present invention is to temporarily lower the absolute value of the threshold voltage in order to reduce the switching time without generating substantial current leakage, as shown in FIGS. 3 to 5.

3 shows an example of a CMOS inverter input buffer 300 with high speed switching and low current leakage. The CMOS inverter input buffer 300 includes a PMOS transistor 306, a complementary NMOS transistor 308, a pullup element 314, and an optional capacitor 312. Gates of the PMOS and NMOS transistors 306 and 308 are connected to the input node 302. The output signal is transmitted from the output node 310, and the output node 310 is connected to the drains of the PMOS and NMOS transistors 306 and 308. For example, a pullup element 314, such as a resistor, is connected to the supply voltage and the bulk region of the PMOS transistor 306.

The resistance of the pull-up element 314 depends on the characteristics of the input buffer 300, and in particular on the characteristics of the PMOS transistor 306. For example, the resistance value can be 1KΩ to 3000KΩ. If a voltage can be provided to the bulk region of the PMOS transistor, other pull-up devices 314 such as RL circuits or diodes may also be used. Pull-up element 314 serves as a charging mechanism to supply voltage to the bulk region of PMOS 306.

The optional capacitor 312 is connected to the gate and bulk region of the PMOS transistor. When the PMOS and NMOS transistors 306 and 308 do not provide enough input capacitance to increase the switching time of the buffer, the capacitor 312 adds the gate capacitance to the input buffer 300.

When the input signal goes low, that is, when Vil is received at the input node 102, the gate capacitance temporarily pulls the bulk region of the PMOS transistor 306 low. This reduces the absolute value of the threshold voltage (| Vt |). Thus, the PMOS transistor 306 is "stronger" so that the current moves faster through the P-channel. The pull-up element 314 recharges the bulk region of the PMOS transistor 306 with the supply voltage after the output is switched high. Optionally, the PMOS transistor 306 and the pullup element 314 may be connected to different supply voltages.

4 shows an example of a CMOS NOR input buffer 400 with fast switching and low current leakage. CMOS NOR input buffer 400 includes first and second PMOS transistors 410 and 412, first and second NMOS transistors 414 and 416, first and second pull-up elements 406 and 408, and And an optional capacitor 422. Gates of the second PMOS transistor 412 and the first NMOS transistor 414 are connected to the input node 402. The output signal is transmitted from an output node 420 connected with the drain of the second PMOS transistor 412 and the drains of the first and second NMOS transistors 414 and 416. Sources of the first and second NMOS transistors 414 and 416 are connected to ground. The source of the second PMOS transistor 412 is connected to the drain of the first PMOS transistor 410. The source of the first PMOS transistor 410 is connected to the supply voltage 404. The control signal, labeled "power down", is received at the control node 418. The control signal is connected to the gates of the first PMOS transistor 410 and the second transistor 416. Control node 418 and input node 402 are the inputs of the NOR circuit and the output node is the output of the NOR circuit.

The first pull-up element 406 is connected to the supply voltage and the bulk region of the first PMOS transistor 410. The second pull-up element 408, called a pull-up circuit, is connected to the supply voltage 404 and the bulk region of the second PMOS transistor 412. The resistance values of the pull-up elements 406 and 408 depend on the characteristics of the input buffer 400, and in particular, on the characteristics of the PMOS transistors to which the pull-up elements are connected. For example, the resistance values of the pull-up elements 406 and 408 may be from 1 KΩ to 3000 KΩ. Other values may be allowed depending on the characteristics of the input buffer 400. Pull-up elements 406 and 408 may include other circuits, such as, for example, RL circuits, RLC circuits, or diode circuits, as long as they can provide voltage to the bulk regions of PMOS transistors 410 and 412. The pull-up elements 406 and 408 of this embodiment serve as charging means for supplying voltage to the bulk regions of the PMOS transistors 410 and 412. In other embodiments, only one of two pull-up elements 406 and 408 may be used.

An optional capacitor 422 can be added to increase the gate capacitance. An optional capacitor 422 is connected to the gate and the bulk of the second PMOS transistor.

Optionally, the first PMOS transistor 410 and the pull-up elements 406 and 408 may be connected to different supply voltages, respectively. Conventional supply voltages are 5.0 volts and 3.3 volts. The present invention uses a low power input buffer. The low power input buffer has a supply voltage below 3.3 volts. For example, the supply voltage is approximately 2.0 volts to 1.0 volts. The invention can also be used in other supply voltage ranges.

5 is a cross-sectional view of a PMOS transistor 500 incorporating components of the present invention. PMOS transistor 500 includes an N-type substrate region 526, a dielectric region 524, two P-type regions 518 and 522, and a P-channel region 520 called N-well. An external interface of the PMOS transistor 500 includes a source 512, a gate 514, a drain 516 and a bulk 528. PMOS transistor 500 has a pull-up element 506 that connects bulk 528 with the supply voltage of source node 504. An optional capacitor 508 connects the gate 514 and the bulk 528. Gate 514 is connected to gate node 502 that receives a gate signal. The drain 516 is connected to the drain node 510 which transmits the output from the PMOS transistor 500. When a ground voltage of substantially zero volts is applied to the gate node 502, no P-channel is formed and drain 516 supplies the lowest current. When a negative voltage is applied to the gate node 502, electrons bounce off the surface to form the P-channel 520, which is a conducting region, for a positive current to flow from the source 512 to the drain 516.

In NMOS transistors, the body bias effect occurs when the potential difference between the backgate voltage (Vb) and the source potential (Vs), called Vbs, is changed negatively by the voltage of the input signal. Increase the absolute value of the threshold voltage. In the case of a PMOS transistor, the potential difference Vbs changes to a positive value to increase the absolute value of the threshold voltage. When this occurs in the NMOS transistor, the gate-source voltage Vgs decreases, the driving force of the NMOS transistor decreases, and the signal transfer resistance increases. This is called the negative body bias effect. The present invention temporarily lowers the absolute value of the threshold voltage of the PMOS transistor by using a complementary phenomenon called a positive body bias effect.

The two input buffers 300 and 400 (FIGS. 3 and 4) have a high DC threshold voltage that lowers voltage leakage. In addition, input buffers 300 and 400 have a low AC threshold voltage that provides fast switching and low leakage voltage. Such an input buffer is estimated to be able to switch from high to low in approximately 50% to 60% of the time of a conventional low voltage input buffer.

The input buffer 500 may be used in various devices, including semiconductor memory, mobile phone flash memory, logic circuits, and other circuits used in a computer. In a preferred embodiment, the input buffer 500 is used in a low power semiconductor memory.

When the input line switches from high to low (logical 1 to logic 0), the gate capacitance is temporarily lowered. This reduces the absolute value of the threshold voltage. The current then travels faster through the P-channel. This causes the output voltage Vo to switch from low to high more quickly. The bulk layer voltage Vbulk is recharged to fill the supply voltage through the pull-up element 506 after the output node 510 goes high. Optionally, a capacitor 508 is added to increase the capacitance between the gate and the bulk.

The following equation describes the effect on the absolute value of the threshold voltage.

| Vt | = V _t0 + δ * [sqrt (2Φ _F + V _bs )-sqrt (2Φ _F )]

here,

| Vt | is the absolute value of the threshold voltage of the PMOS transistor.

V _t0 is the threshold voltage when V _bs = 0.

δ is the bias effect constant of the substrate. This constant is a function of the manufacturing process and can vary between devices.

Φ _F is the bulk potential. Bulk potential is a function of the manufacturing process and can vary between devices.

Vbs is the voltage difference between the bulk region and the source.

To temporarily lower the absolute value of the threshold voltage (| Vt |) as the gate voltage goes from high to low, | Vbs | goes low and the bulk voltage Vb rises to the source voltage Vs, which is a bulk-source It means that the voltage (| Vbs |) is negative. When the gate voltage is switched low, the bulk voltage is connected to the gate voltage and lower than the supply voltage. This temporarily lowers the threshold voltage (| Vt |) of the PMOS transistor, causing the output voltage (Vout) to switch quickly.

The RC circuit (eg, 506 and 508 in Figure 5) is preferably adjusted to prevent latch-up when the bulk voltage is lower than the source voltage.

3 to 5 illustrate an inverter and a NOR input buffer, the present invention can be implemented in other types of input buffers used in semiconductor devices such as memory devices. For example, the present invention can be used for a NAND input buffer.

While the preferred embodiments have been illustrated and described, they are not intended to limit the present invention, but are intended to include methods and apparatus that can be modified and substituted all within the scope of the invention or its equivalents as defined in the appended claims. You should know

Claims (10)

As an input buffer circuit 300 for a semiconductor device, An input node 302, An output node 310, A PMOS transistor 306 having a source, a gate, a drain and a bulk node, the source node being connected to the first supply voltage 304; An NMOS transistor 308 having a source, a gate, a drain, and a bulk node, the source node of which is connected to ground; Wherein gate nodes of the PMOS and NMOS transistors 306 and 308 are connected to the input node 302 and drain nodes of the PMOS and NMOS transistors are connected to the output node 310; And a pull-up circuit (314) coupled to the bulk node of the PMOS transistor (306) and a second supply voltage (304). The input buffer circuit (300) of claim 1, wherein the input buffer circuit (300) is configured as a low power input buffer circuit. The input buffer circuit (300) of claim 1, wherein the first supply voltage (304) and the second supply voltage provide the same voltage. The input buffer circuit (300) of claim 1, wherein the first supply voltage (304) is 1.9 volts or less. 2. The input buffer circuit (300) of claim 1, wherein said pull-up circuit (314) is comprised of a resistor. 2. The input buffer circuit (300) of claim 1, further comprising a capacitor circuit (312) coupled to the source and bulk nodes of the PMOS transistor (306). The input buffer circuit (300) of claim 1, wherein the pull-up circuit (314) reduces the threshold voltage of the PMOS transistor (306) and reduces the switching time of the input buffer circuit (300). The input buffer circuit (300) of claim 1, wherein the input buffer circuit (300) is configured of a CMOS inverter circuit. First and second PMOS transistors 410 and 412 having an input node 402, an output node 420, a selection node 418, and a source, gate, drain, and bulk node, respectively, source, gate, respectively. First and second NMOS transistors 414 and 416 having drain and bulk nodes, The source node of the second PMOS transistor 412 is connected to the first supply 404, the source nodes of the first and second NMOS transistors 414, 416 are connected to ground, and the first and second NMOS The drain nodes of the transistors 414 and 416 are connected to the output node 420, the gate node of the first NMOS transistor 414 is connected to the input node 402, and the gate node of the second NMOS transistor 416 is Connected to the selection node 418, A drain node of the first PMOS transistor 410 is connected to the output node 420, a gate node of the first PMOS transistor 410 is connected to the input node 402, and the second PMOS transistor ( The gate node of 412 is an input buffer circuit 400 connected to the selection node 418, The first pullup circuit 406 is connected to the bulk node and the second supply voltage of the first PMOS transistor 410, and the second pullup circuit 408 is connected to the bulk node and the third supply voltage of the second PMOS transistor 410. Input buffer circuit 400, characterized in that connected. At least one NMOS transistor 308, at least one PMOS transistor 306 connected to the NMOS transistor 308, and a pull-up circuit 314 connecting a bulk node of the PMOS transistor 306 to a supply voltage 304. CMOS input circuit 300, And a memory array connected to the CMOS input circuit (300).