KR20030001870A - Semiconductor memory device with global io line - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a global input / output line, and more particularly to a semiconductor memory device having two or more banks and address cells for two or more DQs.

The present invention relates to a semiconductor memory device having two or more banks and address cells for two or more DQs, wherein the bank is divided into two and an upper division bank and a lower division bank are provided to have address cells for the same DQ. Are arranged adjacent to each other, and the upper global I / O line groups that transfer an arbitrary DQ of the upper divided bank are arranged side by side between left and right sides of the upper divided bank to which the same DQ is allocated, and the same DQ is allocated. A semiconductor memory device including a structure in which lower global I / O line groups that transfer arbitrary DQs of the lower divided banks are arranged side by side between left and right sides of the lower divided banks.

Description

Semiconductor memory device with global input / output lines {SEMICONDUCTOR MEMORY DEVICE WITH GLOBAL IO LINE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a semiconductor memory device having a global input / output line, and more particularly to a semiconductor memory device having two or more banks and address cells for two or more DQs.

A conventional memory device divided into two or more banks has a structure in which input / output lines connected to a plurality of banks are arranged long over the entire area of the device and transferred to an externally connected input / output pad.

1 shows an example of a device having four banks 10, 11, 12, 13 and 16 data pads (DQ pads, not shown). Each bank has an X Decoder 14 which can select row addresses separately and a Y Decoder 15 which can select column addresses separately for independent operation.

Each bank has address cells corresponding to 16 DQs that can accept 16 input / output signals. In addition, each bank is connected to a global IO line 16 that transmits 16 DQ signals. At this time, although the global input / output line 16 is not shown, 16 lines are comprised so that 16 data may be received.

Since the global input / output line 16 is disposed in the entire memory device, the delay difference between both ends of the global input / output line increases as the semiconductor device becomes highly integrated, low voltage, and high speed. This further increases the difficulty in securing margins in implementing high speeds.

Conventionally, it has been filed with Korean Patent Application No. 10-1998-0029314 as a method for solving the above problems.

That is, as shown in FIG. 2, a method of dividing one bank into several blocks, assigning only addresses corresponding to specific DQs to each block, and disposing global I / O lines only to corresponding DQ blocks of other banks is proposed. It became.

The first bank (bank 0) is DQ <0: 3> in the first block 20, DQ <4: 7> in the second block 21, and DQ <7:11> in the third block 22. The fourth block 23 includes address cells corresponding to DQ <12:15>.

In this case, the arrangement of the global input / output lines 24 corresponding to DQ <0: 3> may include the second bank (bank 1) and the fourth bank (bank 3) in the first block 20 of the third bank (bank 2). ) Extends to the first block 20. Although not shown in the figure, the global input / output lines are configured as four lines so that four data corresponding to the number of DQs, that is, DQ <0: 3> can be transferred.

In addition, the arrangement of the global input / output lines 25 corresponding to DQ <4: 7> may include the second bank (bank 1) and the fourth bank (bank 3) in the second block 21 of the third bank (bank 2). ) Extends to the second block 21.

The arrangement of the global input / output lines 26 corresponding to DQ <8:11> is performed by the third and second banks (bank 1) and fourth bank (bank 3) in the third block 22 of the third bank (bank 2). It extends to the third block 22.

The arrangement of the global input / output lines 27 corresponding to DQ <12:15> may be arranged in the fourth block 23 of the third bank (bank 2) of the second bank (bank 1) and the fourth bank (bank 3). It extends to the fourth block 23.

In this case, reference numeral 28 denotes an X decoder capable of selecting a row address, and 29 denotes a Y decoder in which a column address can be selected.

The global I / O lines configured as described above can reduce the delay difference by reducing the length of the global I / O lines than the arrangement shown in FIG. 1.

However, even in the arrangement of the global input / output lines shown in FIG. 2, in the graphics memory device having 32 input / output data or the DDR SDRAM which requires twice the input / output lines, the layout area of the global input / output lines arranged throughout the device and the high speed operation are increased. It is also a bottleneck in margins at.

Accordingly, an object of the present invention is to provide a semiconductor memory device capable of efficiently arranging global input / output lines to efficiently reduce the length of the global input / output lines.

1 is a view for explaining a semiconductor memory device having a global input and output line according to the prior art.

FIG. 2 is a diagram for describing a semiconductor memory device having a conventional global input / output line for solving the problem of FIG. 1.

3 is a diagram for describing a semiconductor memory device having a global input / output line according to an embodiment of the present invention.

4 and 5 are diagrams for explaining an application example to the embodiment of FIG.

6 and 7 illustrate a semiconductor memory device having a global input / output line in accordance with another embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

30, 110: first upper division bank 31, 111: second upper division bank

32, 112: third upper division bank 33, 113: fourth upper division bank

40, 120: first subdivision bank 41, 121: second subdivision bank

42, 122: third subdivision bank 43, 123: fourth subdivision bank

34: upper global I / O line group 35, 45, 50: X decoder

36, 46, 60: Y decoder 101: first block

102: second block 103: third block

104: fourth block 150: first upper global input / output line group

160: second upper global I / O line group

170: first lower global I / O line group

180: second lower global I / O line group

A semiconductor memory device having a global input / output line of the present invention for achieving the above object is a semiconductor memory device having two or more banks and address cells responsible for two or more DQs. An upper global bank and a lower divided bank formed adjacent to each other so as to have a corresponding address cell and adjacently arranged, and an upper global that transfers an arbitrary DQ of the upper divided bank between left and right sides of an upper divided bank to which the same DQ is allocated. A semiconductor memory device including a structure in which an input / output line group is arranged side by side, and a lower global input / output line group, which transfers an arbitrary DQ of the lower division bank, is arranged side by side between left and right sides of a lower division bank to which the same DQ is allocated. It characterized in that to provide.

In addition, according to the present invention, in a semiconductor memory device having two or more banks and address cells for two or more DQs, each of the banks is divided into two and divided into higher divisions to have address cells for the same DQ. A bank and a lower divided bank are formed adjacent to each other, and each of the upper divided bank and the lower divided bank is divided into two blocks, and a first block and a second block are allocated, and a first block of the upper divided bank is allocated. An upper first global I / O line group configured to carry data inputted and outputted from the second uppermost global input / output line group to the data pad, and to carry the data input and output from the second block of each upper divided bank to the data pad; The data input / output data of the first block of each subdivision bank is transferred to a data pad. And arranging a lower first global input / output line group, and a lower second global input / output line group configured to load data input / output in a second block of each subdivision bank to a data pad. It is characterized by providing.

In addition, according to the present invention, an upper division bank and a lower division bank are provided so that two or more banks and address cells are in charge of two or more DQs, and each bank is divided into two to have address cells in charge of the same DQ. A semiconductor memory device in which a first block and a second block are allocated by dividing each of the upper and lower partition banks into two blocks and assigning a first block and a second block. Arrange the upper and lower partition banks so that data input and output from a cell can be transferred up and down in adjacent banks, and arrange the data pads in a row to transfer data to external pins between the upper partition banks. The data input and output from the first block of each upper division bank is loaded. A T-shaped upper first global I / O line group to be transmitted to the pad is disposed, and a T-shaped upper second to load data input / output in the second block of each upper division bank to be transferred to the corresponding data pad, respectively. A T-shaped lower first global I / O line group for distributing data input and output in the first block of each subdivision bank and transferring the data to and from the corresponding data pad, respectively; A semiconductor memory device including arranging a lower second global I / O line group having a T-shape for loading data input and output from a second block of a lower division bank to a corresponding data pad is provided.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a diagram for describing a semiconductor memory device having a global input / output line according to an embodiment of the present invention, and FIGS. 4 and 5 are views for explaining an application example to the embodiment of FIG. 7 is a diagram for describing a semiconductor memory device having a global input / output line according to another exemplary embodiment of the present invention. In this case, in order to facilitate the description of the 16 DQs described below, the following description will be made by dividing DQ <0: 7> and DQ <8:15>.

As shown in FIG. 3, a semiconductor memory device having four banks having sixteen DQs is shown.

Referring to FIG. 2, in a method of dividing a conventional bank into blocks corresponding to specific DQs in the banks, the semiconductor memory device of the present invention does not divide the banks and arranges blocks that are responsible for a specific DQ in different locations. .

That is, the same DQ is allocated while dividing 16 DQs in one bank into two by eight. Here, each divided bank divided into DQs is referred to as an upper divided bank and a lower divided bank, respectively, according to positions. At this time, only the data corresponding to DQ <0: 7> can be stored in the address cell of the upper division bank, and only the data corresponding to DQ <8:15> are stored in the address cell of the lower division bank.

The upper division banks arranged in this way include the first to fourth upper division banks. The second upper division bank 31 is disposed below the first upper division bank 30, and the third upper division bank 32 is disposed on the right side of the first upper division bank 30. The fourth upper division bank 33 is disposed below the bank.

The lower divided bank also includes first to fourth lower divided banks. The second lower divided bank 41 is disposed on the lower side 40 of the first lower divided bank, and the third lower divided bank 42 is disposed on the right side of the first lower divided bank 40. The fourth lower division bank 43 is disposed below the bank 42.

Next, the upper global I / O line group for loading data corresponding to DQ <0: 7> of the upper divided bank between the left and the right of the first to fourth upper divided banks 30, 31, 32 and 33. 34 are arranged side by side, and data corresponding to DQ <8:15> of the lower divided banks is disposed between the left and right sides of the first to fourth lower divided banks 40, 41, 42 and 43. Lower global input / output line groups 44 for loading are arranged side by side. At this time, the upper and lower global I / O line groups 34 and 44 are arranged side by side by the number of DQs in the upper and lower divided banks, although not shown in the figure.

This arrangement does not take into account the location of data pads (DQ pads, not shown) for transferring data contained in the upper and lower global I / O line groups to the outside, or the data pads are divided at both ends of the device. In the case of an ODIC (Outer-DQ-Inter-Control) structure or in the center, the length of the global input / output line can be reduced by half compared to the conventionally proposed method, and reduced than the proposed method in FIG. do.

In this case, reference numerals 35 and 45 denote X decoders capable of selecting row addresses, and reference numerals 36 and 46 denote Y decoders in which column addresses can be selected.

4 shows an application example of the embodiment of FIG. 3.

That is, the X decoder 50 of the banks adjacent to each other is shared in the areas of the separated first to fourth upper division banks 30, 31, 32, and 33. The same is true of separate subdivision banks. This allows the number of X decoders to be cut in half due to the shared X decoders in each of the upper division banks adjacent to each other, and the structure is simplified. At this time, although not shown in the figure, there is further provided a means for selectively supplying a row address information signal output from the shared X decoder 50 to any one of the divided banks.

5 then illustrates the improved application of FIG. 3.

That is, the Y decoder 60 of the banks adjacent to each other is shared in the areas of the separated first to fourth upper division banks 30, 31, 32, and 33. The same is true of separate subdivision banks. This also allows the number of Y decoders to be halved due to the shared Y decoder of each higher division bank adjacent to each other, and the structure is simplified. Although not shown in the drawing, the apparatus further includes means for selectively supplying a column address information signal output from a shared Y decoder to any one of the divided banks.

Next, FIG. 6 illustrates another embodiment of the global input / output line arrangement method of the semiconductor memory device of the present invention. As shown in FIG. 6, the same DQs are allocated while dividing 16 DQs in one bank by eight. The upper divided bank and the lower divided bank are arranged as much as possible. At this time, only the data corresponding to DQ <0: 7> can be stored in the address cell of the upper division bank, and only the data corresponding to DQ <8:15> are stored in the address cell of the lower division bank. In addition, the divided upper and lower divided banks are divided into two blocks to allocate the first block and the second block.

In this case, only the data corresponding to DQ <0: 3> may be stored in the first block 101 of the upper division bank, and DQ 102 <4: in the second block 102 of the upper division bank. 7> Allocate the data so that it can be stored. Also, the first block 103 of the lower divided bank is allocated so that only data corresponding to DQ <8:11> can be stored, and the second block 104 of the lower divided bank is allocated to DQ <12:15>. Allocate only the relevant data.

The upper division banks arranged in this way include the first to fourth upper division banks. The second upper division bank 111 is disposed below the first upper division bank 110, and the third upper division bank 112 is disposed on the right side of the first upper division bank 100, and the third upper division bank is disposed. The fourth upper division bank 113 is disposed below the bank.

The lower divided bank also includes first to fourth lower divided banks. The second lower divided bank 121 is disposed on the lower side 120 of the first lower divided bank, the third lower divided bank 122 is disposed on the right side of the first lower divided bank 120, and the third lower divided bank is disposed. The fourth lower division bank 123 is disposed below the bank 122.

Subsequently, the upper first global input / output line group 150 is disposed to share data input / output in the first block 101 of the first to fourth upper division banks 110, 111, 112, and 113. The upper second global I / O line group 160 is disposed to share data input / output in the second block 102 of the first to fourth upper banks 110, 111, 112, and 113.

In addition, the lower first global I / O line group 170 is disposed to share data input and output in the first block 103 of the first to fourth lower banks 120, 121, 122, and 123, The lower second global I / O line group 180 is disposed to share data input / output in the second block 104 of the first to fourth lower banks 120, 121, 122, and 123.

More specifically, the first upper global input / output line group 150 extends from the first block 101 of the first upper division bank 110 to the first block 101 of the second upper division bank 111. Data input and output at the first block 101 of each divided upper division bank is shared.

In addition, the second upper global input / output line group 160 extends from the second block 102 of the first upper division bank 110 to the second block 102 of the second upper division bank 111, respectively. The data inputted and outputted by the second block 102 of the divided upper partition bank is shared.

Subsequently, the first lower global input / output line group 170 extends from the first block 103 of the first lower division bank 120 to the first block 103 of the second lower division bank 121, respectively. The data inputted and outputted in the first block 103 of the divided subdivided bank is shared.

In addition, the second lower global I / O line group 180 extends from the second block 104 of the first lower division bank 120 to the second block 104 of the second lower division bank 121, respectively. Data input and output from the second block 104 of the divided subdivision bank is shared.

Such a structure can reduce the delay difference than the structure proposed in FIG. 3 by applying the same DQ proposed in FIG. 3 to the assigned upper and lower divided banks. In addition, although the scheme proposed in FIG. 6 is not shown in the figure, it may be efficient when a data pad (DQ Pad) is disposed at the center or across the device.

Next, FIG. 7 shows another embodiment of the present invention, in which the reference numerals of the same structures proposed in FIG. 6 are the same. As shown, the upper divided bank and the lower divided bank are arranged so that the same DQ is allocated while dividing the sixteen DQs in one bank two by eight. At this time, only the data corresponding to DQ <0: 7> can be stored in the address cell of the upper division bank, and only the data corresponding to DQ <8:15> are stored in the address cell of the lower division bank. Here, the upper and lower divided banks are arranged so that data input / output in the address cells of the upper divided bank and the lower divided bank can be transferred up and down in the banks adjacent to each other.

In addition, the divided upper and lower divided banks are divided into two blocks to allocate the first block and the second block. In this case, only the data corresponding to DQ <0: 3> may be stored in the first block 101 of the upper division bank, and DQ 102 <4: in the second block 102 of the upper division bank. 7> Allocate the data so that it can be stored. Also, the first block 103 of the lower divided bank is allocated so that only data corresponding to DQ <8:11> can be stored, and the second block 104 of the lower divided bank is allocated to DQ <12:15>. Allocate only the relevant data.

The upper division banks arranged in this way include the first to fourth upper division banks. The second upper division bank 111 is disposed below the first upper division bank 110, and the third upper division bank 112 is disposed on the right side of the first upper division bank 100, and the third upper division bank is disposed. The fourth upper division bank 113 is disposed below the bank.

The lower divided bank also includes first to fourth lower divided banks. The second lower divided bank 121 is disposed on the lower side 120 of the first lower divided bank, the third lower divided bank 122 is disposed on the right side of the first lower divided bank 120, and the third lower divided bank is disposed. The fourth lower division bank 123 is disposed below the bank 122.

In addition, the data pads DQ <0: 7> of the DQ <0: 7> are arranged in a line between the first upper division bank 110 and the third upper division bank 112, and the second upper division bank 111 and the second upper division bank 111 are arranged in a row. The data pads of DQ <8:15> are arranged in series between the four upper division banks 113.

Subsequently, as shown in FIG. 6, the upper first global I / O line group (eg, to share data input and output in the first block 101 of the first to fourth upper division banks 110, 111, 112, and 113). The upper second global I / O line group 160 so as to arrange 150 and share data input / output in the second block 102 of the first to fourth upper banks 110, 111, 112, and 113. Place it.

In addition, the lower first global I / O line group 170 is disposed to share data input and output in the first block 103 of the first to fourth lower banks 120, 121, 122, and 123, The lower second global I / O line group 180 is disposed to share data input / output in the second block 104 of the first to fourth lower banks 120, 121, 122, and 123.

More specifically, each global input / output line group 150, 160, 170, 180 is arranged in a T-shape. That is, the upper first global input / output line group 150 inputs and outputs the upper and lower sides in the first block 101 of the first to fourth upper banks 110, 111, 112, and 113. Arranged in the line direction with DQ <0; 3> to the data pad. In addition, the upper second global I / O line group 160 is shared data input and output upward and downward in the second block 102 of the first to fourth upper banks 110, 111, 112, and 113. And transfer it to the data pad of DQ <4: 7>.

In addition, the lower first global I / O line group 170 is shared data inputted to the upper and lower sides in the first block 103 of the first to fourth lower banks 120, 121, 122, and 123. Put DQ <8; 11> to a data pad arranged in a line direction. In addition, the lower second global I / O line group 180 is shared data input and output upward and downward in the second block 104 of the first to fourth lower division banks 120, 121, 122, and 123. And transfer it to the data pad of DQ <12:15>.

In this case, reference numeral 200 denotes an X decoder for selecting a row address, and reference numeral 300 denotes a Y decoder for selecting a column address.

By arranging in such a structure, delay difference between DQs due to the length of the global input / output line can be reduced.

In the above-described embodiment, the four-bank semiconductor memory device having 16 DQs has been described, but the present invention can also be applied to an N-bank semiconductor memory device having more DQs.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

According to the semiconductor memory device having the global input / output line of the present invention described above, by dividing the upper division bank and the lower division bank so as to cover any particular DQ, and efficiently reduce the length of the global input / output line, high integration, low voltage, The delay difference across the global I / O line due to the high speed can be reduced.

Therefore, the delay difference is a bottleneck in high speed operation, which can be effectively improved.

In addition, in the case of a product having a large number of input / output data, the area of the global input / output line increases as much as the difference in delay, but it can be reduced by disposing it so that it does not overlap.

Claims (14)

A semiconductor memory device having two or more banks and address cells for two or more DQs. The bank is divided into two, and an upper division bank and a lower division bank are formed so as to have address cells that are responsible for the same DQ. An upper global I / O line group configured to transfer an arbitrary DQ of the upper divided bank side by side between the left and right sides of the upper divided bank to which the same DQ is allocated, And a structure in which lower global I / O line groups that transfer an arbitrary DQ of the lower divided bank are arranged side by side between left and right sides of the lower divided bank to which the same DQ is allocated. Device. The method of claim 1, And the semiconductor memory device is a semiconductor memory device having four banks having sixteen DQs (DQ <0:15>). The method of claim 2, And the upper division bank includes first to fourth upper division banks, and the lower division bank includes first to fourth upper division banks. The method of claim 3, wherein Wherein the first to fourth upper division banks include address cells for DQ <0: 7>, and the first to fourth lower division banks include address cells for DQ <8:15>. A semiconductor memory device having a global input output line. The method of claim 4, wherein A second upper division bank is disposed below the first upper division bank, a third upper division bank is disposed on the right side of the first upper division bank, and a fourth upper division bank is located below the third upper division bank. Is placed, A second subdivision bank is disposed below the first subdivision bank, a third subdivision bank is disposed on the right side of the first subdivision bank, and a fourth subdivision bank is provided under the third subdivision bank. The semiconductor memory device having a global input output line, characterized in that disposed. The method of claim 5, An upper global I / O line group for arranging data corresponding to DQ <0: 7> of an upper divided bank is arranged side by side between left and right sides of the first to fourth upper divided banks, A lower global input / output line group for loading data corresponding to DQ <8:15> of the lower divided bank is arranged in parallel between left and right sides of the first to fourth lower divided banks. Semiconductor memory device. The method of claim 1, A Y decoder capable of discriminating and selecting column addresses of each divided bank formed in parallel with respect to a direction of the global input / output line group; And an X decoder capable of discriminating and selecting a row address between the upper and lower sides of each of the divided banks. The method of claim 1, An X decoder capable of discriminating and selecting a row address of each divided bank formed in parallel with respect to a direction of the global input / output line group; And a Y decoder for dividing and selecting column addresses between the upper and lower sides of the divided banks. The method of claim 7, wherein The X decoder is disposed in common between the adjacent respective divided banks, And a means for selectively supplying a row address fixing signal outputted from the common X decoder under control of a bank selection signal to any one bank of the divided banks. A semiconductor memory device having a. The method of claim 8, The Y decoder is disposed in common between the adjacent respective divided banks, And a means for selectively supplying a column address fixing signal outputted from the common Y decoder by being controlled by a bank selection signal, to any one bank of the divided banks. A semiconductor memory device having a. A semiconductor memory device having two or more banks and address cells for two or more DQs. Splitting each bank into two to form an upper division bank and a lower division bank so as to have an address cell for the same DQ; Dividing each of the upper divided bank and the lower divided bank into two blocks to allocate a first block and a second block; An upper first global input / output line group configured to carry data inputted to and outputted from a first block of each upper division bank to a data pad; An upper second global input / output line group configured to carry data inputted to and outputted from a second block of each upper division bank to a data pad; Arranging lower first global input / output line groups carrying data inputted to and outputted from a first block of each lower division bank to a data pad; And arranging a lower second global input / output line group that carries data inputted to and outputted from a second block of each lower division bank to a data pad. The method of claim 11, And the first and second upper global input / output line groups and the first and second lower global input / output line groups have the same length. The method of claim 12, The first upper global I / O line group extends from the first block of the Nth upper division bank to the first block of the N + 1 upper division bank, The second upper global I / O line group extends from the second block of the Nth upper division bank to the second block of the N + 1th upper division bank, The first lower global I / O line group extends from the first block of the Nth subdivision bank to the first block of the N + 1th subdivision bank, And the second lower global input / output line group extends from the second block of the Nth subdivision bank to the second block of the N + 1th subdivision bank. Two or more banks and two or more DQ address cells are provided, and each bank is divided into two to form an upper division bank and a lower division bank so as to have an address cell for the same DQ. A semiconductor memory device in which each of the upper and lower division banks is divided into two blocks, and a first block and a second block are allocated. The upper and lower divided banks are arranged so that data input / output in the address cells of the upper divided bank and the lower divided bank can be transferred up and down in the adjacent divided banks. Arranged in a row of data pads for transferring data to external pins between the upper division banks; A T-shaped upper first global input / output line group configured to load data inputted to and output from the first block of each upper division bank and transfer the data to a corresponding data pad, respectively; An upper second global I / O line group having a T-shape for carrying data input and output in the second block of each upper division bank and transferring the data to and from a corresponding data pad, respectively; A T-shaped lower first global I / O line group configured to load data input and output in the first block of each lower division bank and transfer the data to and from the corresponding data pad, respectively; And having a T-shaped lower second global input / output line group configured to load data input and output in the second block of each lower division bank and transfer the data input and output to a corresponding data pad, respectively. Semiconductor memory device.