KR20030001604A - Voltage generator - Google Patents

Abstract

The present invention relates to a voltage generating circuit, wherein in a low external voltage section, a memory cell capacitor which is a reference voltage for generating a reference potential in an intermediate power supply voltage generating circuit and supplying an external voltage having a large current driving capability to determine a signal charge amount When the reference potential used as the voltage has a fast and stable potential, and the reference voltage rises above or above the stable value through the voltage comparison circuit, the external voltage is cut off to supply the reference potential generated in the intermediate power voltage circuit. By applying the intermediate power supply voltage to the chip, it is possible to prevent errors that are recognized as high when the low data written to the charge storage electrode is read after the power is applied. Yield problems caused by voltage problems and The voltage generation circuit can be reduced to a series of test time can reduce the production costs involved are presented to verify.

Description

Voltage generator circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage generating circuit, and in particular, a half supply voltage (half Vcc) generating circuit which is used as a reference voltage for determining a signal charge amount in a semiconductor device or as a precharge voltage of a bit line to set a signal detection standard It is about.

For the special test of the semiconductor memory device, for example, to test the reliability of the gate dielectric film, a voltage corresponding to the middle potential of the power supply voltage (hereinafter, referred to as a half power supply voltage (half Vcc) forcibly) is forcibly applied to the external voltage (Vext). ) Or to a specific potential, such as ground voltage (Vss). To do this, the pass transistor is turned on during normal operation using the pass transistor to cut off the path where the potential generated in the half Vcc circuit is supplied into the chip. Turn off the pass transistor.

1 is a conventional intermediate voltage generation circuit diagram and is configured as follows.

The NAND gate 11 inputs the first control signal S1 and the second control signal S2 inverted by the first inverter I11 and logically combines them. The first NMOS transistor N11 connected between the first node Q11 and the ground terminal Vss is driven according to the output signal of the NAND gate 11. The first PMOS transistor P11 connected between the power supply terminal Vcc and the second node Q12 is driven according to the output signal of the second inverter I12 which inverts the output signal of the NAND gate 11. The second PMOS transistor P12 connected between the power supply terminal Vcc and the third node Q13 is also driven in accordance with the output signal of the second inverter I12. The third PMOS transistor P13 and the second NMOS transistor N12 are connected in series between the power supply terminal Vcc and the second node Q12. The ground voltage Vss is applied to the third PMOS transistor P13. The turn-on state is maintained, and the second NMOS transistor N12 is driven according to the potential of the first node Q11. The fourth PMOS transistor P14 and the third NMOS transistor N13 are connected in series between the second node Q12 and the ground terminal Vss. The fourth PMOS transistor P14 is driven according to the potential of the third node Q13 and inputs the potential of the second node Q12 as a well bias. The third NMOS transistor N13 maintains a turn-on state according to the power supply voltage Vcc. A fourth NMOS transistor N14 driven according to the potential of the first node Q11 is connected between the power supply terminal Vcc and the fourth node Q14, and is connected between the fourth node Q14 and the ground terminal Vss. The fifth PMOS transistor P15 which is driven in accordance with the potential of the third node Q13 is connected to it. Between the fourth node Q14 and the first output terminal Vcp, the first control transistor S3 and the first pass transistor T11 driven according to the signal inverted through the second inverter I12 are Connected. Between the fourth node Q14 and the second output terminal Vblp, the second pass transistor T12 is driven in accordance with the fourth control signal S4 and the signal inverted through the third inverter I13. Connected.

In the above configuration, the first control signal S1 is a signal having a high state when the voltage is higher than a specific voltage after the supply voltage is applied to the chip. Will remain high. Also, the second to fourth control signals S2 to S4 are signals for a special test, and the second control signal S2 is a signal for preventing the intermediate power voltage circuit from operating, and the third control signal S3. Is a signal used to prevent an intermediate supply voltage generated in the intermediate supply voltage circuit from being transferred into the chip. In addition, the first output voltage Vcp output to the first output terminal Vcp is a capacitor voltage of the memory cell used as a reference voltage for determining the amount of signal charge in the chip, and is output to the second output terminal Vblp. The second output voltage Vblp is a precharge voltage of a bit line that sets a reference for signal detection in a chip.

Referring to the driving method of the conventional intermediate voltage generator circuit configured as described above are as follows.

In the normal operation, the first control signal S1 is applied in a high state, and the second to fourth control signals S2 through S4 are applied in a low state. The NAND gate 11 inputs a signal in which the first control signal S1 in a high state and the second control signal S2 in a low state are inverted to a high state through the first inverter I11 to receive a low state signal. Output The first NMOS transistor N11 is turned off by the output signal of the NAND gate 11 output in the low state. In addition, the output signal of the NAND gate 11 output in the low state is inverted to the high state by the second inverter I12, and the first and second PMOS transistors P11 and P12 are turned off by this signal. . The power supply voltage Vcc is supplied to the first node Q11 by the third PMOS transistor P13 to which the ground voltage Vss is applied to maintain the turn-on state, so that the first node Q11 is kept high. . The second NMOS transistor N12 is turned on by the potential of the first node Q11 that maintains the high state, whereby the power supply voltage Vcc is supplied to the second node Q12 so that the second node Q12 Will remain high. The potential of the third node Q13 is turned low by the third NMOS transistor N13 that is supplied with the power supply voltage Vcc to maintain the turn-on state, thereby turning on the fourth PMOS transistor P14. Therefore, the potential lowered by the threshold voltage of the fourth PMOS transistor P14 at the potential of the second node Q12 is supplied to the third node Q13. However, the potential of the third node Q13 is kept low by the turned-on third NMOS transistor N13. Further, the fourth NMOS transistor N14 is turned on by the potential of the first node Q11 that maintains the high state, and the fifth PMOS transistor P15 by the potential of the third node Q13 that maintains the low state. Is turned on. Therefore, the fourth node Q14 maintains the voltage distributed by the fourth NMOS transistor N14 and the fifth PMOS transistor P15. The potential of the fourth node Q14 is output to the first voltage Vcp and the second voltage Vblp through the first and second pass transistors T11 and T12. At this time, the first pass transistor T11 is turned on by the third control signal S3 applied in the low state and the signal inverted through the second inverter I12, and the second pass transistor T12 is turned on. The fourth control signal S4 applied in the low state and the signal is turned on by the signal inverted through the third inverter I13.

On the other hand, when the first voltage Vcp, which is a capacitor voltage of a memory cell used as a reference voltage for determining the amount of signal charge in the chip, is tested, the first control signal S1 is applied in a high state and the second control signal. Since S2 may remain high or low, it is substantially don't care, and the third and fourth control signals S3 and S4 are applied in the high state and the low state, respectively. The NAND gate 11 inputs the first control signal S1 applied in the high state and the second control signal S2 which is the don care to output a low state signal. The first NMOS transistor N11 is turned off by the output signal of the NAND gate 11 output in the low state. In addition, the output signal of the NAND gate 11 output in the low state is inverted to the high state by the second inverter I12, and the first and second PMOS transistors P11 and P12 are turned off by this signal. . The power supply voltage Vcc is supplied to the first node Q11 by the third PMOS transistor P13 to which the ground voltage Vss is applied to maintain the turn-on state, so that the first node Q11 is kept high. . The second NMOS transistor N12 is turned on by the potential of the first node Q11 that maintains the high state, whereby the power supply voltage Vcc is supplied to the second node Q12 so that the second node Q12 Will remain high. The potential of the third node Q13 is turned low by the third NMOS transistor N13 to which the power supply voltage Vcc is applied to maintain the turn-on state, thereby turning on the fourth PMOS transistor P14. Therefore, the potential lowered by the threshold voltage of the fourth PMOS transistor P14 at the potential of the second node Q12 is supplied to the third node Q13. However, since the third NMOS transistor N13 maintains the turn-on and forms a path to the ground terminal Vss, the potential of the third node Q13 remains low. Further, the fourth NMOS transistor N14 is turned on by the potential of the first node Q11 that maintains the high state, and the fifth PMOS transistor P15 by the potential of the third node Q13 that maintains the low state. Is turned on. Therefore, the fourth node Q14 maintains the voltage distributed by the fourth NMOS transistor N14 and the fifth PMOS transistor P15. On the other hand, since the third control signal S3 is applied in the high state, the first pass transistor T11 is turned off, so that the first output voltage Vcp is not output. In addition, the fourth control signal S4 is applied in a low state so that the second pass transistor T12 is turned on to output the second output voltage Vblp. That is, in order to apply the external voltage Vext or the ground voltage Vss to the first output voltage Vcp, the output from the intermediate power supply voltage generation circuit should be prevented.

In addition, in order to test the second output voltage Vblp, which is the precharge voltage of the bit line, which sets the reference for signal detection in the chip during the special test, the first control signal S1 is applied in a high state, and the second control is performed. The signal S2 is substantially don't care because it may remain in a high state or a low state, and the third and fourth control signals S3 and S4 are applied in the low state and the high state, respectively. The NAND gate 11 inputs the first control signal S1 applied in the high state and the second control signal S2 which is the don care to output a low state signal. The first NMOS transistor N11 is turned off by the output signal of the NAND gate 11 output in the low state. In addition, the output signal of the NAND gate 11 output in the low state is inverted to the high state by the second inverter I12, and the first and second PMOS transistors P11 and P12 are turned off by this signal. . The power supply voltage Vcc is supplied to the first node Q11 by the third PMOS transistor P13 to which the ground voltage Vss is applied to maintain the turn-on state, so that the first node Q11 is kept high. . The second NMOS transistor N12 is turned on by the potential of the first node Q11 that maintains the high state, whereby the power supply voltage Vcc is supplied to the second node Q12 so that the second node Q12 Will remain high. The potential of the third node Q13 is turned low by the third NMOS transistor N13 to which the power supply voltage Vcc is applied to maintain the turn-on state, thereby turning on the fourth PMOS transistor P14. Therefore, the potential lowered by the threshold voltage of the fourth PMOS transistor P14 at the potential of the second node Q12 is supplied to the third node Q13. However, since the third NMOS transistor N13 maintains the turn-on and forms a path to the ground terminal Vss, the potential of the third node Q13 remains low. Further, the fourth NMOS transistor N14 is turned on by the potential of the first node Q11 that maintains the high state, and the fifth PMOS transistor P15 by the potential of the third node Q13 that maintains the low state. Is turned on. Therefore, the fourth node Q14 maintains the voltage distributed by the fourth NMOS transistor N14 and the fifth PMOS transistor P15. On the other hand, the third control signal S3 is applied in the low state, the first pass transistor T11 is turned on, and the first output voltage Vcp is output. In addition, the fourth control signal S4 is applied in a high state so that the second pass transistor T12 is turned off so that the second output voltage Vblp is not output. That is, the output from the intermediate power supply voltage generation circuit is prevented to apply the external voltage Vext or the ground voltage Vss to the second output voltage Vblp.

The intermediate voltage generating circuit constructed and driven as described above turns on the first and second pass transistors simultaneously to output the first and second output voltages during normal operation, and the first or second when performing special tests. The pass transistor is selectively turned on to selectively output the first or second output voltage.

However, while the size of the chip increases almost four times with generation in the case of DRAM, the driving capability of a half Vcc circuit is not significantly improved. Therefore, the transient response characteristic that satisfies the time change of the external load is deteriorated. In particular, it takes a long time to charge a stable voltage of the half power supply voltage (half Vcc) to a large load such as when a power supply voltage is applied. do. In normal operation mode, the reference voltage, which determines the amount of signal charge due to the voltage drop that occurs as the power generated from the half Vcc circuit passes through these pass transistors, is written to the chip before the voltage remains stable. A read operation is performed. Therefore, when the written data is in the low state, that is, the ground voltage Vss, it is stored in the low state, that is, the ground voltage Vss, due to the influence of the voltage up conpling effect in the power voltage initialization period. When the data of the charge storage electrode is also read because the potential rises, an error occurs in which the stored data becomes a high state, that is, the external voltage Vext. This phenomenon occurs frequently in the high temperature and low external voltage ranges. This problem occurs because the reference voltage does not maintain a stable voltage. When the test is applied immediately after the power is applied, an error occurs, and when the test is performed after the power is applied in advance, it is confirmed that the test succeeds.

The present invention provides a voltage generating circuit capable of outputting a stable voltage even at high temperature and low external voltage.

Another object of the present invention is to provide a voltage generation circuit for supplying an external voltage having a large current driving force to a large load such as when a power supply voltage is applied to a chip so that the reference voltage for determining the amount of signal charge can have a stable intermediate voltage value. To provide.

It is still another object of the present invention to provide a voltage generation circuit capable of preventing malfunction of a chip.

In order to solve the above-mentioned problems, the present invention generates a reference potential in an intermediate power supply voltage generation circuit in a section where the external voltage is low, and simultaneously supplies an external voltage Vext having a large current drivability. The reference potential used as the memory cell capacitor voltage, which is the reference voltage for determining the signal charge amount, has a fast and stable potential. When the reference voltage rises to a stable value or higher through the voltage comparison circuit, the external voltage Vext is cut off and the reference potential generated in the intermediate power supply voltage circuit is supplied to apply the stable intermediate power supply voltage to the chip. .

1 is a circuit diagram of a conventional intermediate power supply voltage.

2 is an intermediate power supply voltage generation circuit diagram according to the present invention.

3 is a first control circuit diagram for driving an intermediate power supply voltage generating circuit according to the present invention;

4 is an output waveform diagram of a first control circuit.

5 is a second control circuit diagram for driving an intermediate power supply voltage generation circuit according to the present invention;

6 is an output waveform diagram of a second control circuit.

The voltage generation circuit according to the present invention includes a first logic means for logical combination of a first control signal and a second control signal, and a first switching for adjusting a potential of a first node according to an output signal of the first logic means. Means, second switching means for adjusting the potential of the second node in accordance with the inverted signal of the output signal of the first logic means, and adjusting the potential of the third node in accordance with the potential of the first and second nodes. A voltage regulating means for outputting the second logic means for logically combining the third control signal and the sixth control signal, and outputting a potential of the third node according to the output signal of the second logic means and its inverted signal. A first pass transistor for outputting to a terminal, a second pass transistor for outputting a potential of the third node to a second output terminal in accordance with a fourth control signal and an inverted signal thereof, and a fifth control signal It depending characterized in that made in a third switching means for outputting an external voltage to the first output terminal.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

2 is a voltage generation circuit diagram according to the present invention, and is configured as follows.

The NAND gate 21 inputs the first control signal S1 and the second control signal S2 inverted by the first inverter I21 and logically combines them. The first NMOS transistor N21 connected between the first node Q21 and the ground terminal Vss is driven according to the output signal of the NAND gate 21. The first PMOS transistor P21 connected between the power supply terminal Vcc and the second node Q22 is driven in accordance with the output signal of the second inverter I22 which inverts the output signal of the NAND gate 21. The second PMOS transistor P22 connected between the power supply terminal Vcc and the third node Q23 is also driven in accordance with the output signal of the second inverter I22. The third PMOS transistor P23 and the second NMOS transistor N22 are connected in series between the power supply terminal Vcc and the second node Q22. The ground voltage Vss is applied to the third PMOS transistor P23. The turn-on state is maintained, and the second NMOS transistor N22 is driven according to the potential of the first node Q21. The fourth PMOS transistor P24 and the third NMOS transistor N23 are connected in series between the second node Q22 and the ground terminal Vss. Here, the fourth PMOS transistor P24 is driven according to the potential of the third node Q23 and inputs the potential of the second node Q22 as a well bias. The third NMOS transistor N23 maintains a turn-on state by applying a power supply voltage Vcc. A fourth NMOS transistor N24 driven according to the potential of the first node Q21 is connected between the power supply terminal Vcc and the fourth node Q24, and is connected between the fourth node Q24 and the ground terminal Vss. The fifth PMOS transistor P25 which is driven in accordance with the potential of the third node Q23 is connected to it. The first pass transistor T21 is connected between the fourth node Q24 and the first output terminal Vcp, and the first pass transistor T21 is connected to the third control signal S3 and the sixth control signal S6. Is driven according to the output signal of the second inverter I22 which inverts the output signal of the NOR gate 22 which logically combines and the third inverter I23 which inverts the output signal of the second inverter I22. Meanwhile, the sixth PMOS transistor P26 is driven between the external power supply terminal Vext and the first output terminal Vcp according to the fifth control signal S5 and to which the external power supply voltage Vext is applied as a well bias. Connected. The second pass transistor T22 is driven between the fourth node Q44 and the second output terminal Vblp according to the fourth control signal S4 and the signal inverted through the fourth inverter I24. ) Is connected.

In the above configuration, the first control signal S1 is a signal having a high state when a specific voltage is higher than a specific voltage after a power supply voltage is applied to the chip. When the external voltage Vext is 1.5 V or higher, it is determined that power is applied to the chip. Will remain high. Also, the second to fourth control signals S2 to S4 are signals for a special test, and the second control signal S2 is a signal for preventing the intermediate power voltage circuit from operating, and the third control signal S3. Is a signal used to prevent an intermediate supply voltage generated in the intermediate supply voltage circuit from being transferred into the chip. The fifth control signal S5 becomes low when the potential of the first output voltage Vcp is lower than the output voltage of the intermediate power voltage circuit, thereby supplying the external voltage Vext to the first output terminal Vcp. Compensates for the potential of the first output voltage Vcp, and becomes high when the potential of the first output voltage Vcp is higher than the output voltage of the intermediate power supply voltage circuit, thereby making the external voltage Vext to the first output terminal Vcp. Do not allow to be supplied. In addition, the sixth control signal S6 detects that the potential of the first output voltage Vcp is the output voltage of the intermediate power supply voltage circuit by the fifth control signal S5, and then adjusts the voltage generated in the intermediate power supply voltage circuit. Output to the first output terminal (Vcp). The fifth and sixth control signals S5 and S6 are generated by the first control circuit of FIG. 3 which will be described later. Meanwhile, the first output voltage Vcp output to the first output terminal Vcp is a capacitor voltage of a memory cell used as a reference voltage for determining the amount of signal charge in the chip, and is output to the second output terminal Vblp. The second output voltage Vblp is a precharge voltage of a bit line that sets a reference for signal detection in a chip.

Referring to the driving method of the voltage generating circuit according to the present invention configured as described above are as follows.

In the normal operation, the first control signal S1 is applied in a high state, and the second to fourth control signals S2 through S4 are applied in a low state. The fifth and sixth control signals S5 and S6 are applied in a high state and a low state, respectively. The NAND gate 21 inputs a signal in which the first control signal S1 in a high state and the second control signal S2 in a low state are inverted to a high state through the first inverter I21 to receive a low state signal. Output The first NMOS transistor N21 is turned off by the output signal of the NAND gate 21 output in the low state. In addition, the output signal of the NAND gate 21 output in the low state is inverted to the high state by the second inverter I22, and the first and second PMOS transistors P21 and P22 are turned off by this signal. . The power supply voltage Vcc is supplied to the first node Q21 by the third PMOS transistor P23 to which the ground voltage Vss is applied to maintain the turn-on state, thereby maintaining the high state of the first node Q21. . The second NMOS transistor N22 is turned on by the potential of the first node Q21 that maintains the high state, whereby the power supply voltage Vcc is supplied to the second node Q22 so that the second node Q22 Will remain high. The potential of the third node Q23 is turned low by the third NMOS transistor N23 that is supplied with the power supply voltage Vcc to maintain the turn-on state, thereby turning on the fourth PMOS transistor P24. Therefore, the potential lowered by the threshold voltage of the fourth PMOS transistor P24 at the potential of the second node Q22 is supplied to the third node Q23. However, the potential of the third node Q23 is kept low by the turned-on third NMOS transistor N23. In addition, the fourth NMOS transistor N24 is turned on by the potential of the first node Q21 that maintains the high state, and the fifth PMOS transistor P25 by the potential of the third node Q23 that maintains the low state. Is turned on. Accordingly, the fourth node Q24 maintains the voltage distributed by the fourth NMOS transistor N24 and the fifth PMOS transistor P25. The potential of the fourth node Q24 is output to the first output voltage Vcp and the second output voltage Vblp through the first and second pass transistors T21 and T22. At this time, the first pass transistor T21 receives the third control signal S3 applied in the low state and the sixth control signal S6 applied in the low state to the NOR gate 22 to output a high state signal. The signal is turned on by the signal inverted to the low state through the second inverter I42 and the signal inverted through the third inverter I23. The second pass transistor T22 is turned on by the fourth control signal S4 applied in the low state and the signal inverted through the fourth inverter I24. Meanwhile, the sixth PMOS transistor P26 is turned off by the fifth control signal S5 input in the high state, so that the external voltage Vext is not input to the first output terminal Vcp.

On the other hand, when the first voltage Vcp, which is a capacitor voltage of a memory cell used as a reference voltage for determining the amount of signal charge in the chip, is tested, the first control signal S1 is applied in a high state and the second control signal. Since S2 may remain high or low, it is substantially don't care, and the third and fourth control signals S3 and S4 are applied in the high state and the low state, respectively. The fifth control signal S5 is applied in a high state, and the sixth control signal S6 is applied in a doncare because it maintains a high or low state. The NAND gate 21 inputs the first control signal S1 applied in the high state and the second control signal S2 which is the don care to output a low state signal. The first NMOS transistor N21 is turned off by the output signal of the NAND gate 21 output in the low state. In addition, the output signal of the NAND gate 21 output in the low state is inverted to the high state by the second inverter I22, and the first and second PMOS transistors P21 and P22 are turned off by this signal. . The power supply voltage Vcc is supplied to the first node Q21 by the third PMOS transistor P23 to which the ground voltage Vss is applied to maintain the turn-on state, thereby maintaining the high state of the first node Q21. . The second NMOS transistor N22 is turned on by the potential of the first node Q21 that maintains the high state, whereby the power supply voltage Vcc is supplied to the second node Q22 so that the second node Q22 Will remain high. The potential of the third node Q23 is turned low by the third NMOS transistor N23 that is supplied with the power supply voltage Vcc to maintain the turn-on state, thereby turning on the fourth PMOS transistor P24. Therefore, the potential lowered by the threshold voltage of the fourth PMOS transistor P24 at the potential of the second node Q22 is supplied to the third node Q23. However, since the third NMOS transistor N23 maintains the turn-on state and forms a path to the ground terminal Vss, the potential of the third node Q23 maintains the low state. In addition, the fourth NMOS transistor N24 is turned on by the potential of the first node Q21 that maintains the high state, and the fifth PMOS transistor P25 by the potential of the third node Q23 that maintains the low state. Is turned on. Accordingly, the fourth node Q24 maintains the voltage distributed by the fourth NMOS transistor N24 and the fifth PMOS transistor P25. The third control signal S3 in the high state and the sixth control signal S6 in the don care are input to the NOR gate 22, and the NOR gate 22 logically combines them to output a low state signal. The output signal of the NOR gate 22 output in the low state is inverted to the high state through the second inverter I22, and the first pass is generated by this signal and the signal inverted by the third inverter I23. Transistor T21 is turned on. Therefore, the potential of the fourth node Q24 is not output to the first output voltage Vcp. At this time, since the fifth control signal S5 is applied in a high state to turn off the sixth PMOS transistor P26, the external voltage Vext is not applied to the first output terminal Vcp. In addition, the fourth control signal S4 is applied in a low state so that the second pass transistor T22 is turned on to output the second output voltage Vblp. That is, in order to apply the external voltage Vext or the ground voltage Vss to the first output voltage Vcp, the output from the intermediate power supply voltage generation circuit should be prevented.

In addition, in order to test the second output voltage Vblp, which is the precharge voltage of the bit line, which sets the reference for signal detection in the chip during the special test, the first control signal S1 is applied in a high state, and the second control is performed. The signal S2 is substantially don't care because it may remain in a high state or a low state, and the third and fourth control signals S3 and S4 are applied in the low state and the high state, respectively. In addition, the output of the fifth control signal S5 is adjusted according to the potential of the first output voltage Vcp, and the sixth control signal S6 is applied in a low state. The NAND gate 21 inputs the first control signal S1 applied in the high state and the second control signal S2 which is the don care to output a low state signal. The first NMOS transistor N21 is turned off by the output signal of the NAND gate 21 output in the low state. In addition, the output signal of the NAND gate 21 output in the low state is inverted to the high state by the second inverter I22, and the first and second PMOS transistors P21 and P22 are turned off by this signal. . The power supply voltage Vcc is supplied to the first node Q21 by the third PMOS transistor P23 to which the ground voltage Vss is applied to maintain the turn-on state, thereby maintaining the high state of the first node Q21. . The second NMOS transistor N22 is turned on by the potential of the first node Q21 that maintains the high state, whereby the power supply voltage Vcc is supplied to the second node Q22 so that the second node Q22 Will remain high. The potential of the third node Q23 is turned low by the third NMOS transistor N23 that is supplied with the power supply voltage Vcc to maintain the turn-on state, thereby turning on the fourth PMOS transistor P24. Therefore, the potential lowered by the threshold voltage of the fourth PMOS transistor P24 at the potential of the second node Q22 is supplied to the third node Q23. However, since the third NMOS transistor N23 maintains the turn-on state and forms a path to the ground terminal Vss, the potential of the third node Q23 maintains the low state. In addition, the fourth NMOS transistor N24 is turned on by the potential of the first node Q21 that maintains the high state, and the fifth PMOS transistor P25 by the potential of the third node Q23 that maintains the low state. Is turned on. Accordingly, the fourth node Q24 maintains the voltage distributed by the fourth NMOS transistor N24 and the fifth PMOS transistor P25. The NOR gate 22, which has received the third control signal S3 in the low state and the sixth control signal S6 in the low state, outputs a high state signal, and the signal is low through the second inverter I22. The state is reversed. The first pass transistor T21 is turned on by the output signal of the second inverter I22 in the low state and the signal in which the signal is inverted to the high state through the third inverter I23. Therefore, the potential of the fourth node Q42 is output at the first output voltage Vcp. However, when the first output voltage Vcp is lower than the set reference voltage, the fifth control signal S5 in the low state is output by the second control signal of FIG. 5. Therefore, the external voltage Vext is applied to the first output terminal Vcp, and the external voltage Vext is output as the first output voltage Vcp. On the other hand, when the first output voltage Vcp is higher than the set reference voltage, the fifth control signal S5 is input in a high state, and thus the external voltage Vext is not input. In addition, the fourth control signal S4 is applied in a high state so that the second pass transistor T22 is turned off so that the second output voltage Vblp is not output. That is, the output from the intermediate power supply voltage generation circuit is prevented to apply the external voltage Vext or the ground voltage Vss to the second output voltage Vblp.

3 is a first control circuit diagram for generating first and seventh control signals for driving a voltage generating circuit according to the present invention, and is configured as follows.

First to fourth resistors R31 to R34 are connected in series between the external power supply terminal Vext and the ground terminal Vss. A first NMOS transistor N31 driven according to the potential of the first node Q31 is connected between the external power supply terminal Vext and the gate terminal of the second NMOS transistor N32. The potential of the first node Q31 is determined according to the resistance ratio of the first to fourth resistors R31 to R34 and the second to fourth resistors R32 to R34. The first PMOS transistor P31 is connected between the external power supply terminal Vext and the second node Q32 to maintain a turn-on state. A second NMOS transistor N32 driven according to an external voltage Vext applied through the first NMOS transistor N31 is connected between the second node Q32 and the ground terminal Vss. The potential of the second node Q32 is inverted and delayed through the first to third inverters I31 to I33 and output as the seventh control signal S7. A third NMOS transistor N33 driven according to the potential of the third node Q33 is connected between the external power supply terminal Vext and the gate terminal of the fourth NMOS transistor N34. The potential of the third node Q33 is determined according to the resistance ratios of the first to fourth resistors R31 to R34 and the third and fourth resistors R33 and R34. The second PMOS transistor P32 is connected between the external power supply terminal Vext and the fourth node Q34 to maintain a turn-on state. A fourth NMOS transistor N34 driven according to an external voltage Vext applied through the third NMOS transistor N33 is connected between the fourth node Q34 and the ground terminal Vss. The potential of the fourth node Q34 is inverted and delayed through the fourth to sixth inverters I34 to I36 and output as the first control signal S1. Meanwhile, the potential of the fifth node Q35 is determined by the ratio of the first to fourth resistors R31 to R34 and the fourth resistor R34.

The driving method of the first control circuit for generating the first and seventh control signals for driving the voltage generating circuit according to the present invention configured as described above will be described using a graph showing the potential of each node shown in FIG. Is as follows.

When the external voltage Vext rises, the potential of the first node Q31 also rises to a value lower than the external voltage Vext. When the potential of the first node Q31 rises to turn on the first NMOS transistor N31, an external voltage Vext is applied thereto. When the second NMOS transistor N32 is completely turned on by the external voltage Vext applied through the first NMOS transistor N31, the external voltage supplied to the second node Q32 through the first PMOS transistor P31. Vext is passed to the ground terminal Vss. Accordingly, the second node Q32 maintains the potential of the low state. The potential of the second node Q32 maintaining the low state is inverted to a high state through the first to third inverters I31 to I33 and output as the seventh control signal S7. On the other hand, when the external voltage Vext rises, the potential of the third node Q33 also rises to a value lower than the potential of the external voltage Vext and the first node Q31. When the potential of the third node Q33 rises to turn on the third NMOS transistor N33, an external voltage Vext is applied thereto. When the fourth NMOS transistor N34 is completely turned on by the external voltage Vext applied through the third NMOS transistor N33, the external voltage supplied to the fourth node Q34 through the second PMOS transistor P32. Vext is passed to the ground terminal Vss. Therefore, the fourth node Q34 maintains the potential of the low state. The potential of the fourth node Q34 maintaining the low state is inverted to a high state through the fourth to sixth inverters I34 to I36 and output as the first control signal S1. That is, after a predetermined time after the seventh control signal S7 is output in the high state, the first control signal S1 is output in the high state.

5 is a circuit diagram of a second control circuit for generating fifth and sixth control signals for driving a voltage generating circuit according to the present invention, and is configured as follows.

The voltage comparison circuit 41 connected between the external power supply terminal Vext and the ground terminal Vss is driven according to the potential of the third node Q43 to compare the first output voltage Vcp with the reference voltage Vref. The result is output to the second node Q42. The inverting means composed of the fifth PMOS transistor P45 and the fifth NMOS transistor N45 connected between the external power supply terminal Vext and the ground terminal Vss inverts the potential of the second node Q42 so that The potential of the node Q43 is determined. The fourth NMOS transistor N44 connected between the third node Q43 and the ground terminal Vss is driven according to the seventh control signal S7 delayed inverted through the first to third inverters I41 to I43. . The sixth PMOS transistor P46 connected between the external power supply terminal Vext and the second node Q42 is driven according to the potential of the third node Q43. Eighth and ninth NMOS transistors N48 and N49 are connected in series between the second node Q42 and the ground terminal Vss. The eighth NMOS transistor N48 is driven according to the seventh control signal S7 inverted and delayed through the first to fifth inverters I41 to I45, and the ninth NMOS transistor N49 is driven by the first and second inverters It is driven according to the seventh control signal S7 delayed through I41 and I42. The seventh PMOS transistor P47 connected between the external power supply terminal Vext and the output terminal of the fifth control signal S5 is driven according to the potential of the third node Q43. The sixth and seventh NMOS transistors N46 and N47 are connected in series between the fifth control signal S5 output terminal and the ground terminal Vss. The sixth NMOS transistor N46 is turned on by applying a power supply voltage Vcc, and the seventh NMOS transistor N47 is driven according to the potential of the third node Q43. The first NAND gate 42 includes a seventh control signal S7 delayed through the first and second inverters I41 and I42 and a seventh control signal S7 delayed through the first to sixth inverters I41 to I46. Enter a logical combination. The third NAND gate 43 outputs the eighth inverter I48 that inverts the output signal of the seventh inverter I47 that inverts the potential of the second node Q42 and the output signal of the first NAND gate 42. A signal is input and logically combined to output the sixth control signal S6.

A driving method of the second control circuit for generating the fifth and sixth control signals for driving the voltage generation circuit according to the present invention configured as described above will be described below with reference to FIG. 6.

When the seventh control signal S7 is applied to the high state, it is delayed through the first and second inverters I41 and I42 to turn on the ninth NMOS transistor N49 and is input to one end of the first NAND gate 42. do. On the other hand, the seventh control signal S7 input in the high state is input to the other end of the first NAND gate 42 after a predetermined time delay through the first to sixth inverters I41 to I46. In this process, the seventh control signal S7 is inverted to a low state through the first to third inverters I41 to I43 to turn off the fourth NMOS transistor N44, and the first to fifth inverters I41. To I45 to invert the delay to turn off the eighth NMOS transistor N48. However, the period where the output signal of the second inverter I42 and the output signal of the fifth inverter I45 meet in the high state, that is, the seventh control signal S7 is applied in the high state, The potential of the second node Q42, which is the output signal of the voltage comparison circuit 41, is initialized to the low state in the pulse period of the delay time until the output signal reaches the transition from the high state to the low state. The potential of the second node Q42 output in the low state turns off the fifth NMOS transistor P45, turns on the fifth PMOS transistor P45, and supplies an external voltage Vext to the third node Q43. Therefore, the third node Q42 goes high. The seventh PMOS transistor P47 is turned off by the potential of the third node Q43 in the high state, and the seventh NMOS transistor N47 is turned on. Therefore, the fifth control signal S5 is output in the low state. On the other hand, the first NAND gate 42 which inputs the output signal of the second inverter I42 and the output signal of the sixth inverter I46 which are input in the high state, logically combines them and outputs the low state signal. The output signal of the first NAND gate 42 output in the low state is inverted to the high state through the eighth inverter I48 and input to one end of the second NAND gate 43. The third node Q43 maintains a high state in a short period in which the second node Q42 maintains a low state. The potential of the third node Q43 maintaining the high state is inverted to the low state through the seventh inverter I47 and input to the other end of the second NAND gate 43. The second NAND gate 43 which inputs the output signal of the seventh inverter I47 in the low state and the output signal of the eighth inverter I48 in the high state, logically combines them and outputs a signal in the high state. This signal becomes the sixth control signal S6.

Meanwhile, the voltage comparison circuit 41 compares the first output voltage Vcp and the reference voltage Vref, and when the first output voltage Vcp is greater than the reference voltage Vref, the second node Q42 is in a high state. This potential is output as the fifth control signal S5 in the high state. However, when the first output voltage Vcp is smaller than the reference voltage Vref, the second node Q42 goes low, and this potential is output as the fifth control signal S5 in the low state. That is, the fifth control signal S5 is output in a low state when the initialization and the first output voltage Vcp are lower than the reference voltage Vref, and when the first output voltage Vcp is greater than the reference voltage Vref. Outputs high.

When the first output voltage Vcp is greater than the reference voltage Vref, the second node Q42 is in a high state and the third node Q43 is in a low state. The potential of the third node Q43 in the low state is inverted to the high state through the seventh inverter I47 and input to one end of the second NAND gate 43. The other end of the second NAND gate 43 receives the output signal of the eighth inverter I38 in the high state. The second NAND gate 43 logically combines two signals in a high state to output a low state signal. This signal acts as the sixth control signal S6. In addition, the sixth control signal S6 is output in a high state after a predetermined delay time when the seventh control signal S7 is input in a high state, and a predetermined delay is output when the seventh control signal S7 is output in a low state. Outputs low after time.

As described above, according to the present invention, the current driveability is large with respect to a large external load, such as a case where a high temperature and a low external voltage, in which a voltage drop is greatest, is applied and a power is applied to the chip. By supplying an external voltage so that the first output voltage can have a stable intermediate power supply voltage, it is possible to prevent an error that is recognized as a high state when the low state data written to the charge storage electrode is read after the power is applied. During the test at the level and package level, there is a problem with the intermediate supply voltage, resulting in a reduction in yield and the series of test times involved to verify it, thereby reducing production costs.

Claims (20)

First logic means for logic combining the first control signal and the second control signal, First switching means for adjusting the potential of the first node according to the output signal of the first logic means; Second switching means for adjusting the potential of the second node according to the inverted signal of the output signal of the first logic means; Voltage adjusting means for adjusting the potential of the third node according to the potential of the first and second nodes; Second logic means for logic combining the third control signal and the sixth control signal, A first pass transistor for outputting a potential of the third node to a first output terminal in accordance with an output signal of the second logic means and an inverted signal thereof; A second pass transistor for outputting a potential of the third node to a second output terminal in accordance with a fourth control signal and an inverted signal thereof; And third switching means for outputting an external voltage to the first output terminal according to the fifth control signal. 2. The voltage generating circuit as claimed in claim 1, wherein said first logic means is a NAND gate. 2. The voltage generating circuit according to claim 1, wherein said first switching means is an NMOS transistor connected between a power supply terminal and a ground terminal. 2. The voltage generating circuit as claimed in claim 1, wherein said second switching means is a PMOS transistor connected between a power supply terminal and said second node. 2. The NMOS transistor according to claim 1, wherein the voltage regulating means comprises: an NMOS transistor connected between a power supply terminal and the third node and driven according to a potential of the first node; And a PMOS transistor connected between the third node and a ground terminal and driven according to the potential of the second node. 2. The voltage generator circuit as claimed in claim 1, wherein said second logic means is an OR gate. 2. The voltage generating circuit according to claim 1, wherein said third switching means is a PMOS transistor connected between an external power supply terminal and said first output terminal. The voltage generating circuit according to claim 1, wherein the fifth control signal is generated by a voltage comparing circuit comparing the potential of the first output terminal with a reference voltage. The method of claim 1 or 8, wherein the fifth control signal is output in a high state when the potential of the first output terminal is higher than the reference voltage, and when the potential of the first output terminal is lower than the reference voltage. Voltage generation circuit characterized in that the output in the low state. The sixth control signal of claim 1, wherein the sixth control signal comprises: a first delay signal for delaying the seventh control signal for a first time and a second delay signal for delaying the seventh control signal for a second time; 1 logic means, And a second logic means for inputting and logically combining a signal having the same phase as the inverted signal of the first logic means and the fifth control signal. 11. The voltage generating circuit according to claim 10, wherein said first logic means is a first NAND gate. 11. The voltage generating circuit according to claim 10, wherein said second logic means is a second NAND gate. 11. The apparatus of claim 10, wherein the seventh control signal comprises: voltage distribution means for distributing the external voltage to a predetermined potential; First switching means for driving the output of the voltage distribution means to supply the external voltage; And a voltage generating circuit which is driven according to the external voltage input through the first switching means and output by a voltage adjusting means for regulating the external voltage to a predetermined potential. The voltage generation circuit according to claim 13, wherein said voltage distribution means is comprised of a plurality of resistors connected between said external power supply terminal and a ground terminal. The voltage generating circuit as claimed in claim 13, wherein said first switching means is an NMOS transistor. The PMOS transistor of claim 13, wherein the voltage adjusting means comprises: a PMOS transistor connected between the external power supply terminal and the seventh control signal output terminal and driven by a ground voltage; And an NMOS transistor connected between the seventh control signal output terminal and the ground terminal and driven by the external voltage input through the first switching means. 2. The apparatus of claim 1, wherein the first control signal comprises: voltage distribution means for distributing the external voltage to a predetermined potential; First switching means for driving the output of the voltage distribution means to supply the external voltage; And a voltage generating circuit which is driven according to the external voltage input through the first switching means and output by a voltage adjusting means for regulating the external voltage to a predetermined potential. 18. The voltage generator circuit as claimed in claim 17, wherein said voltage distribution means comprises a plurality of resistors connected between said external power supply terminal and a ground terminal. 18. The voltage generator circuit as claimed in claim 17, wherein said first switching means is an NMOS transistor. 18. The apparatus of claim 17, wherein the voltage adjusting means comprises: a PMOS transistor connected between the external power supply terminal and the seventh control signal output terminal and driven by a ground voltage; And an NMOS transistor connected between the seventh control signal output terminal and the ground terminal and driven by the external voltage input through the first switching means.