KR200216619Y1 - Semiconductor package - Google Patents
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- Publication number
- KR200216619Y1 KR200216619Y1 KR2019970031721U KR19970031721U KR200216619Y1 KR 200216619 Y1 KR200216619 Y1 KR 200216619Y1 KR 2019970031721 U KR2019970031721 U KR 2019970031721U KR 19970031721 U KR19970031721 U KR 19970031721U KR 200216619 Y1 KR200216619 Y1 KR 200216619Y1
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- South Korea
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- semiconductor chip
- semiconductor package
- heat dissipation
- semiconductor
- wire
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
복수개의 리이드부; 상기 리이드부와 와이어에 의해서 와이어 본딩되는 반도체 칩; 및 상기 반도체 칩의 일부가 노출되도록 상기 반도체 칩상에 부착되는 방열부재;를 포함하는 반도체 패키지에 관한 것으로서, 반도체 칩의 아랫면에 방열부재을 설치하고, 이 방열부재사이에 반도체 칩의 일부를 외부로 노출시킴으로써 반도체 칩으로부터 발생하는 열을 용이하게 방출시킬 수 있다.A plurality of lead portions; A semiconductor chip wire-bonded by the lead portion and a wire; And a heat dissipation member attached to the semiconductor chip so that a portion of the semiconductor chip is exposed. A heat dissipation member is provided on a bottom surface of the semiconductor chip, and a portion of the semiconductor chip is exposed to the outside between the heat dissipation members. By doing so, heat generated from the semiconductor chip can be easily released.
Description
본 고안은 반도체 패키지에 관한 것으로서, 더 상세하게는 방열층의 구조가 개선된 반도체 패키지에 관한 것이다.The present invention relates to a semiconductor package, and more particularly, to a semiconductor package having an improved structure of a heat dissipation layer.
통상적으로 반도체 패키지는 반도체 리이드프레임이 스탬핑 공정 또는 에칭 공정을 통하여 제조된 다음에 기억 소자인 반도체 칩등과 같은 다른 부품과의 조립 과정을 거쳐서 구성된다.Typically, a semiconductor package is constructed by fabricating a semiconductor leadframe through a stamping process or an etching process and then assembling it with other components such as a semiconductor chip, which is a storage element.
최근에는 반도체 칩의 박형화 및 소형화 추세에 따라 리이드 프레임도 소형화되고 있는 추세이다. 반도체 칩이 고집적화, 고밀도화됨에 따라, 집적 회로의 소비 전력이 증가하게 된다. 이에 따라, 반도체 패키지는 우수한 방열성이 요구된다.Recently, the lead frame has also been miniaturized in accordance with the trend toward thinner and smaller semiconductor chips. As semiconductor chips become more integrated and denser, power consumption of integrated circuits increases. Accordingly, the semiconductor package requires excellent heat dissipation.
도 1은 이러한 반도체 패키지(10)의 일 예를 나타낸 것이다.1 illustrates an example of such a semiconductor package 10.
도면을 참조하면, 상기 반도체 패키지(10)에는 반도체 칩(11)이 마련된다. 상기 반도체 칩(11)의 각 단자는 와이어(12)를 이용하여 리이드부(13)와 각각 와이어 본딩된다. 상기 반도체 칩(11)과 리이드부(12)의 아랫면은 접착제(14)에 의하여 방열부재(15)가 부착된다. 그리고, 상기 리이드부(13)의 상하면에는 봉지재(16)가 봉지되어 와이어 본딩부를 외부로부터 보호하게 된다.Referring to the drawing, the semiconductor package 10 is provided with a semiconductor chip 11. Each terminal of the semiconductor chip 11 is wire-bonded with the lead portion 13 using the wire 12. The heat dissipation member 15 is attached to the lower surface of the semiconductor chip 11 and the lead portion 12 by an adhesive 14. The encapsulant 16 is encapsulated on the upper and lower surfaces of the lead portion 13 to protect the wire bonding portion from the outside.
이와 같이 완성된 반도체 패키지(10)는 외부 단자의 전기적 신호가 리이드부(13)에 의해 상기 반도체 칩(11)으로 전달되고, 반면에 상기 반도체 칩(11)으로부터 나온 전기적 신호는 상기 리이드부(13)를 통하여 외부 단자에 전해진다.In the semiconductor package 10 completed as described above, an electrical signal of an external terminal is transmitted to the semiconductor chip 11 by the lead portion 13, while an electrical signal from the semiconductor chip 11 is transferred to the lead portion ( It is transmitted to the external terminal through 13).
여기에서, 상기 반도체 패키지(10)에 전원이 인가되면, 고집적화된 반도체 칩(11)에는 많은 양의 열이 발생한다. 이러한 열은 금속 소재로 제조되는 상기 방열부재(15)에 의하여 외부로 방출시키게 된다.Here, when power is applied to the semiconductor package 10, a large amount of heat is generated in the highly integrated semiconductor chip 11. This heat is released to the outside by the heat radiation member 15 made of a metal material.
그런데, 상기 방열부재(15)만으로는 반도체 칩(11)으로부터 발생되는 열을 완전히 방출시키는 것이 불가능하다. 따라서, 상기 반도체 칩(11)은 장시간 이용시 열적 변화를 받게 되고, 가열 및 냉각 과정에서 내부 응력이 발생하게 된다. 이러한 내부 응력으로 인하여 상기 반도체 칩(11) 상에는 크랙이 발생하게 되고, 이 크랙을 통하여 수분등이 침투함으로써 작동 불량의 원인이 된다.However, it is impossible to completely discharge the heat generated from the semiconductor chip 11 with only the heat dissipation member 15. Therefore, the semiconductor chip 11 is subjected to a thermal change when it is used for a long time, and internal stress is generated during the heating and cooling process. Due to such internal stress, cracks are generated on the semiconductor chip 11, and moisture and the like penetrate through the cracks, thereby causing malfunction.
본 고안은 상기와 같은 문제점을 해결하기 위하여 창안된 것으로서, 반도체 칩으로부터 발생하는 열을 효과적으로 방출시킬 수 있는 반도체 패키지를 제공하는데 그 목적이 있다.The present invention was devised to solve the above problems, and an object thereof is to provide a semiconductor package capable of effectively releasing heat generated from a semiconductor chip.
도 1은 종래의 반도체 패키지를 도시한 단면도이고,1 is a cross-sectional view showing a conventional semiconductor package,
도 2는 본 고안에 따른 반도체 패키지를 도시한 단면도이다.2 is a cross-sectional view showing a semiconductor package according to the present invention.
〈도면의 주요 부분에 대한 부호의 간단한 설명〉<Brief description of symbols for the main parts of the drawings>
10,20. 반도체 패키지10,20. Semiconductor package
11,21. 반도체 칩11,21. Semiconductor chip
12,22. 와이어12,22. wire
13,23. 리이드부13,23. Lead part
14,24. 접착제14,24. glue
15,25. 방열부재15,25. Heat dissipation member
25a. 개구부25a. Opening
16,26. 봉지재16,26. Encapsulant
27. 수지층27. Resin Layer
상기와 같은 목적을 달성하기 위하여 본 고안의 반도체 패키지는, 복수개의 리이드부; 상기 리이드부와 와이어에 의해서 와이어 본딩되는 반도체 칩; 및 상기 반도체 칩의 일부가 노출되도록 상기 반도체 칩상에 부착되는 방열부재;를 포함한다.In order to achieve the above object, the semiconductor package of the present invention includes a plurality of lead portions; A semiconductor chip wire-bonded by the lead portion and a wire; And a heat dissipation member attached to the semiconductor chip so that a portion of the semiconductor chip is exposed.
본 고안은 상기 노출된 반도체 칩의 표면에 소정 두께의 수지층이 형성되는 것을 특징으로 한다.The present invention is characterized in that a resin layer having a predetermined thickness is formed on the exposed surface of the semiconductor chip.
본 고안은 상기 수지층의 열팽창계수가 상기 반도체 칩의 열팽창계수와 동일한 것을 특징으로 한다.The present invention is characterized in that the thermal expansion coefficient of the resin layer is the same as the thermal expansion coefficient of the semiconductor chip.
본 고안의 다른 특징에 따르면, 상기 방열부재는 상기 반도체 칩의 노출되는 부위와 대응되는 개구부를 가지는 것이 바람직하다.According to another feature of the present invention, the heat radiating member preferably has an opening corresponding to the exposed portion of the semiconductor chip.
이하에서 첨부된 도면을 참조하면서 본 고안에 따른 반도체 패키지의 바람직한 일 실시예를 상세히 설명하고자 한다.Hereinafter, a preferred embodiment of a semiconductor package according to the present invention will be described in detail with reference to the accompanying drawings.
도 2는 본 고안에 따른 반도체 패키지(20)를 나타낸 것이다.2 shows a semiconductor package 20 according to the present invention.
도면을 참조하면, 상기 반도체 패키지(20)에는 반도체 칩(21)이 마련된다. 상기 반도체 칩(21)의 기억 소자는 리이드부(23)와 접속되는데, 이것은 와이어(22)를 통한 와이어본딩으로 가능하다.Referring to the drawing, the semiconductor package 20 is provided with a semiconductor chip 21. The memory element of the semiconductor chip 21 is connected with the lead portion 23, which is possible by wire bonding through the wire 22.
상기 반도체 칩(21)과 리이드부(23)의 단부에는 방열부재(25)가 접착제(24)에 의하여 부착되어 있다. 이때, 상기 반도체 칩(21)은 아랫면의 일부가 노출되도록 그 가장자리를 따라서 상기 방열부재(25)가 부착된다. 그리고, 상기 방열부재(25)는 상기 반도체 칩(21)의 노출되는 부분과 대응되는 부위에 개구부(25a)가 형성된다.The heat dissipation member 25 is attached to the ends of the semiconductor chip 21 and the lead portion 23 by the adhesive agent 24. In this case, the heat dissipation member 25 is attached along the edge of the semiconductor chip 21 to expose a portion of the bottom surface thereof. The heat radiating member 25 has an opening 25a formed at a portion corresponding to the exposed portion of the semiconductor chip 21.
상기 개구부(25a)를 통하여 노출된 상기 반도체 칩(21)상에는 이것을 외부로부터 보호하기 위하여 수지층(27)이 얇게 도포된다. 상기 수지층(27)은 고분자 수지로서, 상기 반도체 칩(27)의 열팽창계수와 동일한 값을 가진다.On the semiconductor chip 21 exposed through the opening 25a, a resin layer 27 is applied thinly to protect it from the outside. The resin layer 27 is a polymer resin and has the same value as the thermal expansion coefficient of the semiconductor chip 27.
한편, 상기 리이드부(23)의 상하면에는 몰딩재(26)를 이용하여 몰딩하게 된다. 상기 리이드부(23)의 윗면에 봉지되는 몰딩재(26)는 와이어 본딩부를 외부로부터 보호하게 된다. 또한, 상기 리이드부(23)의 아랫면에 몰딩되는 몰딩재(26)는 상기 수지층(27)이 형성된 반도체 칩(27)상에는 몰딩되지 않는다.On the other hand, the upper and lower surfaces of the lead portion 23 is molded using a molding material 26. The molding material 26 encapsulated on the upper surface of the lead portion 23 protects the wire bonding portion from the outside. In addition, the molding material 26 molded on the lower surface of the lead portion 23 is not molded on the semiconductor chip 27 on which the resin layer 27 is formed.
상기와 같이 구성된 본 고안에 따른 반도체 패키지(20)는 상기 리이드부(23)를 통하여 외부 단자의 전기적 신호가 상기 반도체 칩(21)으로 전달되고, 이와 반대로 상기 반도체 칩(21)으로부터 나온 전기적 신호는 다시 외부 단자에 전해진다.In the semiconductor package 20 according to the present invention configured as described above, an electrical signal of an external terminal is transmitted to the semiconductor chip 21 through the lead portion 23, and conversely, an electrical signal from the semiconductor chip 21. Is passed back to the external terminal.
이때, 상기 반도체 칩(21)에서는 고밀도화, 고집적화로 인한 많은 열이 발생하게 되고, 이 열은 상기 반도체 칩(21)의 아랫면에 부착된 방열부재(25)를 통하여 방출하게 된다. 이것은 상기 방열부재(25)가 열 전도성이 우수한 금속재로 제조되어서 가능하다. 그리고, 상기 방열부재(25)의 개구부(25a)를 통하여 상기 반도체 칩(21)의 아랫면 일부가 외부로 노출되므로 외부의 공기가 유입되어 열을 효과적으로 냉각시킬 수 있다.At this time, the semiconductor chip 21 generates a large amount of heat due to high density and high integration, and the heat is emitted through the heat dissipation member 25 attached to the lower surface of the semiconductor chip 21. This is possible because the heat dissipation member 25 is made of a metal material having excellent thermal conductivity. In addition, since a portion of the lower surface of the semiconductor chip 21 is exposed to the outside through the opening 25a of the heat radiating member 25, outside air may be introduced to effectively cool the heat.
이상의 설명에서와 같이 본 고안의 반도체 패키지는 반도체 칩의 아랫면에 방열부재을 설치하고, 이 방열부재사이에 반도체 칩의 일부를 외부로 노출시킴으로써 반도체 칩으로부터 발생하는 열을 용이하게 방출시킬 수 있다.As described above, in the semiconductor package of the present invention, a heat dissipation member is disposed on a lower surface of the semiconductor chip, and the heat generated from the semiconductor chip can be easily released by exposing a portion of the semiconductor chip to the outside between the heat dissipation members.
본 고안은 도면에 도시된 일 실시예를 참고로 설명되었으나 이는 예시적인 것에 불과하며, 본 기술 분야의 통상의 지식을 가진 자라면 이로부터 다양한 변형 및 균등한 타 실시예가 가능하다는 점을 이해할 것이다. 따라서, 본 고안의 진정한 기술적 보호 범위는 첨부된 등록청구범위의 기술적 사상에 의해 정해져야 할 것이다.Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention should be defined by the technical spirit of the appended claims.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019970031721U KR200216619Y1 (en) | 1997-11-11 | 1997-11-11 | Semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019970031721U KR200216619Y1 (en) | 1997-11-11 | 1997-11-11 | Semiconductor package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19990018490U KR19990018490U (en) | 1999-06-05 |
| KR200216619Y1 true KR200216619Y1 (en) | 2001-04-02 |
Family
ID=53897108
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR2019970031721U Expired - Fee Related KR200216619Y1 (en) | 1997-11-11 | 1997-11-11 | Semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR200216619Y1 (en) |
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1997
- 1997-11-11 KR KR2019970031721U patent/KR200216619Y1/en not_active Expired - Fee Related
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| Publication number | Publication date |
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| KR19990018490U (en) | 1999-06-05 |
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