KR20020065730A - Lead frame for fabricating semiconductor package - Google Patents
Lead frame for fabricating semiconductor package Download PDFInfo
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- KR20020065730A KR20020065730A KR1020010005903A KR20010005903A KR20020065730A KR 20020065730 A KR20020065730 A KR 20020065730A KR 1020010005903 A KR1020010005903 A KR 1020010005903A KR 20010005903 A KR20010005903 A KR 20010005903A KR 20020065730 A KR20020065730 A KR 20020065730A
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- lead frame
- lead
- die pad
- package
- semiconductor package
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48095—Kinked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
본 발명은 반도체 패키지 제조용 리드프레임에 관한 것으로서, 리드프레임의 구조를 개선을 통해 다이 어태치 및 몰딩 공정 진행시 다이패드와 다이 어태치 에폭시와의 결합력 및, 리드와 몰딩콤파운드와의 결합력이 증대되도록 하여 패키지의 신뢰성이 향상되도록 한 것이다.The present invention relates to a lead frame for manufacturing a semiconductor package, and improves the structure of the lead frame to increase the bonding force between the die pad and the die attach epoxy and the bonding force between the lead and the molding compound during the die attach and molding process. This is to improve the reliability of the package.
이를 위해, 본 발명은 반도체칩(5)이 부착되는 다이패드(4)와, 상기 다이패드(4) 주위에 배치되는 리드(7)를 구비한 리드프레임(1)에 있어서; 상기 리드프레임(1)의 다이패드(4) 상면과 리드(7)의 상면에 복수개의 요입홈(100)을 형성한 것을 특징으로 하는 반도체 패키지 제조용 리드프레임이 제공된다.To this end, the present invention relates to a lead frame (1) having a die pad (4) to which a semiconductor chip (5) is attached and a lead (7) arranged around the die pad (4); A lead frame for manufacturing a semiconductor package is provided, wherein a plurality of recessed grooves 100 are formed on an upper surface of the die pad 4 and an upper surface of the lead 7 of the lead frame 1.
Description
본 발명은 반도체 패키지 제조용 리드프레임에 관한 것으로서, 더욱 상세하게는 다이 어태치 및 몰딩 공정 진행시 다이패드와 다이 어태치 에폭시와의 결합력 및, 리드와 몰딩콤파운드와의 결합력이 증대되도록 리드프레임의 구조를 개선한 것이다.The present invention relates to a lead frame for manufacturing a semiconductor package, and more particularly, to a structure of a lead frame such that the bonding force between the die pad and the die attach epoxy and the bonding force between the lead and the molding compound are increased during the die attach and molding process. Will be improved.
일반적으로, 반도체 산업에서 집적회로에 대한 패키징 기술은 소형화에 대한 요구 및 실장 신뢰성을 만족시키기 위해 지금까지 계속 발전해오고 있다.In general, the packaging technology for integrated circuits in the semiconductor industry continues to evolve to meet the demand for miniaturization and mounting reliability.
즉, 소형화에 대한 요구는 칩 스케일에 근접한 패키지에 대한 개발을 가속화시키고 있으며, 실장 신뢰성에 대한 요구는 실장작업의 효율성 및 실장후의 기계적·전기적 신뢰성을 향상시킬 수 있는 패키지 제조 기술에 대한 중요성을 부각시키고 있다.In other words, the demand for miniaturization is accelerating the development of packages close to the chip scale, and the demand for mounting reliability emphasizes the importance of package manufacturing technology that can improve the efficiency of mounting work and the mechanical and electrical reliability after mounting. I'm making it.
한편, 일반적으로 반도체소자는 집적회로가 형성된 웨이퍼 상태에서 낱개의 칩으로 각각 분리된 후, 이것을 플라스틱 패키지나 세라믹 패키지에 탑재하여 기판에의 실장이 용이하도록 조립하는 패키징 공정을 거치게 된다.On the other hand, in general, semiconductor devices are separated into individual chips in a wafer in which integrated circuits are formed, and then mounted in a plastic package or a ceramic package, and then subjected to a packaging process for assembling the substrate to facilitate mounting on the substrate.
이와 같이 행해지는 반도체소자에 대한 패키징 공정의 주목적은 기판이나 소켓에 실장하기 위한 형상의 확보와 기능보호에 있다고 할 수 있다.The main purpose of the packaging step for the semiconductor element thus performed is to secure the shape and protect the function for mounting on the substrate or the socket.
또한, 최근에는 집적회로의 고집적화에 따라 다핀화, 미세조립기술, 또 실장형태의 다양화에 따른 패키지의 다종류화 등, 조립공정과 관련된 기술도 각각 세분된 분야에 따라 크게 변화하고 있다.In addition, in recent years, technologies related to the assembly process, such as multi-pinning, micro-assembly technology, and package variety due to the diversification of the mounting type according to the high integration of integrated circuits, are also greatly changed according to the subdivided fields.
반도체 조립공정의 개요에 대해 현재 가장 많이 사용되고 있는 플라스틱 타입의 반도체소자를 예로 들어 설명하면 다음과 같다.An overview of the semiconductor assembly process will be described below with an example of a plastic type semiconductor device which is most used.
먼저, 전기적 회로가 형성된 웨이퍼를 각각의 단일 칩으로 분리하는데, 이때Si(실리콘)는 모스경도 7로서 딱딱하고 깨지기 쉬운 성질을 갖고 있으므로 웨이퍼의 제조시 미리 분리할 라인에 절단하기 위한 물질을 넣어두고 이 분리라인을 따라 브레이크 응력을 가해 파괴, 분리시키는 방법을 취하는 경우가 많다.First, the wafer on which the electrical circuit is formed is separated into each single chip.Si (silicon) has a Mohs hardness of 7, which is hard and brittle, so that a material for cutting is placed in a line to be separated in advance in manufacturing the wafer. In many cases, a break stress is applied along this separation line to break and separate.
또한, 분리된 각각의 반도체 칩은 도 1에 도시된 바와 같은 리드프레임의 다이패드에 본딩되고, 이때의 접합방법은 Au-Si 공정(共晶)법, 납땜법, 수지접착법 등이 있으며 용도에 따라 알맞은 방법이 선택되어 사용된다.In addition, each of the separated semiconductor chips is bonded to the die pad of the lead frame as shown in FIG. 1, and the bonding method includes Au-Si process, soldering, resin bonding, and the like. The appropriate method is selected and used accordingly.
한편, 전술한 바와 같이 반도체 칩을 리드프레임의 다이패드에 접착하는 목적은 조립이 완료된 후 기판에 실장시키기 위해서 뿐만 아니라, 전기적 입출력단자나 어스(earth)를 겸하는 일도 있으며 소자의 동작시 발생하는 열의 방열통로로서도 필요로 하는 경우가 있기 때문이다.On the other hand, as described above, the purpose of bonding the semiconductor chip to the die pad of the lead frame is not only to be mounted on the substrate after assembly is completed, but also to serve as an electrical input / output terminal or earth, This is because the heat dissipation path may be required.
상기와 같이 반도체 칩을 본딩한 후에는 칩의 본딩패드와 리드프레임의 인너리드를 와이어로 본딩하므로써 연결하게 되며, 와이어 본딩의 방법으로 플라스틱 봉함 패키지에서는 일반적으로 골드 와이어를 사용한 열압착법 또는 열압착법과 초음파법을 혼용한 방법이 주로 이용되고 있다.After bonding the semiconductor chip as described above, the bonding pad of the chip and the inner lead of the lead frame are connected by wire bonding. In the plastic sealing package, the thermal bonding method or the thermocompression bonding using gold wire is generally performed. The method which mixed the method and the ultrasonic method is mainly used.
또한, 와이어 본딩에 의해 반도체 칩과 인너리드가 전기적으로 연결된 후에는 칩을 고순도의 에폭시 수지를 사용하여 성형 봉합하므로써 몰드바디를 형성시키는 몰딩공정이 수행되는데, 이때 사용되는 에폭시 수지는 집적회로의 신뢰성을 좌우하는 중요한 요소이며, 수지의 고순도화와 몰딩시 집적회로에 주어지는 응력을 저감시키기 위한 저응력화 등의 개선이 추진되고 있다.In addition, after the semiconductor chip and the inner lead are electrically connected by wire bonding, a molding process of forming a mold body by forming and sealing the chip using a high purity epoxy resin is performed. In addition, the improvement of the high purity of the resin and the reduction of the stress for reducing the stress applied to the integrated circuit during molding are being promoted.
그리고, 상기한 공정이 완료된 후에는 IC 패키지를 소켓이나 기판에 실장하기 위해 아웃터리드(outer lead)를 소정의 형상으로 절단하고 성형하는 공정이 행해지며, 아웃터리드에는 실장접합성(납땜성)을 향상시키기 위해 도금이나 납딥(dip)이 처리된다.After the above process is completed, a process of cutting and molding an outer lead into a predetermined shape is carried out to mount the IC package on a socket or a substrate, and the mount is improved in solderability. Plating or dip dips are applied to make them.
한편, 반도체 패키지는 실장형태 및 리드형태에 따라 여러 가지 유형으로 나뉘는데, 리드프레임을 이용한 패키지의 대표적인 예로서는 전술한 DIP(Dual Inline Package)외에 QFP(Quad Flat Package), TSOP(Thin Small Outline Package)등이 있다.On the other hand, semiconductor packages are divided into various types according to the mounting type and lead type. As a representative example of a package using a lead frame, QFP (Quad Flat Package), TSOP (Thin Small Outline Package), etc. in addition to the above-described Dual Inline Package (DIP) There is this.
그러나, 이와 같은 패키지에 적용되는 종래의 리드프레임은 다이패드 및 리드에 기계적인 처리가 되어 있지 않고, Ag나 Ni/Pd등을 플레이팅하는 방법으로 다이 어태치 에폭시나 몰딩콤파운드(8)와의 결합력을 높이도록 되어 있다.However, the conventional lead frame applied to such a package does not have a mechanical treatment on the die pad and the lead, and bonds with the die attach epoxy or the molding compound 8 by plating Ag, Ni / Pd, or the like. It is supposed to raise.
그러나, 이러한 Ag나 Ni/Pd등을 플레이팅 만으로는 다이 어태치 에폭시나 몰딩콤파운드(8)와 리드프레임간의 결합력을 충분히 확보할 수 없는 문제점이 있었다.However, there is a problem that the bonding force between the die attach epoxy or the molding compound 8 and the lead frame cannot be sufficiently secured by plating only Ag or Ni / Pd.
본 발명은 상기한 제반 문제점을 해결하기 위한 것으로서, 기계적인 처리를 통해 다이 어태치 공정 및 몰딩공정에 있어 다이패드와 다이 어태치 에폭시와의 결합력 및, 리드와 몰딩콤파운드와의 결합력이 증대되도록 한 반도체 패키지 제조용 리드프레임을 제공하는데 그 목적이 있다.The present invention is to solve the above-mentioned problems, the mechanical treatment to increase the bonding strength of the die pad and die attach epoxy in the die attach process and molding process, and the bonding force between the lead and the molding compound It is an object of the present invention to provide a lead frame for manufacturing a semiconductor package.
도 1은 종래 리드프레임의 기술요부를 나타낸 평면도1 is a plan view showing the main technical parts of the conventional lead frame
도 2는 본 발명에 따른 리드프레임의 기술요부를 나타낸 평면도Figure 2 is a plan view showing the main part of the lead frame according to the present invention
도 3은 본 발명에 따른 리드프레임을 이용한 패키지 제조과정중 다이 어태치 및 와이어 본딩이 완료된 상태를 나타낸 요부 단면도3 is a cross-sectional view illustrating main parts of a die attach and wire bonding completed during a package manufacturing process using a lead frame according to the present invention.
도 4는 본 발명에 따른 리드프레임을 이용한 패키지 제조과정중 몰딩이 완료된 상태를 나타낸 요부단면도Figure 4 is a main cross-sectional view showing a state in which the molding is completed during the package manufacturing process using the lead frame according to the present invention.
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
1:리드프레임100:요입홈1: lead frame 100: recessed groove
3:와이어4:다이패드3: wire 4: die pad
5:반도체칩6:에폭시5: semiconductor chip 6: epoxy
7:리드8:몰딩콤파운드7: Lead 8: Molding Compound
상기한 목적을 달성하기 위해, 본 발명은 반도체칩이 부착되는 다이패드와, 상기 다이패드 주위에 배치되는 리드를 구비한 리드프레임에 있어서; 상기 리드프레임의 다이패드 상면과 리드의 상면에 복수개의 요입홈을 형성한 것을 특징으로 하는 반도체 패키지 제조용 리드프레임이 제공된다.In order to achieve the above object, the present invention provides a lead frame having a die pad to which a semiconductor chip is attached and a lead disposed around the die pad; Provided is a lead frame for manufacturing a semiconductor package, wherein a plurality of recessed grooves are formed on an upper surface of a die pad and a lead of the lead frame.
이하, 본 발명의 실시예를 도 2 내지 도 4를 참조하여 상세히 설명하면 다음과 같다.Hereinafter, an embodiment of the present invention will be described in detail with reference to FIGS. 2 to 4.
도 2는 본 발명에 따른 리드프레임의 기술요부를 나타낸 평면도로서, 본 발명은 반도체칩(5)이 부착되는 다이패드(4)와, 상기 다이패드(4) 주위에 배치되는 리드(7)를 구비한 리드프레임(1)에 있어서; 상기 리드프레임(1)의 다이패드(4) 상면과 리드(7)의 상면에 복수개의 요입홈(100)을 형성한 것이다.FIG. 2 is a plan view showing the main elements of the lead frame according to the present invention. The present invention relates to a die pad 4 to which a semiconductor chip 5 is attached, and a lead 7 disposed around the die pad 4. In the lead frame (1) provided; A plurality of recessed grooves 100 are formed on an upper surface of the die pad 4 and an upper surface of the lead 7 of the lead frame 1.
이 때, 상기 요입홈(100)은 딤플(dimple) 형태를 띠며, 다이패드(4) 또는 리드(7)의 면상에 소정 행렬을 이루도록 메트릭스(matrix) 타입으로 형성된다.In this case, the concave groove 100 has a dimple shape and is formed in a matrix type so as to form a predetermined matrix on the surface of the die pad 4 or the lid 7.
한편, 상기 요입홈(100)은 리드(7)의 와이어(3) 본딩영역을 벗어난 영역에 존재하게 된다.On the other hand, the recessed groove 100 is present in a region outside the bonding area of the wire 3 of the lead (7).
이와 같이 구성된 본 발명의 작용은 다음과 같다.The operation of the present invention configured as described above is as follows.
본 발명에서는 다이패드(4) 및 리드(7) 상에 Ag나 Ni/Pd등을 플레이팅하는 외에 추가적으로 기계가공에 의해 형성되는 요입홈(100)이 구비된다.In the present invention, in addition to plating Ag, Ni / Pd, etc. on the die pad 4 and the lead 7 is provided with a recess groove 100 is formed by additional machining.
이에 따라, 본 발명은 도 3에 나타낸 바와 같이, 반도체칩(5)을 다이패드(4)에 부착하는 다이 어태치 공정시 에폭시(6)와 다이패드(4)와의 접촉면적을 증대시켜 상호간의 결합력을 증대시킬 수 있다.Accordingly, the present invention increases the contact area between the epoxy 6 and the die pad 4 during the die attach process of attaching the semiconductor chip 5 to the die pad 4, as shown in FIG. 3. The bonding force can be increased.
또한, 도 4에 나타낸 바와 같이, 몰딩공정시에는 리드(7)와 몰딩콤파운드(8)와의 접촉면적을 증대시키므로써, 리드(7)와 몰딩콤파운드(8) 상호간의 결합력을증대시킬 수 있게 된다.In addition, as shown in FIG. 4, during the molding process, the contact area between the lid 7 and the molding compound 8 is increased, so that the bonding force between the lid 7 and the molding compound 8 can be increased. .
한편, 본 발명은 리드프레임(1)의 다이패드(4)와 에폭시(6) 및 리드(7)와 몰딩콤파운드(8)와의 접촉면적 증대를 통해 상호간의 결합력이 증대됨과 더불어, 요입홈(100)으로 인해 크랙의 전파가 효과적으로 차단되어 패키지의 신뢰성을 높일 수 있게 된다.Meanwhile, the present invention increases the contact area between the die pad 4, the epoxy 6, the lead 7, and the molding compound 8 of the lead frame 1, and increases the mutual coupling force and the concave groove 100. This effectively blocks the propagation of the cracks, increasing the reliability of the package.
이상에서와 같이, 본 발명은 리드프레임의 구조 개선을 통해 리드프레임과 에폭시 또는 몰딩콤파운드와의 접촉면적을 증대시킨 것이다.As described above, the present invention is to increase the contact area of the lead frame and the epoxy or molding compound through the structural improvement of the lead frame.
이에 따라, 본 발명은 리드프레임과 에폭시 또는 몰딩콤파운드와의 결합력이 증대되므로써 크랙의 전파가 방지되며, 패키지의 신뢰성 테스트시 크랙이 발생하더라도 요입홈에 의해 크랙의 전파가 차단되므로써 패키지의 신뢰성을 높이는 효과를 가져오게 된다.Accordingly, the present invention prevents the propagation of cracks by increasing the bonding force between the lead frame and epoxy or molding compound, and increases the reliability of the package by blocking the propagation of the cracks by the recessed grooves even if a crack occurs during the reliability test of the package. Will have an effect.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020010005903A KR20020065730A (en) | 2001-02-07 | 2001-02-07 | Lead frame for fabricating semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020010005903A KR20020065730A (en) | 2001-02-07 | 2001-02-07 | Lead frame for fabricating semiconductor package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20020065730A true KR20020065730A (en) | 2002-08-14 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020010005903A Ceased KR20020065730A (en) | 2001-02-07 | 2001-02-07 | Lead frame for fabricating semiconductor package |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117119682A (en) * | 2022-05-17 | 2023-11-24 | 荣耀终端有限公司 | Circuit board assembly, electronic equipment and manufacturing method of circuit board assembly |
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2001
- 2001-02-07 KR KR1020010005903A patent/KR20020065730A/en not_active Ceased
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117119682A (en) * | 2022-05-17 | 2023-11-24 | 荣耀终端有限公司 | Circuit board assembly, electronic equipment and manufacturing method of circuit board assembly |
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