KR20020064022A - thin film transistor array panel for liquid crystal display and manufacturing method thereof - Google Patents

Abstract

A gate wiring including a gate line, a gate electrode, and a gate pad is formed on the insulating substrate, and a gate insulating film is formed thereon. Next, an amorphous silicon layer and a doped amorphous silicon layer are deposited and a photosensitive film pattern having a different thickness depending on the position is formed. Using the photoresist pattern as a mask, an amorphous silicon layer, a doped amorphous silicon layer, and a gate insulating film are etched to form a semiconductor layer and an ohmic contact layer, and a contact hole exposing a gate line is formed. Next, an auxiliary gate line connected to the gate line is formed through the contact hole and the data line including the data line, the source electrode, the drain electrode, and the data pad. Next, a protective film is formed and a pixel electrode is formed. Here, the auxiliary data line may be formed at a position overlapping with the data line when the gate line is formed, and contact holes may be formed to expose the auxiliary data line when the semiconductor layer and the ohmic contact layer are formed to be connected to the data line formed thereon. . As described above, an auxiliary line overlapping at least one of the gate line and the data line may be formed to prevent a defect due to disconnection.

Description

Thin film transistor substrate for liquid crystal display device and manufacturing method therefor {thin film transistor array panel for liquid crystal display and manufacturing method}

The present invention relates to a thin film transistor substrate for a liquid crystal display device and a manufacturing method thereof, and more particularly, to a thin film transistor substrate for a liquid crystal display device having a double wiring and a manufacturing method thereof.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two glass substrates on which electrodes are formed and a liquid crystal layer interposed therebetween. A display device for controlling the amount of light transmitted by rearranging them.

A substrate of a liquid crystal display generally has a thin film transistor for switching a voltage applied to an electrode. The thin film transistor substrate includes, in addition to the thin film transistor, a gate line and a gate pad that receives a signal from the outside and transfers the signal to the gate line. A data line including a gate line, a data line, and a data pad for receiving a signal from the outside and transferring the signal to the data line is formed.

In general, the wiring is formed using a metal having a low resistance. In the case of forming a single film, if a wiring break occurs during the process, there is a problem in that the production yield is reduced.

The technical problem to be achieved by the present invention is to prevent the disconnection of the wiring.

1 is a layout view illustrating a thin film transistor substrate for a liquid crystal display according to a first embodiment of the present invention.

2 is a cross-sectional view taken along the line II-II in FIG.

3A is a layout view showing a thin film transistor substrate in a first step of manufacturing according to the first embodiment of the present invention;

FIG. 3B is a cross sectional view taken along line IIIb-IIIb in FIG. 3A;

4A is a cross-sectional view at the next stage of FIG. 3B;

4B and 4C are cross-sectional views sequentially showing the processes in the next step of FIG. 4A in the order thereof;

FIG. 5A is a layout view at the next step of FIG. 4C;

FIG. 5B is a cross sectional view taken along the line Vb-Vb in FIG. 5A;

FIG. 6a is a layout view in the next step of FIG. 5a;

FIG. 6B is a cross sectional view taken along the line VIb-VIb in FIG. 6A;

FIG. 7a is a layout view in the next step of FIG.

FIG. 7B is a cross sectional view taken along the line VIIb-VIIb in FIG. 7A;

8 is a layout view illustrating a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention.

9 is a cross-sectional view taken along line VII-VII in FIG. 8,

10A is a layout view showing a thin film transistor substrate in a first step of manufacturing according to the second embodiment of the present invention;

FIG. 10B is a cross-sectional view taken along the line VIIb-VIIb in FIG. 10A;

FIG. 11A is a sectional view at the next step of FIG. 10B,

11B and 11C are sectional views showing the process in the next step of FIG. 11A in the order thereof;

12A is a layout view at the next step of FIG. 11C;

FIG. 12B is a cross sectional view taken along the line b-? B in FIG. 12A;

FIG. 13A is a layout view in the next step of FIG. 12A;

FIG. 13B is a cross sectional view taken along line XIIIb-XIIIb in FIG. 13A;

FIG. 14a is a layout view in the next step of FIG. 13a;

FIG. 14B is a cross-sectional view taken along line XIVb-XIVb in FIG. 14A.

In order to achieve this problem, the present invention forms a double wiring connected through a contact hole drilled in the gate insulating film.

According to the present invention, a gate line is formed on an insulating substrate, the gate line is covered with an insulating film, and a data line is formed on the insulating film. An auxiliary data line formed of the same layer as the gate line and connected to the data line through a first contact hole formed in the insulating film, and an auxiliary data line formed of the same layer as the data line and connected to the gate line through a second contact hole formed in the insulating film At least one of the gate lines is located.

In such a thin film transistor substrate for liquid crystal display devices, a gate wiring including a gate line and a gate electrode is formed on an insulating substrate, and the gate insulating film covers the gate wiring. A semiconductor layer is formed in an island shape on the gate electrode, and a data line including a data line, a source electrode, and a drain electrode is formed on the semiconductor layer and the gate insulating film. The protective film covers the data wiring, and the pixel electrode is formed on the protective film. An auxiliary data line formed of the same layer as the gate line and connected to the data line through a first contact hole formed in the gate insulating film, and connected to the gate line through a second contact hole formed of the same layer as the data line and formed through the gate insulating film At least one of the auxiliary gate lines may be located.

Here, the auxiliary data line overlaps the data line, and the auxiliary gate line preferably overlaps the gate line.

Meanwhile, an ohmic contact layer may be further formed between the semiconductor layer and the data line.

In order to manufacture such a thin film transistor substrate for a liquid crystal display, first, a gate wiring including a gate line and a gate electrode is formed on an insulating substrate. Next, the gate insulating film and the amorphous silicon layer are sequentially deposited, and at least one or more contact holes are formed in the gate insulating film by using a photosensitive film pattern having a different thickness depending on the position, and a semiconductor layer made of amorphous silicon is formed. Next, a data line including a data line, a source electrode and a drain electrode is formed, and a protective film and a pixel electrode are formed in this order.

Here, it is preferable to form an auxiliary gate line overlapping the gate line when forming the data line, the contact hole exposes the gate line, and connect the gate line and the auxiliary gate line through the contact hole.

On the other hand, when forming the gate wiring, an auxiliary data line overlapping the data line is formed, the contact hole exposes the auxiliary data line, and the data line and the auxiliary data line may be connected through the contact hole.

And forming an auxiliary data line overlapping with the data line when forming the gate wiring, and forming an auxiliary gate line overlapping with the gate line when forming the data wiring, wherein the contact hole exposes the gate line and the auxiliary data line, respectively, The gate line and the auxiliary gate line may be connected to each other, and the data line and the auxiliary data line may be connected to each other.

In this case, the photoresist pattern includes a first portion having a first thickness, a second portion thicker than the first thickness, and a third portion having no thickness and excluding the first and second portions, and including the first region and the first region. It is formed using an optical mask comprising a second region having a low transmittance and a third region having a higher transmittance than the first region, wherein the first, second and third regions of the mask are formed of the first, second and third portions of the photoresist pattern. It is preferable to arrange so as to correspond to each of the third portions. In the photoresist pattern, the third portion is preferably formed so that the contact hole is to be formed, the second portion is located above the semiconductor layer, and the third portion is positioned at a portion other than the first and second portions. In order to control the transmittance of the first to third regions differently, a slit pattern smaller than the resolution of the transflective film or the exposure machine may be formed in the photomask.

Meanwhile, an ohmic contact layer may be further formed between the semiconductor layer and the data line, and the semiconductor layer, the ohmic contact layer, and the contact hole may be formed in one photo process.

In the present invention, when forming the ohmic layer and the ohmic contact layer through a single photo process, a contact hole connected to the gate line or the data line is formed, and an auxiliary gate line and an auxiliary data line overlapping the gate line or the data line are formed to disconnect the line. Can reduce the occurrence of

Next, a thin film transistor substrate for a liquid crystal display device and a method for manufacturing the same according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the same. do.

First, a structure of a thin film transistor substrate for a liquid crystal display according to a first embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

FIG. 1 is a layout view illustrating a thin film transistor substrate for a liquid crystal display according to a first exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the line II-II of FIG. 1.

1 and 2, on the insulating substrate 10, aluminum (Al) or aluminum alloy (Al alloy), molybdenum (Mo) or molybdenum-tungsten alloy (MoW), chromium (Cr), tantalum (Ta) and the like Gate wirings 21, 22, and 23 made of a metal or a conductor are formed. The gate wiring is connected to the gate line 21 extending in the horizontal direction, the gate electrode 22 that is part of the gate line 21, and the end of the gate line 21, and receives a scan signal from the outside to the gate line 21. A gate pad 23.

The gate wirings 21, 22, and 23 may be formed in a single layer, but may be formed in a double layer or a triple layer. In the case of forming more than two layers, it is preferable that one layer is made of a material having a low resistance and the other layer is made of a material having good contact properties with other materials. For example, a double layer of Cr / Al (or an Al alloy) or Al / A bilayer of Mo can be mentioned.

A gate insulating layer 30 made of silicon nitride (SiN _X ) is formed on the gate lines 21, 22, and 23.

A semiconductor layer 41 made of a semiconductor such as amorphous silicon is formed on the gate insulating layer 30, and an semiconductor such as amorphous silicon doped with n-type impurities such as phosphorus (P) is formed on the semiconductor layer 41. Resistive contact layers 52 and 53 are formed on both sides of the gate electrode 22.

On the ohmic contact layers 52 and 53, data wirings 61, 62, 63, 64 and auxiliary gate lines 65 made of a metal or a conductor such as aluminum or an aluminum alloy, molybdenum or molybdenum-tungsten alloy, chromium, tantalum, or the like are provided. Formed. The data line includes a data line 61 extending in the vertical direction, a source electrode 62 which is a part of the data line 61, a drain electrode 63 facing the source electrode 62 around the gate electrode 22, and data. And a data pad 64 connected to the line 61 to receive an image signal from the outside and transmit the image signal to the data line 61. The auxiliary gate line 65 is formed in the same layer as the data lines 61, 62, 63, and 64 by being separated for each pixel area, and the gate line 21 is formed through the contact hole 31 formed in the insulating film 30. Connected with

The data wirings 61, 62, 63, and 64 can be formed in a single layer similarly to the gate wirings 21, 22, and 23, but can also be formed in a double layer or a triple layer. In the case of forming more than two layers, it is preferable that one layer is formed of a material having a low resistance and the other layer is formed of a material having good contact properties with other materials.

A protective film 70 made of silicon nitride or an organic insulating film is formed on the data lines 61, 62, 63, and 64 and the gate insulating film 30. The passivation layer 70 has not only a contact hole 73 exposing the gate pad 23 with the gate insulating film 30, but also a contact hole 74 and a drain electrode 63 exposing the data pad 64. It has a contact hole 72.

The pixel electrode 80, the auxiliary gate pad 83, and the auxiliary data pad 84 made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) are formed on the passivation layer 70.

The pixel electrode 80 is connected to the drain electrode 63 through the contact hole 72 to receive an image signal. The auxiliary gate pad 83 and the auxiliary data pad 84 are connected to the gate pad 23 and the data pad 64 through the contact holes 73 and 74, respectively, which are the pads 23 and 64 and the external circuit. It serves to complement the adhesion with the device and to protect the pads 23 and 64.

As described above, in the thin film transistor substrate according to the first exemplary embodiment of the present invention, the auxiliary gate line 65 connected to the gate line 21 through the contact hole 31 is formed on the gate line 21. The disconnection failure of 21 can be prevented, and the production yield can be improved.

Next, a method of manufacturing a thin film transistor substrate for a liquid crystal display according to a first exemplary embodiment of the present invention will be described with reference to FIGS. 3A to 7B and FIGS. 1 and 2.

First, as shown in FIGS. 3A and 3B, a gate wiring conductor or a metal is deposited on the insulating substrate 10 to a thickness of 1,000 Å to 3,000 으로 by sputtering, and patterned by a photolithography process using a mask. A gate wiring including 21, the gate electrode 22, and the gate pad 23 is formed.

Next, as shown in FIGS. 4A and 4B, the gate insulating film 30, the amorphous silicon layer, and the amorphous silicon layer doped with n-type impurities are respectively 1,500 kV to 5,000 kV, 500 kV to 1,500 kV using chemical vapor deposition. After the deposition in order of a thickness of 300 kPa to 600 kPa, a photosensitive film is applied. Next, the photosensitive film is irradiated with light using a mask 100 having a different transmittance depending on the location and then developed to form photosensitive film patterns 112 and 114 having different thicknesses depending on the location. At this time, the first portion 112 of the photoresist patterns 112 and 114 located at the portion A in which the island-shaped ohmic contact layer 51 and the semiconductor layer 41 below is formed is the remaining region (other than the photoresist pattern 112 and 114). It is thicker than the second portion 114 located at C), and the photosensitive film of the portion B on the gate line 21 is removed.

As such, there may be various methods of varying the thickness of the photoresist layer according to the position. In order to control the light transmittance in the C region, a slit or lattice-shaped pattern is mainly formed or a semi-transmissive layer is used.

In this case, the line width of the pattern located between the slits, or the interval between the patterns, that is, the width of the slits, is preferably smaller than the resolution of the exposure machine used for exposure. In the case of using a semi-transmissive film, a different transmittance is used to control the transmittance when fabricating a mask. A thin film having a thickness or a thin film may be used.

Here, the second portion 114 of the photoresist layer is exposed to light using a photoresist layer made of a reflowable material, and is exposed using a conventional mask that is divided into a portion that can completely transmit light and a portion that can not completely transmit light. And a portion of the photoresist film flows down to a portion where the photoresist film does not remain.

Next, etching is performed on the photoresist pattern 114 and the films below, the doped amorphous silicon layer 50, the amorphous silicon layer 40, and the gate insulating layer 30.

First, as shown in FIG. 4B, the contact hole 31 exposing the gate line 21 by removing the exposed doped amorphous silicon layer 50, the amorphous silicon layer 40, and the gate insulating layer 30 of the portion B is exposed. To form. In this process, the photoresist patterns 112 and 114 are preferably performed under conditions that are hardly etched.

Next, as shown in FIG. 4C, the photoresist layer pattern is ashed to remove the C photoresist pattern 114 to expose the doped amorphous silicon layer 50. At this time, since the photoresist pattern 112 of the portion A is also etched, the thickness becomes thin, so that the photoresist pattern 112 is removed so that the doped amorphous silicon layer 50 of the portion A is not exposed. Next, the doped amorphous silicon layer 50 and the amorphous silicon layer 40 of the C portion are removed.

Next, when the photoresist pattern 112 remaining in the portion A is removed, as shown in FIGS. 5A and 5B, an island-shaped ohmic contact layer 51 and a semiconductor layer 41 below the gate electrode 22 are formed. Is formed.

Next, as shown in FIGS. 6A and 6B, a conductor or a metal for data wiring is deposited to a thickness of 1,500 mV to 3,000 mV by a sputtering method, and patterned by a photolithography process using a mask to form a data line 61 and a source electrode. The data line and the auxiliary gate line 65 including the 62, the drain electrode 63, and the data pad 64 are formed. In this case, the auxiliary gate line 65 is separated for each pixel area and formed on the gate line 21, and is connected to the gate line 21 through the contact hole 31. Next, the ohmic contact layer 51 not covered by the source electrode 62 and the drain electrode 63 is removed to separate the two portions 52 and 53.

Next, as shown in FIGS. 7A and 7B, silicon nitride is deposited using a chemical vapor deposition method, or spin coating an organic insulating layer to form a protective film 70 having a thickness of 3,000 kPa or more, and patterned by a photolithography process using a mask. To form contact holes 72, 73, and 74.

Next, as shown in FIG. 1 and FIG. 2, a transparent conductive material such as ITO or IZO is deposited to a thickness of 400 kV to 500 kV by a sputtering method, and patterned by a photolithography process using a mask to form the pixel electrode 80. The auxiliary gate pad 83 and the auxiliary data pad 84 are formed.

In the first embodiment of the present invention, the auxiliary gate line 65 is formed on the gate line 21 to form a double wiring, but the auxiliary data line may be formed on the data line 61. This will be described as a second embodiment of the present invention with reference to FIGS. 8 to 14A.

First, a structure of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention will be described with reference to FIGS. 8 and 9.

FIG. 8 is a layout view illustrating a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention, and FIG. 9 is a cross-sectional view taken along line VII-VII of FIG. 8.

8 and 9, in the structure of the thin film transistor substrate according to the second exemplary embodiment of the present invention, an auxiliary gate line is not formed on the gate line 21, and an auxiliary data line is formed below the data line 61. Except for forming (25), it has the same structure as in the first embodiment of the present invention.

Next, a method of manufacturing a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention will be described with reference to FIGS. 10A to 14B and FIGS. 8 and 9.

First, as shown in FIGS. 10A and 10B, a gate wiring conductor or a metal is deposited on the insulating substrate 10 and patterned by a photolithography process using a mask to form a gate line 21, a gate electrode 22, and a gate pad ( A gate wiring including the 23 and the auxiliary data line 25 are formed. Here, the auxiliary data line 25 is formed at a position overlapping with the data line 61 to be formed later.

Next, as shown in FIG. 11A, the gate insulating film 30, the amorphous silicon layer, and the amorphous silicon layer doped with n-type impurities are sequentially deposited, and then a photosensitive film is coated. Next, the photosensitive film is irradiated with light using a mask 200 having a different transmittance depending on the location, and then developed to form photosensitive film patterns 212 and 214 having different thicknesses depending on the location. At this time, the third portion 212 positioned in the portion D of the photoresist patterns 212 and 214 where the island-shaped ohmic contact layer 51 and the semiconductor layer 41 below is formed is the third portion 212. The thickness is thicker than the fourth portion 214 positioned in the region F except for the photoresist, and the photoresist of the portion E above the auxiliary data line 25 is removed.

Next, etching is performed on the photoresist pattern 214 and the underlying layers, the doped amorphous silicon layer 50, the amorphous silicon layer 40, and the gate insulating layer 30.

First, as shown in FIG. 11B, the contact hole 32 exposing the auxiliary data line 25 by removing the exposed doped amorphous silicon layer 50, the amorphous silicon layer 40, and the gate insulating layer 30 of the E portion. ). In this process, the photoresist patterns 212 and 214 may be preferably performed under conditions that are hardly etched.

Next, as shown in FIG. 11C, the photoresist pattern is ashed to remove the photoresist pattern 214 of the F portion to expose the doped amorphous silicon layer 50. At this time, since the photoresist pattern 212 of the portion D is also etched, the thickness becomes thin, so that the photoresist pattern 212 may be removed so that the doped amorphous silicon layer 50 of the portion D is not exposed. Next, the doped amorphous silicon layer 50 and the amorphous silicon layer 40 of the F portion are removed.

Next, as shown in FIGS. 12A and 12B, when the photoresist pattern 212 remaining in the portion D is removed, an island-shaped ohmic contact layer 51 and a semiconductor layer 41 below the gate electrode 22 are removed. Is formed.

Next, as shown in FIGS. 13A and 13B, a conductor or a metal for data wiring is deposited by a method such as sputtering and patterned by a photolithography process using a mask to form a data line 61, a source electrode 62, and a drain electrode 63. ) And a data line including the data pad 64. In this case, the data line 61 is formed on the auxiliary data line 25 and is connected to the data line 61 through the contact hole 32. Next, the ohmic contact layer 51 not covered by the source electrode 62 and the drain electrode 63 is removed to separate the two portions 52 and 53.

Next, as shown in FIGS. 14A and 14B, the protective layer 70 is formed and patterned by a photolithography process using a mask to form contact holes 72, 73, and 74.

Next, as shown in FIGS. 8 and 9, a transparent conductive material such as ITO or IZO is deposited and patterned by a photolithography process using a mask to form the pixel electrode 80, the auxiliary gate pad 83, and the auxiliary data pad ( 84).

Meanwhile, both the auxiliary gate line and the auxiliary data line may be formed. In this case, the auxiliary data line 25 is formed when the gate lines 21, 22, and 23 are formed, and the data lines 61, 62, 63, and 64 are formed. In forming, the auxiliary gate line 65 is formed. Further, in the process of forming the ohmic contact layer 51 and the semiconductor layer 41, the same as in the first and second embodiments without forming a photoresist pattern on the gate line 21 and the auxiliary data line 25. The etching process is performed to form a contact hole 31 exposing the gate line 21 and a contact hole 32 exposing the auxiliary data line 25 together in the gate insulating film 30.

As described above, in the present invention, when forming the ohmic layer and the ohmic contact layer through a single photo process, a contact hole connected to the gate line or the data line is formed, and an auxiliary gate line and an auxiliary data line overlapping the gate line or the data line are formed. The occurrence of disconnection can be reduced.

Claims (15)

A gate line formed over the insulating substrate, An insulating film covering the gate line, A data line formed on the insulating film, An auxiliary data line formed of the same layer as the gate line and connected to the data line through a first contact hole formed in the insulating layer, and through a second contact hole formed of the same layer as the data line and formed in the insulating layer. A thin film transistor substrate for a liquid crystal display device comprising at least one of an auxiliary gate line connected to the gate line. A gate wiring including a gate line and a gate electrode formed on an insulating substrate, A gate insulating film covering the gate wiring, A semiconductor layer formed in an island shape on the gate electrode; A data line including a data line, a source electrode, and a drain electrode formed on the semiconductor layer and the gate insulating layer; A protective film covering the data wiring, A pixel electrode formed on the passivation layer, An auxiliary data line formed of the same layer as the gate line and connected to the data line through a first contact hole formed in the gate insulating film, and a second contact hole formed of the same layer as the data line and bored in the gate insulating film A thin film transistor substrate for a liquid crystal display device including any one or more of an auxiliary gate line connected to the gate line through. In claim 2, The auxiliary data line overlaps the data line. In claim 2, The auxiliary gate line overlaps the gate line. In claim 2, And a resistive contact layer formed between the semiconductor layer and the data line. Forming a gate wiring including a gate line and a gate electrode on the insulating substrate, Depositing a gate insulating film, Depositing an amorphous silicon layer, Forming at least one contact hole in the gate insulating film using a photoresist pattern having a different thickness according to a position and simultaneously forming a semiconductor layer made of the amorphous silicon; Forming a data line including a data line, a source electrode and a drain electrode, Forming a protective film, Forming a pixel electrode Method of manufacturing a thin film transistor substrate for a liquid crystal display device comprising a. In claim 6, In the forming of the data line, an auxiliary gate line overlapping the gate line is formed, and the contact hole exposes the gate line, and the thin film for a liquid crystal display device connects the gate line and the auxiliary gate line through the contact hole. Method for manufacturing a transistor substrate. In claim 6, Forming an auxiliary data line overlapping the data line in the forming of the gate wiring, wherein the contact hole exposes the auxiliary data line, and connects the data line and the auxiliary data line through the contact hole. Method of manufacturing a thin film transistor substrate. In claim 6, Forming an auxiliary data line overlapping the data line in the forming of the gate line and forming an auxiliary gate line overlapping the gate line in the forming of the data line, wherein the contact hole is the gate line and the auxiliary data A method of manufacturing a thin film transistor substrate for a liquid crystal display device, wherein each line is exposed, the gate line and the auxiliary gate line are connected through the contact hole, and the data line and the auxiliary data line are connected to each other. In claim 6, The photoresist pattern may include a first part having a first thickness, a second part thicker than the first thickness, and a third part having no thickness and excluding the first and second parts. Manufacturing method. In claim 10, The photoresist pattern is formed using an optical mask including a first region, a second region having a lower transmittance than the first region, and a third region having a higher transmittance than the first region, wherein the first, second, And a second and a third region are aligned to correspond to the first, second and third portions of the photoresist pattern, respectively. In claim 11, In the photoresist pattern, the third portion is a portion where the contact hole is to be formed, the second portion is formed above the semiconductor layer, and the third portion is formed to be located at a portion except the first and second portions. Method for manufacturing a thin film transistor substrate for use. In claim 12, A method of manufacturing a thin film transistor substrate for a liquid crystal display device, wherein a slit pattern smaller than the resolution of a transflective film or an exposure machine is formed in the photomask to differently control the transmittances of the first to third regions. In claim 6, And forming an ohmic contact layer between the semiconductor layer and the data line. The method of claim 14, And forming the semiconductor layer, the ohmic contact layer, and the contact hole in one photo process.