KR20020060452A - Semiconductor integrated circuit and method for manufacturing the same - Google Patents

Abstract

The present invention discloses a semiconductor integrated circuit and a method of manufacturing the same. A method of manufacturing a semiconductor integrated circuit according to the disclosed invention is as follows. First, an interlayer insulating film is formed on the semiconductor substrate structure on which the circuit elements are formed. The interlayer insulating film is then etched to expose a plurality of portions of the surface of the semiconductor substrate structure, thereby forming a plurality of holes. Subsequently, a metal layer is deposited on the interlayer insulating film provided with holes to form metal wiring for bonding pads having a topology.

Description

Semiconductor integrated circuit and method for manufacturing the same

The present invention relates to a semiconductor integrated circuit and a method of manufacturing the same, and more particularly, to a bonding pad structure of a semiconductor integrated circuit and a method of manufacturing the same.

After completing the fabrication process of the semiconductor integrated circuit, the integrated circuit is assembled into a package for use in a printed circuit board. Here, the metal on the bonding pad of the circuit element having a lead extending to the inner lead of the package lead frame to electrically connect the inner lead of the package and the bonding pad of the manufactured circuit element. Bonds are formed.

1 is a cross-sectional view of a semiconductor integrated circuit having a general bonding pad.

Referring to the drawings, the upper insulating film 12 of the semiconductor substrate 10 is formed. At this time, semiconductor devices are formed on the semiconductor substrate 10. After the barrier metal film 14 is formed on the insulating film 12, the bonding metal wiring layer 16 is formed on the barrier metal film 14. Thereafter, the passivation film 18 is formed on the bonding metal wiring layer 16, and then predetermined portion patterning is performed so that the bonding pad region is limited. As a result, the bonding pad 20 is completed.

However, in the conventional bonding pad 20, pressure is applied by the bonding or the probe during the wire bonding process and the probing test process. Thus, the pressure applied to the bonding pad 20 acts as a severe mechanical stress. For this reason, a crack (indicated by C of FIG. 1) is likely to occur in the passivation film 18 and the lower interlayer insulating layer, and in severe cases, the interlayer insulating layer is destroyed. For this reason, the reliability of a semiconductor element deteriorates.

Accordingly, the technical problem of the present invention is to provide a semiconductor integrated circuit having a bonding pad that can alleviate stress.

Another object of the present invention is to provide a method for manufacturing the semiconductor integrated circuit.

1 is a cross-sectional view illustrating a bonding pad of a general semiconductor integrated circuit.

2A and 2B are cross-sectional views illustrating a bonding pad of a semiconductor integrated circuit according to an embodiment of the present invention.

(Explanation of symbols for the main parts of the drawing)

30-semiconductor substrate 34-active device region

44-Third interlayer insulating film 48-Metal wiring for bonding pads

In order to achieve the above technical problem of the present invention, a semiconductor integrated circuit according to one aspect of the present invention, a semiconductor substrate, an interlayer insulating film formed on the semiconductor substrate, having a topology on the surface, and on the interlayer insulating film And a bonding pad provided with a topology by the interlayer insulating film.

Here, the interlayer insulating film has a plurality of holes and has a topology. A conductive layer may be coated on each of the inner walls of the holes of the interlayer insulating film.

The semiconductor substrate may include an active device region, and may include at least one interlayer insulating layer and at least one metal wiring between the semiconductor substrate including the active region and the interlayer insulating layer including the plurality of holes.

In addition, a method for manufacturing a semiconductor integrated circuit according to another aspect of the present invention is as follows. First, an interlayer insulating film is formed on the semiconductor substrate structure on which the circuit elements are formed. The interlayer insulating film is then etched to expose a plurality of portions of the surface of the semiconductor substrate structure, thereby forming a plurality of holes. Subsequently, a metal layer is deposited on the interlayer insulating film provided with holes to form metal wiring for bonding pads having a topology.

Here, the semiconductor substrate structure is obtained by forming at least one interlayer insulating film over the semiconductor substrate including the active device, and forming at least one metal wiring over the interlayer insulating film.

In addition, between the step of forming a hole and the step of forming the metal wiring for the bonding pad, forming a conductive layer on the top of the resultant; And chemical mechanical polishing the conductive layer.

(Example)

Hereinafter, preferred embodiments of the present invention will be described based on the accompanying drawings.

2A and 2B are cross-sectional views illustrating a semiconductor integrated circuit according to the present invention.

Here, the embodiments of the present invention can be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below. Embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. Accordingly, the shape and the like of the elements in the drawings are exaggerated to emphasize a more clear description, and the elements denoted by the same reference numerals in the drawings means the same elements. In addition, where a layer is described as being "on" another layer or semiconductor substrate, a layer may exist in direct contact with the other layer or semiconductor substrate, or a third layer therebetween. Can be done.

First, referring to FIG. 2A, a semiconductor substrate 30 is prepared. In the semiconductor substrate 30, the active device region 34 is defined by the device isolation region 32. In addition, the active device region 34 may be, for example, a diode region, a silicon controlled rectifier (SCR) or a resistive region. In addition, various circuit elements may be densely integrated in the semiconductor substrate 30 in addition to the active device region 32. The first interlayer insulating layer 36 is formed on the semiconductor substrate 30. The first interlayer insulating layer 36 is etched to expose a plurality of portions per active device region, thereby forming a first contact hole h ₁ . Subsequently, the first conductive layer is formed to sufficiently fill the first contact hole h ₁ , and then the first conductive layer is chemical mechanical polishing (hereinafter referred to as CMP) to form the conductive plug 38a. do. A tungsten metal film may be used as the conductive layer constituting the conductive plug 38a. Here, since the CMP process was performed to form the conductive plug 38a, the semiconductor substrate resultant surface becomes flat. Then, the first metal wire 38b is routed to be in contact with the conductive plugs 38a of each active region. In this case, one first metal wire 38b may be formed in each active device area.

Next, as shown in FIG. 2B, a second interlayer insulating film 40 is formed on the semiconductor substrate 30 to which the first metal wiring 38 is routed. In this case, a film having a planarization property may be used as the second interlayer insulating film 40. In addition, after the second interlayer insulating film 40 is deposited by a general silicon oxide film, the CMP process may be performed to planarize the surface of the second interlayer insulating film 40. The second metal wire 42 is formed on the second interlayer insulating film 40 to serve as a buffer layer. In this case, for example, an aluminum metal film may be used as the second metal wire 42, or a barrier metal film such as titanium or a titanium nitride film may be used.

A third interlayer insulating film 44 is deposited on the second metal wire 42. Thereafter, the third interlayer insulating film 44 is patterned so that multiple regions of the second metal wiring 42 can be exposed. Accordingly, a plurality of second contact holes h ₂ is formed in the third interlayer insulating film 44. Here, the second diameter of the contact hole (h ₂₎ being greater than the first contact hole (h ₁₎ in diameter. In addition, the number and size of the second contact holes h ₂ may be adjusted so that a sufficient topology can be generated in the third interlayer insulating film 44. Thereafter, a second conductive layer, for example, a tungsten metal layer, is formed on top of the third interlayer insulating film 44 having a topology, and then CMP so that the surface of the third interlayer insulating film 44 is exposed. At this time, even if the second conductive layer is CMP, since the size of the second contact hole h2 is relatively large, the second conductive layer is mostly removed without being embedded in the second contact hole h2, or the second contact hole h2. ) Will remain on the inner wall. Here, reference numeral 46 denotes a residual conductive layer remaining in the second contact hole h2. Accordingly, the resultant surface of the semiconductor substrate 30 is provided with a topology by the third interlayer insulating film 44 having the second contact hole h ₂ .

Thereafter, a metal wiring 48 for a bonding pad is formed on the resultant. In this case, the bonding pad metal wire 48 is formed in a curved shape by the second contact hole h ₂ of the third interlayer insulating film 44. As the bonding wire metal wiring 48, for example, an aluminum alloy film may be used. As such, as the bonding pad metal wire 48 is formed to have a curved shape, that is, a topology, even when a pressure is applied to the bonding pad metal wire 48 during the wire bonding or probing test, it is generated by such pressure. The stress that is caused is alleviated by the third interlayer insulating film 44. That is, when the bonding pads are formed to bend, the stress is alleviated considerably than when the bonding pads are formed flat, so that the stress is not transferred to the lower insulating film. Accordingly, problems such as cracks do not occur in the insulating film.

Next, the passivation film 50 is formed on the bonding pad metal wiring 48. Here, the passivation film 50 may be a silicon nitride film or a silicon nitride oxide film having high external charges and water trapping characteristics and having a strong film quality. Thereafter, a predetermined portion of the metal wiring 48 for bonding pads is patterned to expose the pads.

Table 1 below is a table measuring the stress applied to the curved bonding pad type and the flat bonding pad type when the thickness of the third interlayer insulating film 44 is the same.

Bonding pad type Curved Bonding Pads Flat Type Bonding Pads Third interlayer insulating film thickness 6000 Å 6000 Å Stress applied to the third interlayer insulating film 89.4 MPa 240.9 MPa Average stress applied to metal wiring 58.8 MPa 150.6 MPa

According to Table 1, when pressure is applied to each bonding pad under the same wire bonding condition (or the same probing test condition), the curved bonding pad is less stressed than the flat bonding pad. In addition, since the third interlayer insulating film of the curved type bonding pad is also less stressed than the third interlayer insulating film of the flat type bonding pad, there is less risk of cracking.

As described in detail above, according to the present invention, the metal wiring for the bonding pad is formed to be bent. Accordingly, even when a predetermined pressure is applied to the bonding pad during the wire bonding or probing test, the stress is alleviated by the bent portion, thereby preventing cracking or breakage of the underlying insulating film.

Claims (7)

Semiconductor substrates; An interlayer insulating film formed on the semiconductor substrate and having a topology on a surface thereof; And And a bonding pad formed on the interlayer insulating film and provided with a topology by the interlayer insulating film. The semiconductor integrated circuit according to claim 1, wherein the interlayer insulating film has a plurality of holes. The semiconductor integrated circuit according to claim 2, wherein a conductive layer is coated on each of the inner walls of the holes of the interlayer insulating film. The semiconductor substrate of claim 2, wherein the semiconductor substrate comprises an active device region, and at least one interlayer insulating layer and at least one metal interconnection between the semiconductor substrate including the active region and the interlayer insulating layer including the plurality of holes. Semiconductor integrated circuit comprising a. Providing a semiconductor substrate structure having circuit elements formed thereon; Forming an interlayer insulating film on the semiconductor substrate structure; Etching the interlayer insulating film to expose a plurality of surfaces of the semiconductor substrate structure to form a plurality of holes; And And depositing a metal layer on the interlayer insulating layer provided with the holes to form a metal wiring for a bonding pad having a topology. The method of claim 5, wherein providing the semiconductor substrate structure comprises: Forming at least one interlayer insulating film over the semiconductor substrate including the active device; And And forming at least one metal wiring on the interlayer insulating film. The method of claim 5, further comprising: forming a conductive layer on the resultant, between forming the hole and forming the metal wiring for the bonding pad; And chemical mechanical polishing the conductive layer.