KR20020057235A - Method for manufacturing in liquid crystal display device - Google Patents

Abstract

The present invention provides a method of manufacturing a liquid crystal display device in which an ITO layer and a gate are separated by an interlayer insulating layer, and two separated layers are formed as vias to form another ITO layer as a bridge to form a gate common short. A patterning method comprising: patterning a gate simultaneously with a common line on a glass; forming a first gate insulating film on a front surface including the common line and the gate; forming an ITO layer on a front surface and selectively patterning the first ITO Forming a layer; forming a second gate insulating film on the front surface and performing an active patterning and source / drain patterning process; forming an interlayer insulating layer on the front surface and selectively etching to expose portions of the gate and the first ITO layer Forming a contact hole so as to; And patterning the second ITO layer as a contact bridge layer on the front surface.

Description

Manufacturing method of liquid crystal display device {METHOD FOR MANUFACTURING IN LIQUID CRYSTAL DISPLAY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device. In particular, a gate common short can be improved by separating an ITO layer from a gate as an interlayer insulating layer, and forming a separate ITO layer as a bridge after vias are formed. It relates to a method of manufacturing a liquid crystal display device.

With the development of new advanced video devices such as high definition TVs (hereinafter referred to as HDTVs), there is a demand for flat panel displays.

LCD is a representative technology of flat panel display, and it does not have problems such as colorization, low power, and high speed which ELD (electro luminescence display), VFD (vacuum fluorescence display), PDP (plasma display panel) cannot solve.

The LCD is divided into two types, passive and active. The active LCD is controlled by an active element such as TFT to control each pixel one by one, which is much superior to the passive LCD in speed, viewing angle, and contrast. It is used as the most suitable indicator for HDTV that requires more than 10,000 pixels of resolution. Accordingly, as the importance of TFTs is highlighted, R & D on them is intensifying.

In particular, unlike the TFT-LCD operated by TN (twist nematic) liquid crystal, the TFT-LCD in the IPS mode forms a common electrode on the TFT substrate by using a gate metal, and thus usually has four masks. Manufacturing is taking place.

Hereinafter, a manufacturing process of the liquid crystal display of the prior art will be described with reference to the accompanying drawings.

1A and 1B are cross-sectional and planar configuration diagrams in the prior art ITO patterning, and FIGS. 2A and 2B are cross-sectional and planar configuration diagrams in the prior art gate patterning.

3 is a cross-sectional and plan view showing the gate common short problem due to ITO residues.

The prior art first deposits an ITO layer on the substrate 1 and selectively patternes it using an ITO mask, as in FIGS. 1A and 1B.

In the prior art, a process of 18 "FPS has a gate line + common line + ITO pattern formed on the same layer at the time of Cst and Common formation, and ITO contacts the common line to serve as a pixel for Cst.

Usually, ITO is deposited by sputtering after initial cleaning, and the 1st ITO process is completed in a box-shaped pattern.

After that, the gate metal is deposited and patterned on the same film. At this time, the gate line to form a channel on the TFT and the common line to deliver a common voltage to the ITO are simultaneously patterned to form a Cst pixel.

2A and 2B, a gate forming material layer is formed on the entire surface including the ITO pattern layer 2 and selectively patterned using a gate mask to form the gate 3.

In such a prior art process, as shown in FIG. 3, since the ITO and the gate are patterned on the same glass, the probability that a gate common short is generated by the ITO residue 4 increases.

This happens the same regardless of the structural change of the common line.

In manufacturing such a liquid crystal display device of the prior art, there are the following problems.

First, patterning the ITO and gate over the same glass increases the probability that gate common shorts will be caused by ITO residues.

Second, since ITO is an oxide film, the interfacial reaction with glass is well performed, but the etching rate is lowered, which causes a limitation in capacity.

The main cause of yield degradation in current 18 "FPS is gate common short, which is caused by the structural problems being designed where the ITO and common lines are formed on the same layer.

The present invention is to solve the problems arising in the manufacturing of the liquid crystal display of the prior art, the separation between the ITO layer and the gate as an interlayer insulating layer, and after forming the two separated vias via another ITO layer to form a bridge It is an object of the present invention to provide a method for manufacturing a liquid crystal display device capable of improving a gate common short.

1A and 1B are cross-sectional and planar views of the prior art ITO patterning

2A and 2B are cross-sectional and planar configuration diagrams in the prior art gate patterning

3 is a cross-sectional and plan view showing the gate common short problem due to ITO residues.

4 is a plan view illustrating a liquid crystal display according to the present invention.

5A and 5B are cross-sectional views of a liquid crystal display according to the present invention.

-Explanation of symbols for the main parts of the drawing-

51. Glass 52. First Gate Insulator

53. 1st ITO 54. 2nd gate insulating film

55. Common line 56. Second ITO

57. Passivation layer 58. Source / drain

According to an aspect of the present invention, there is provided a method of manufacturing a liquid crystal display device, the method comprising: patterning a gate simultaneously with a common line on a glass; Forming a first gate insulating film on the front surface; Forming an ITO layer on the front surface and selectively patterning to form a first ITO layer; Forming a second gate insulating film on the front surface and the active patterning and source / drain patterning process Forming an interlayer insulating layer on the front surface and selectively etching to form contact holes to expose a portion of the gate and the first ITO layer; And patterning the second ITO layer as a contact bridge layer on the front surface.

Hereinafter, a method of manufacturing a liquid crystal display according to the present invention will be described in detail with reference to the accompanying drawings.

4 is a plan view illustrating a liquid crystal display according to the present invention, and FIGS. 5A and 5B are cross-sectional views illustrating a process of the liquid crystal display according to the present invention.

The present invention applies the principle that 1st ITO and gate are separated using an interlayer insulating film without forming ITO and gate or common line on the same layer, and the contact of these two layers is formed by floating pattern of 2nd ITO pattern. .

The process sequence is as follows.

First, the gate is patterned at the same time as the common line 55.

The first gate insulating layer 52 is deposited on the entire surface including the common line 55 and the gate.

An ITO layer is formed on the entire surface on which the first gate insulating film 52 is formed and selectively patterned to form the first ITO layer 53.

In addition, a second gate insulating layer 54 is formed on the entire surface including the first ITO layer 53, and active patterning and source / drain 58 patterning are performed.

Here, any one of Ti / Al / Ti, Mo / AlNd / Al, Mo / Al / Mo, Mo / Al, Mo / Ad, Mo / Al / Ta, Cr / Al is used as the gate and source / drain layers. To form.

Subsequently, a passivation layer 57 is formed on the entire surface and selectively etched to form contact holes to expose the gate and a part of the first ITO layer 53.

Here, the passivation film used as the interlayer insulating layer is formed with a thickness of 300 kPa to 2000 kPa using any one of SiNx, SiON and SiOF.

The second ITO layer 56 is patterned with a contact bridge layer on the front surface.

Thus, without forming ITO and gate or common line on the same layer, 1st ITO and gate are separated by using an interlayer insulating film, and the contact between these two layers is formed by floating pattern of 2nd ITO pattern to solve gate common short problem. I can solve it.

In the present invention, the common line in the active panel may be formed of the first ITO layer without forming a series bar, and only the pad portion to which the common signal is input and the outermost pixel of the active panel may form the series bar.

It is also possible to reverse the order of the gate and the first ITO pattern process.

The present invention can be applied to a technique for manufacturing an array process of a large size TFT-LCD having 18 ″ FRS (Fringe Field Swithcing) having an In Plane Switch (IPS) structure.

However, in addition to the common metal and ITO connected to the other metal layer it is obvious that the same can also be applied to form a contact bridge.

Such a manufacturing method of the liquid crystal display device according to the present invention has the following effects.

First, the ITO residue remaining between the patterns in the 1st ITO pattern completely eliminates the occurrence of the gate common short of the common line, which occurs later as a bridge between the gate and the common line in the gate pattern. Can be.

Second, since the reliability of the device can be improved only by depositing the interlayer insulating layer without the addition of a process requiring a long time such as a mask process or etching, the yield can be improved.

Third, even if a gate common short occurs, repair is difficult because the address cannot be easily found.

That is, in the present invention, the GCS is caused by the 2nd ITO, and this case can be easily found during the cell test.

Fourth, the ITO on SiNx is 20% faster than the ITO on glass and stable in residue, resulting in improved process reliability.

Fifth, the black matrix layer can be made relatively small to improve the aperture ratio, and the GCS by the gate can be effectively reduced by removing the series bar of the common.

Claims (4)

In manufacture of the liquid crystal display device of an IPS mode, Patterning the gate simultaneously with the common line on the glass; Forming a first gate insulating film on the entire surface including the common line and the gate; Forming an ITO layer on the front surface and selectively patterning the first ITO layer; Forming a second gate insulating film on the entire surface and performing an active patterning and source / drain patterning process; Forming a contact hole so as to expose a portion of the gate and the first ITO layer by forming an interlayer insulating layer on the front surface and selectively etching the interlayer insulating layer; And patterning a second ITO layer as a contact bridge layer on a front surface thereof. The method of manufacturing a liquid crystal display device according to claim 1, wherein the interlayer insulating layer is formed to have a thickness of 300 kPa to 2000 kPa using any one of SiNx, SiON, and SiOF. 2. The gate and source / drain layers of claim 1, wherein the gate and source / drain layers are any of Ti / Al / Ti, Mo / AlNd / Al, Mo / Al / Mo, Mo / Al, Mo / Ad, Mo / Al / Ta, Cr / Al. It forms using one, The manufacturing method of the liquid crystal display device characterized by the above-mentioned. The method of claim 1, wherein the second ITO layer is formed in an island-like floating pattern to connect the gate, the common line, and the first ITO layer.