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KR20020055925A - Method of manufacturing a semiconductor device - Google Patents

Method of manufacturing a semiconductor device Download PDF

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KR20020055925A
KR20020055925A KR1020000085185A KR20000085185A KR20020055925A KR 20020055925 A KR20020055925 A KR 20020055925A KR 1020000085185 A KR1020000085185 A KR 1020000085185A KR 20000085185 A KR20000085185 A KR 20000085185A KR 20020055925 A KR20020055925 A KR 20020055925A
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gate structure
metallic
semiconductor device
selective
wet cleaning
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KR100611473B1 (en
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정우석
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박종섭
주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Semiconductor Memories (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE: A method for fabricating a semiconductor device is provided to effectively eliminate an abnormal growth in a subsequent selective epitaxial growth(SEG) process, by removing metallic residue through a wet oxide process after a gate is etched. CONSTITUTION: A metallic gate structure is formed on a substrate. The first wet cleaning process is performed to eliminate the metallic residue generated in forming the metallic gate structure. A selective oxide layer is formed in a part of the sidewall of the gate structure. The second wet cleaning process is carried out. After an interlayer dielectric and a contact hole are formed, an SEG process is performed.

Description

반도체 소자 제조 방법{Method of manufacturing a semiconductor device}Method of manufacturing a semiconductor device

본 발명은 반도체 소자 제조 방법에 관한 것으로, 특히 메탈 게이트의 에치시 생성된 잔유물을 효과적으로 제거하여 선택적 에피텍셜 성장 콘택 플러그 형성시 비정상 성장을 억제할 수 있는 반도체 소자 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device capable of suppressing abnormal growth when forming a selective epitaxial growth contact plug by effectively removing residues generated during etching of a metal gate.

선택적 실리콘 성장 기술의 반도체 소자 이용 가능성은 셀 사이즈의 축소나공정 단순화 차원에서 높이 평가되고 있다. 특히 디램에서는 이미 십 여년 전 부터 선택적 실리콘 성장 아이솔레이션(ISOLATION)에 대한 연구로 확장되고 있다.The availability of semiconductor devices in selective silicon growth technology is highly appreciated in terms of cell size reduction and process simplification. In particular, DRAM has been expanding its research on selective silicon growth isolation (ISOLATION) for over a decade.

메모리 반도체 소자에서 비정질 실리콘은 플러그 형성에 활용되어 왔다. 비정질 실리콘은 도핑 농도를 자유롭게 조절할 수 있고 스텝 커버리지가 우수하여 보이드 없이 갭필(GAP-FILL)이 가능하다. 그러나 셀 사이즈가 축소되면서 플러그의 콘택 저항이 문제되고 있고, 높은 저항은 디바이스 동작에 악영향을 미칠 수 있다. 이러한 문제를 해결하고, 공정 단순화를 위해 선택적 실리콘 성장 플러그의 활용이 제안되고 있다. 그러나, 새로운 게이트 구조로 메탈 게이트가 부각되면서 선택적 실리콘 성장 플러그 형성에 어려움을 겪고 있다. 즉, 메탈 게이트 에치시 메탈 폴리머와 메탈 에처(ETCHER)에서 유발되는 불순물이 선택적 실리콘 성장의 선택성에 악 영향을 미칠 수 있기 때문이다. 특히, 텅스텐 게이트 에치 후 에치 계면을 따라 폴리머성 텅스텐 잔유물이 발견되는데, 이것은 선택적 실리콘 성장의 비정상 성장을 유발 시키는 것으로 밝혀졌다.In memory semiconductor devices, amorphous silicon has been utilized to form plugs. Amorphous silicon can freely adjust the doping concentration and has excellent step coverage, allowing gap fill without voids. However, as the cell size shrinks, plug contact resistance becomes a problem, and high resistance can adversely affect device operation. In order to solve these problems and simplify the process, the use of selective silicon growth plugs has been proposed. However, as the metal gate is emerging as a new gate structure, it is difficult to form a selective silicon growth plug. That is, impurities generated from metal polymers and metal etchant (ETCHER) during the metal gate etch may adversely affect the selectivity of selective silicon growth. In particular, polymeric tungsten residues are found along the etch interface after tungsten gate etch, which has been found to cause abnormal growth of selective silicon growth.

따라서 본 발명은 선택적 플러그 공정을 적용함에 있어 비정상 성장(ABNORMAL)의 원인이 되는 금속성 폴리머를 제거하는 방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for removing a metallic polymer which causes abnormal growth (ABNORMAL) in applying a selective plug process.

본 발명에 의하면, 게이트 에치와 선택적 산화막 형성 이후 습식 세정을 실시하므로써 선택적 실리콘 성장시 비정상 성장을 억제 할 수 있다.According to the present invention, by performing wet cleaning after the gate etch and the selective oxide film formation, it is possible to suppress abnormal growth during selective silicon growth.

도 1a 내지 도 1c는 본 발명에 다른 반도체 소자 제조 방법을 설명하기 위한 단면도.1A to 1C are cross-sectional views illustrating another semiconductor device manufacturing method in accordance with the present invention.

도 2a 및 도2b는 텅스텐 게이트 식각 이후의 텅스텐 폴리머 및 SEG 성장시 비정상 SEG 플러그를 나타내는 도면.2A and 2B show abnormal SEG plugs upon tungsten polymer and SEG growth after tungsten gate etching;

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

10: 기판20: 게이트 구조10: substrate 20: gate structure

상술한 목적을 달성하기 위한 본 발명에 따른 반도체 소자 제조 방법은 기판상에 금속성 게이트 구조를 형성하는 단계와;A semiconductor device manufacturing method according to the present invention for achieving the above object comprises the steps of forming a metallic gate structure on a substrate;

상기 금속성 게이트 구조 형성시 생성된는 금속성 잔유물을 제 1 습식 세정 공정에 의해 제거하는 단계와;Removing, by a first wet cleaning process, the metallic residue produced during formation of the metallic gate structure;

상기 게이트 구조 측벽의 일부에 선택적 산화막을 형성하는 단계와;Forming a selective oxide film on a portion of the sidewall of the gate structure;

상기 산화막 형성 후 제 2 습식 세정 공정을 실시하는 단계와;Performing a second wet cleaning process after the oxide film is formed;

층간 절연막 및 콘택홀 형성 후 선택적 에피텍셜 성장 공정을 실시하는 단계를 포함하여 이루어진 것을 특징으로 한다.And performing a selective epitaxial growth process after forming the interlayer insulating film and the contact hole.

이하, 첨부된 도면을 참조하여 본 발명을 더욱 상세히 설명하기로 한다.Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

선택적 에피텍셜 성장 플러그는 0.15㎛ 기술 이하에서 기존의 아몰퍼스 실리콘을 플러그로 사용하는 경우 최대 문제점인 저항 증가 현상을 근본적으로 해결할 수 있게 한다. 본 발명은 메탈 게이트 구조에서 게이트 에치에 의한 메탈 잔유물 및 메탈에처(etcher)에서 발생하는 메탈성 임퓨리티를 효과적으로 제거할 수 있는 세정 방법을 제공한다. 이것은 후속 선택적 에피텍셜 플러그 형성에 있어 비정상 성장을 제어하는 중요한 역할을 하게된다.Selective epitaxial growth plugs fundamentally solve the biggest problem of increased resistance when using conventional amorphous silicon as plugs under 0.15µm technology. The present invention provides a cleaning method that can effectively remove the metallic residue caused by the gate etch and the metal etchant in the metal gate structure. This plays an important role in controlling abnormal growth in subsequent selective epitaxial plug formation.

도 1a 내지 도 1c는 본 발명에 따른 반도체 소자 제조 방법을 설명하기 위한 단면도이다.1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

도 1a는 기판(10)상에 게이트 구조가 형성된 단면도를 나타내며, 도 1b는 게이트 구조 측벽에 선택적 산화막이 형성된 상태를 도시하고 있다. 게이트 구조를형성하기 위해선 적절한 에치 공정이 요구된다. 이러한 에치 공정에 의해 메탈계 게이트 형성시 잔유물이 발생된다. 이 잔유물을 제거하기 위해 세정 공정을 실시하는데 이를 상세히 설명하기로 한다.FIG. 1A illustrates a cross-sectional view in which a gate structure is formed on the substrate 10, and FIG. 1B illustrates a state in which a selective oxide film is formed on a sidewall of the gate structure. Proper etching process is required to form the gate structure. By the etching process, residues are generated when forming the metal gate. A washing process is performed to remove this residue, which will be described in detail.

게이트 에치 공정 후 H2SO4와 H2O2가 30:1-100:1비율로 형성된 용액에 3 내지 20분 가량 담근다. 그후에 HF 희석액에 50:1-500:1 수용액에 10 내지 100초 동안 담그어 잔유물을 제거한다. 이때 배쓰(BATH)의 온도는 80 내지 100℃가 바람직하다.After the gate etch process, the solution is immersed for about 3 to 20 minutes in a solution in which H 2 SO 4 and H 2 O 2 are formed in a ratio of 30: 1-100: 1. Thereafter, the residue is immersed in a 50: 1-500: 1 aqueous solution for 10 to 100 seconds in a dilute HF solution. At this time, the temperature of the bath (BATH) is preferably 80 to 100 ℃.

선택적 산화막 형성 후에 세정 공정은 다음과 같다.The cleaning process after the selective oxide film formation is as follows.

게이트 에치 공정 후 H2SO4와 H2O2가 30:1-100:1비율로 형성된 용액에 5 내지 20분 가량 담근다. 그 후에 HF 희석액에 50:1-500:1 수용액에 30 내지 300초 동안 담그어 잔유물을 제거한다. 이때 배쓰(BATH)의 온도는 80 내지 100℃가 바람직 하며, 산화막 소모량이 약 10 내지 15Å가량이 되도록 한다.After the gate etch process, the solution is immersed for about 5 to 20 minutes in a solution in which H 2 SO 4 and H 2 O 2 are formed in a ratio of 30: 1-100: 1. Thereafter, the residue is immersed in a 50: 1-500: 1 aqueous solution for 30 to 300 seconds in a dilute HF solution. At this time, the temperature of the bath (BATH) is preferably 80 to 100 ℃, the oxide consumption is to be about 10 to 15Å.

이후, 층간 절연막 및 콘택홀 형성 후 선택적 에피텍셜 성장 플러그 공정을 진행하면 비정상 성장이 억제 되게 된다. 콘택을 형성한 후 선택적 에피텍셜 성장은 LPCVD방법에 의해 실시되는데 이를 좀 더 상세히 설명하기로 한다.Subsequently, when the selective epitaxial growth plug process is performed after the interlayer insulating layer and the contact hole are formed, abnormal growth is suppressed. Selective epitaxial growth after contact formation is performed by LPCVD method, which will be described in more detail.

선택적 에피텍셜 성장 전에 익스 시트 전 세정(EX-SITU PRE CLEANING)은 H2SO4와 H2O2를 4:1-50:1 비율로 맞춘 용액(80-120℃, 5-20분)에 담근 다음 50-100:1HF에 10 내지 30초 동안 담근다.EX-SITU PRE CLEANING prior to selective epitaxial growth was performed in a solution (80-120 ° C, 5-20 minutes) with H 2 SO 4 and H 2 O 2 in a 4: 1-50: 1 ratio. Soak and soak in 50-100: 1HF for 10-30 seconds.

이후, H2 베이크 공정에 의해 자연 산화막을 제거하게 되는데 800-900℃에서10분 내지 1분 실시한다. RTP방법을 사용하는 경우에는 순간적으로 950℃가까이 상승시킨 후 선택적 에피텍셜 성장 온도까지 하강 하는 것으로 진행한다.Thereafter, the natural oxide film is removed by the H2 baking process, which is performed at 800-900 ° C. for 10 minutes to 1 minute. In the case of using the RTP method, the temperature is raised to about 950 ° C and then lowered to the selective epitaxial growth temperature.

LPCVD 시스템에서는 DCS(disclorsiliane, SiCl2H2), HCl, H2가 공정가스로 포함되는데, 공정 조건으 DCS=0.1-2slm, HCl=0-3slm, H2=10-150slm플로우 범위에서 온도는 780-930℃로 유지하며, 압력은 20 내지 250까지 조절하고 온도가 낮아질 수록 압력도 낮아져야 한다.In the LPCVD system, DCS (disclorsiliane, SiCl2H2), HCl, H 2 that are included in the process gas, the process conditions lead DCS = 0.1-2slm, HCl = 0-3slm, H2 = 10-150slm in the flow temperature range 780-930 ℃ The pressure should be adjusted to 20 to 250 and the pressure should be lower as the temperature is lowered.

인 시투 도핑(in-situ doping)은 PH3(1-10%in H2)를 사용하며, 500-2500sccm 정도 흘려 준다. 인 시투 도핑레벨이 5x1019(atoms/cc)이상이 되도록 하는 것이 좋다.In-situ doping uses PH3 (1-10% in H 2 ) and flows about 500-2500sccm. It is recommended that the in-situ doping level is 5x10 19 (atoms / cc) or more.

상술한 선택적 에피텍셜 성장에 의해 형성된 플러그가 도 1c에 도시되어 있다.The plug formed by the selective epitaxial growth described above is shown in FIG. 1C.

도 2a 및 도 2b는 텅스텐 게이트 식각 이후의 텅스텐 잔유물 및 SEG(선택적 에피텍셜 성장) 성장시 비정상 SEG 플러그를 나타내는 도면이다.2A and 2B show abnormal SEG plugs upon tungsten residue and SEG (selective epitaxial growth) growth after tungsten gate etching.

도 3은 텅스텐 게이트 계면 부분에서 텅스텐 잔유물이 확실히 나타나고 있음을 보여 주고 있다.Figure 3 shows that the tungsten residue is clearly seen at the tungsten gate interface.

이러한 잔유물들은 전술한 본 발명에 따른 세정 공정에 의해 제거될 수 있다. 그로인하여 후속 공정인 선택적 에피텍셜 성장공정에서 비정상적인 성장을 억제할 수 있다.These residues can be removed by the cleaning process according to the invention described above. As a result, abnormal growth can be suppressed in the subsequent selective epitaxial growth process.

상술한 바와 같이 본 발명에 의하면 게이트 에치 후 습식 산화 공정에 의해 메탈성 잔유물을 효과적으로 제거하므로써 후속 공정인 선택적 에피텍셜 성장 공정에서의 비정상 성장을 효과적으로 제거 할 수 있다.As described above, according to the present invention, by removing the metal residues by the wet oxidation process after the gate etch, abnormal growth in the subsequent selective epitaxial growth process can be effectively removed.

Claims (3)

기판상에 금속성 게이트 구조를 형성하는 단계와;Forming a metallic gate structure on the substrate; 상기 금속성 게이트 구조 형성시 생성되는 금속성 잔유물을 제 1 습식 세정 공정에 의해 제거하는 단계와;Removing the metallic residue produced during the formation of the metallic gate structure by a first wet cleaning process; 상기 게이트 구조 측벽의 일부에 선택적 산화막을 형성하는 단계와;Forming a selective oxide film on a portion of the sidewall of the gate structure; 상기 산화막 형성 후 제 2 습식 세정 공정을 실시하는 단계와;Performing a second wet cleaning process after the oxide film is formed; 층간 절연막 및 콘택홀 형성 후 선택적 에피텍셜 성장 공정을 실시하는 단게를 포함하여 이루어진 것을 특징으로 하는 반도체 소자의 제조 방법.And forming a selective epitaxial growth process after forming the interlayer insulating film and the contact hole. 제 1 항에 있어서,The method of claim 1, 상기 제 1 습식 세정 공정은 H2SO4와 H2O2가 30:1-100:1비율로 형성된 용액에 5 내지 20분 가량 담근 다음 HF 희석액에 50:1-500:1 수용액에 10 내지 100초 동안 담그어 실시하는 것을 특징으로 하는 반도체 소자의 제조 방법.The first wet cleaning process is immersed for about 5 to 20 minutes in a solution in which H 2 SO 4 and H 2 O 2 are formed in a ratio of 30: 1-100: 1, and then, in a 50: 1-500: 1 aqueous solution, in a 50: 1-500: 1 aqueous solution. A method of manufacturing a semiconductor device, characterized in that soaking for 100 seconds. 제 1 항에 있어서,The method of claim 1, 상기 제 1 습식 세정 공정시 배쓰(BATH)의 온도는 80 내지 100℃인 것을 특징으로 하는 반도체 소자의 제조 방법Method of manufacturing a semiconductor device, characterized in that the temperature of the bath (BATH) in the first wet cleaning process is 80 to 100 ℃.
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KR101005841B1 (en) * 2010-04-13 2011-01-05 주식회사 도우엔지니어즈 River blow-in report with diffusion prevention function of spilled oil
US9006021B2 (en) 2010-04-27 2015-04-14 Tokyo Electron Limited Amorphous silicon film formation method and amorphous silicon film formation apparatus

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KR19980055970A (en) * 1996-12-28 1998-09-25 김영환 Transistor manufacturing method
KR19990027891A (en) * 1997-09-30 1999-04-15 윤종용 Method for forming gate electrode of polyside structure by heat treatment in vacuum
KR20000040110A (en) * 1998-12-17 2000-07-05 김영환 Fabrication method of semiconductor device
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KR101005841B1 (en) * 2010-04-13 2011-01-05 주식회사 도우엔지니어즈 River blow-in report with diffusion prevention function of spilled oil
US9006021B2 (en) 2010-04-27 2015-04-14 Tokyo Electron Limited Amorphous silicon film formation method and amorphous silicon film formation apparatus
KR101529171B1 (en) * 2010-04-27 2015-06-16 도쿄엘렉트론가부시키가이샤 Amorphous silicon film formation method and amorphous silicon film formation apparatus
KR101534634B1 (en) * 2010-04-27 2015-07-09 도쿄엘렉트론가부시키가이샤 Amorphous silicon film formation method and amorphous silicon film formation apparatus
US9123782B2 (en) 2010-04-27 2015-09-01 Tokyo Electron Limited Amorphous silicon film formation method and amorphous silicon film formation apparatus

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