KR20020055922A - Delay circuit - Google Patents

Abstract

The present invention relates to a delay circuit, comprising: a first constant current source for supplying current to a first node, a first switching means for driving the first constant current source, and a first source for adjusting the potential of the first node; A second constant current source, second switching means for driving the second constant current source, a capacitor for charging and discharging the current according to the potential of the first node, and a first enable signal for the first node. A first voltage comparator for comparing the potential and the first reference voltage to determine the output, and a second voltage comparator for comparing the potential of the first node and the second reference voltage to determine the output according to the second enable signal Latch means for latching an output signal of the first voltage comparator and an output signal of the second voltage comparator to output a delayed output signal, and an input signal and a delayed output signal. D) control means for selectively driving said first and second switching means and control means for outputting first and second enable signals for enabling said first and second voltage comparators; Delay circuits with small variations in delay time are also proposed by changes in voltage, temperature, and process conditions.

Description

Delay circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to delay circuits, and more particularly to delay circuits in which the rising time of the rising and falling edges of the input signal is constant despite supply voltage, temperature and process variations.

1 is a conventional delay circuit diagram used in a semiconductor integrated circuit.

When the enable signal flag en is applied in a high state, an input signal flag in is input to enable a plurality of inverters 13 to 19 in the path indicated by A at the rising edge of the input signal flag in. Is delayed for several tens of nanoseconds, and through the paths of the multiple inverters 20 to 22 of the path marked B at the falling edge of the input signal. Therefore, the delayed signals through these paths are inverted through the first and second inverters I11 and I12, respectively, and are input to the NAND gate 23. The NAND gate 23 outputs them in a logical combination, and is inverted delayed through the third to fifth inverters I13 to I15 and output as an output flag.

The delay time of the rising edge and the falling edge is determined by the number of inverters and the values of the resistance and the capacitor.

Conventional delay circuits as described above require multiple resistors and capacitors with an inverter when a delay of tens of nanoseconds is required. By using the inverter chain to delay for a predetermined time, the variation in delay time is very large with respect to changes in voltage, temperature and process. Therefore, it is difficult to accurately match the timing of the control signals, and may cause a malfunction in the internal circuit if the variation in the delay time is larger than the allowable range. In addition, since the passive devices such as resistors and capacitors are implemented in the integrated circuit, the area is increased and the error value is greatly different according to the process material and the process variable.

An object of the present invention is to provide a delay circuit having a small variation in delay time despite changes in voltage, temperature, or process.

Another object of the present invention is to use a constant current source, a current switch, a voltage comparator and a latch having a characteristic of generating a constant magnitude of current despite a change in voltage, temperature or process, instead of using an inverter chain and a passive element It is to provide a delay circuit with a small variation in time.

The present invention utilizes the principle that the voltage increases or decreases linearly with time while charging and discharging a constant current made from a constant current source to a capacitor using a current switch. In other words, in the basic relationship of V = Q / C = I * t / C, the voltage is linearly proportional to the time when the current and the capacitance of the capacitor are constant. Eventually, the voltage comparator detects the voltage value corresponding to the delay time to delay the signal by the target time.

1 is a conventional delay circuit diagram.

2 is a block diagram of a delay circuit according to the present invention.

3 is an operation timing diagram of FIG. 2.

4 is a circuit diagram illustrating an embodiment of a delay circuit according to the present invention.

5 is an operation timing diagram of FIG. 4.

<Explanation of symbols for the main parts of the drawings>

101: first constant current source 102: second constant current source

103: first switching means 104: second switching means

105: first voltage comparator 106: second voltage comparator

107: latch circuit 108: control means

A delay circuit according to the present invention includes a first constant current source for supplying current to a first node, first switching means for driving the first constant current source, and a second constant current for adjusting the potential of the first node. A source, second switching means for driving said second constant current source, a capacitor for charging and discharging a current in accordance with the potential of said first node, a potential of said first node in accordance with a first enable signal, A first voltage comparator for comparing the first reference voltage to determine the output, a second voltage comparator for comparing the potential of the first node and a second reference voltage according to a second enable signal to determine the output; Latching means for outputting a delayed output signal by latching the output signal of the first voltage comparator and the output signal of the second voltage comparator, and in accordance with the input signal and the delayed output signal. Control means for selectively driving the first and second switching means and control means for outputting first and second enable signals for enabling the first and second voltage comparators. do.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

2 is a block diagram of a delay circuit according to the present invention, and is configured as follows.

The first constant current source 101 is for supplying current to the first node Q31 in accordance with the first switching means 103 and is connected between the power supply terminal VDD and the first node Q31. The second constant current source 102 is for adjusting the potential of the first node Q31 in accordance with the second switching means 104 and is connected between the first node Q31 and the ground terminal Vss. The capacitor C31 is for charging current according to the potential of the first node Q31 and is connected between the first node Q31 and the ground terminal Vss. The first voltage comparator 105 compares the potential of the first node Q31 and the first reference voltage Vr1 according to the first enable signal EN1 to determine the output. The first node Q31 The potential of is input to the non-inverting input terminal, and the first reference voltage Vr1 is input to the inverting input terminal. The second voltage comparator 106 determines the output by comparing the potential of the first node Q31 and the second reference voltage Vr2 according to the second enable signal EN2. Is input to the inverting input terminal, and the second reference voltage Vr2 is input to the non-inverting input terminal. The latch circuit 107 consists of first and second NAND gates 31 and 32 to latch the input data for a predetermined time. Here, the first NAND gate 31 feedbacks and logically combines the output signal of the first voltage comparator 105 with the output signal of the second NAND gate 32, and the second NAND gate 32 is the second voltage comparator. The output signal of 106 and the output signal of the first NAND gate 31 are fed back and logically combined. Here, the path A of the first voltage comparator 105 and the first NAND gate 31 becomes a delay path at the rising edge, and the path of the second voltage comparator 106 and the second NAND gate 32 ( B) is the delay path at the falling edge. The first inverter I21 inverts the output signal of the latch circuit 107 and outputs a delayed output signal (flag out) delayed by a predetermined time. On the other hand, the control means 108 is a control signal and first and second voltage comparators for driving the first and second switching means 103 and 104 in accordance with an input signal (flag in) and a delayed output signal (flag out). Outputs first and second enable signals EN1 and EN2 for enabling the voltage comparator only when needed to reduce current consumption at 105 and 106.

The driving method of the delay circuit according to the present invention configured as described above will be described with reference to the operation timing diagram of FIG. 3.

When an input signal (flag in) transitions from a low state to a high state (corresponding to a rising delay time), the first switching means 103 is turned on so that the first node Q31 from the first constant current source 101 is turned on. The current is supplied to the capacitor C, thereby charging the capacitor C31. As time passes, the voltage of the first node Q31 increases linearly. At a time when the voltage of the first node Q31 becomes higher than the first reference voltage Vr1, the first voltage comparator 105 does this. Will be detected. As a result, the rising edge of the input signal flag in is delayed by the time t1 until the voltage of the first node Q31 reaches the first reference voltage Vr1.

When the input signal (flag in) transitions from the high state to the low state (corresponding to the falling delay time), the second switching means 104 is turned on to form a current path to the ground terminal Vss, so that the capacitor C31 The charged current is discharged to the ground terminal Vss. Therefore, the voltage of the first node Q31 decreases linearly, and the second voltage comparator 106 detects this when it becomes smaller than the second voltage Vr2. Similarly, the falling edge of the input signal flag in is delayed by the time t2 until the voltage of the first node Q31 falls below the second reference voltage Vr2.

In this case, the pulse width of the output delayed output flag out is obtained by subtracting the delay time t1 of the rising edge and the delay time t2 of the falling edge from the pulse width PW of the input signal flag in. It's time. Here, the delay time t1 of the rising edge and the delay time t2 of the falling edge are the current values of the first and second constant current sources 101 and 102, the capacitance of the capacitor C31, and the first and second reference voltages. Determined by the voltage levels of (Vr1 and Vr2). On the other hand, when the first voltage comparator 105 is disabled in the t3 section and the second voltage comparator 106 is disabled in the t4 section, the current consumption can be effectively reduced.

FIG. 4 is a circuit diagram illustrating an embodiment of a delay circuit according to the present invention, which will be schematically described with reference to the timing diagram shown in FIG. 5.

The constant current source 43 has a current mirror having a cascode structure driven in accordance with a power-up signal perup, wherein the reference current is independent of voltage and mainly depends on the value of the resistor R41. In addition, the change in current caused by temperature is also negligibly small. On the other hand, if the channel length of the MOS devices constituting the constant current source 43 is designed to be several times the minimum value allowed in the process, and the symmetrical arrangement and matching of each device is considered, the error due to the process variation will be Almost negligible.

The current switch 44 is a differential current switch, which is configured to charge and discharge charges in the capacitor C41 by a signal in which the output signal of the latch circuit 42 and the output signal of the latch circuit 42 are inverted through the inverter. It is a structure that can suppress the charge redistibution phenomenon appearing at the node Q41. When the first PMOS transistor P41 is turned on, the constant current is supplied to the capacitor C11, and when the first NMOS transistor N41 is turned on, the capacitor C11 discharges electric charges.

The first and second voltage comparators 45 and 46 sense the voltage of the first node Q41 and the first voltage comparator 45 when the voltage of the first node Q41 reaches the first reference voltage Vr1 level. ) Output signal Vo1 goes low. At this time, the first voltage comparator 45 is disabled by the first enable signal EN1 output from the control means 48 so that the output signal Vo1 of the first voltage comparator 45 is again in a high state. do. However, due to the latch circuit 47 consisting of the first and second NAND gates 49 and 50, the delay output signal flag out remains high. On the contrary, when the voltage of the first node Q41 falls below the level of the second reference voltage Vr2, the output signal Vo2 of the second voltage comparator 46 goes low. At this time, the second voltage comparator 46 is disabled by the second enable signal EN2 of the control means 48 so that the output signal Vo2 of the second voltage comparator 46 is precharged to the high state again. . However, the delay output signal flag out is kept high by the latch circuit 47 composed of the first and second NAND gates 49 and 50. As described above, the first and second voltage comparators 45 and 46 have the voltage sensing of t1 and t2 shown in FIG. 3 by the first and second enable signals EN1 and EN2 output from the control means 48. It operates only in the required section, which significantly reduces the current consumption due to the use of a voltage comparator. The DC biasing currents of the first and second voltage comparators 45 and 46 are mirrored from the constant current source 43 to the second and third NMOS transistors N42 and N43 so that they remain constant regardless of the voltage variation of the supply voltage. The bias current flows. The first and second enable signals EN1 and EN2 used as control signals for disabling the first and second voltage comparators 45 and 46 are configured with the following logic, respectively.

EN1 = flag in AND pwrup AND (NOT flag in)

EN2 = (NOT flag in) AND pwrup AND flag out

If the input signal is in a low state, since the output signal of the latch circuit 42 is in a low state, since the first NMOS transistor N41 is turned on and the potential of the first node Q41 is always kept low, the capacitor C41 There is no charge stored. Therefore, the offset at the first node Q41 is zero. The power-up signal pwrup is a signal for properly initializing each node to prevent malfunction of the circuit and is automatically performed after the power supply voltage is applied.

In the circuit of the embodiment of the delay circuit according to the present invention, the delay time is a value of the resistor R41 that determines the size of the constant current source 43 and the reference voltage levels of the first and second reference voltages Vr1 and Vr2. T1 and t2 of FIG. 3, that is, the delay time on the rising edge and the delay time on the falling edge may be adjusted relatively and independently. When the first and second reference voltages Vr1 and Vr2 are fixed and the value of the resistor R41 is changed, the delay times of t1 and t2 are shifted to the same value. If the value of the resistor R41 is fixed and the levels of the first and second reference voltages Vr1 and Vr2 are adjusted, the delay times of t1 and t2 are different from each other and thus can be adjusted independently.

As described above, the present invention has the following effects.

First, since the influence of delay time due to power supply voltage, temperature, process change, etc. is minimized, it is easy to design a semiconductor circuit that operates stably with respect to the external environment.

Second, layout size can be significantly reduced by not using multiple inverter chains and passive components such as resistors and capacitors.

Third, in the delay circuit for having a very large delay time, the slew rate of the pulse is designed to be very gentle, thereby increasing the short circuit current inevitably generated in the CMOS device. In addition, switching occurs as many inverters as used, resulting in a higher dynamic current. However, in the circuit of the present invention, the switching occurs only once in the reference voltage of the voltage comparator and consumes current only when the voltage comparator needs to be operated. Thus, the current consumption is very low compared to the conventional structure.

Claims (6)

A first constant current source for supplying current to the first node, First switching means for driving said first constant current source; A second constant current source for adjusting the potential of the first node; Second switching means for driving the second constant current source; A capacitor for charging and discharging current according to the potential of the first node; A first voltage comparator for determining an output by comparing a potential of the first node and a first reference voltage according to a first enable signal; A second voltage comparator for determining an output by comparing a potential of the first node and a second reference voltage according to a second enable signal; Latch means for outputting a delayed output signal by latching an output signal of the first voltage comparator and an output signal of the second voltage comparator; For outputting a control signal for selectively driving the first and second switching means and a first and second enable signal for enabling the first and second voltage comparators in accordance with an input signal and a delayed output signal. A delay circuit comprising a control means. The delay circuit of claim 1, wherein the first voltage comparator inputs a potential of the first node to a non-inverting input terminal, and inputs and compares the first reference voltage to an inverting input terminal. The delay circuit of claim 1, wherein the second voltage comparator inputs a potential of the first node to an inverting input terminal and compares the second reference voltage to a non-inverting input terminal. 2. The delay circuit of claim 1, wherein the latch circuit comprises first and second NAND gates. 5. The gate driving circuit of claim 1, wherein the first latch circuit comprises: a first NAND gate configured to feedback input an output signal of the first voltage comparator and an output signal of the second NAND gate; And a second NAND gate configured to feedback input the output signal of the second voltage comparator and the output signal of the first NAND gate. 5. The output of the second voltage comparator and the second NAND gate of claim 1, wherein an output of the first voltage comparator and the first NAND gate is a delay path at a rising edge of the input signal. And a delay path at the falling edge of the input signal.