[go: up one dir, main page]

KR20020046433A - Method for fabricating capacitor by Atomic Layer Deposition - Google Patents

Method for fabricating capacitor by Atomic Layer Deposition Download PDF

Info

Publication number
KR20020046433A
KR20020046433A KR1020000076627A KR20000076627A KR20020046433A KR 20020046433 A KR20020046433 A KR 20020046433A KR 1020000076627 A KR1020000076627 A KR 1020000076627A KR 20000076627 A KR20000076627 A KR 20000076627A KR 20020046433 A KR20020046433 A KR 20020046433A
Authority
KR
South Korea
Prior art keywords
capacitor
taon
ammonia
tin
upper electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
KR1020000076627A
Other languages
Korean (ko)
Other versions
KR100384851B1 (en
Inventor
이주완
Original Assignee
박종섭
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 박종섭, 주식회사 하이닉스반도체 filed Critical 박종섭
Priority to KR10-2000-0076627A priority Critical patent/KR100384851B1/en
Publication of KR20020046433A publication Critical patent/KR20020046433A/en
Application granted granted Critical
Publication of KR100384851B1 publication Critical patent/KR100384851B1/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD

Landscapes

  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • General Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 플라즈마 원자층 증착법을 이용하여 TiN막을 상부전극으로 형성하고 암모니아 플라즈마를 이용하여 표면처리를 함으로써 막질 개선과 전기적 특성을 향상시킬 수 있는 캐패시터 제조 방법을 제공하기 위한 것으로서, 본 발명은 캐패시터 제조 방법에 있어서, 소정공정이 완료된 기판 상에 하부전극과 베리어메탈을 적층하는 단계; 상기 베리어메탈 상에 TaON 유전막을 형성하는 단계; 상기 TaON 유전막 상에 원자층 증착법을 이용하여 TiN 상부전극을 증착하는 단계; 및 상기 TiN 상부전극을 암모니아 플라즈마처리하여 Cl기를 제거하는 단계를 포함하여 이루어진다.The present invention is to provide a capacitor manufacturing method that can improve the film quality and electrical properties by forming a TiN film as an upper electrode using the plasma atomic layer deposition method and the surface treatment using ammonia plasma, the present invention provides a capacitor manufacturing A method, comprising: stacking a lower electrode and a barrier metal on a substrate on which a predetermined process is completed; Forming a TaON dielectric layer on the barrier metal; Depositing a TiN upper electrode on the TaON dielectric layer using atomic layer deposition; And removing the Cl group by subjecting the TiN upper electrode to an ammonia plasma treatment.

Description

원자층 증착법에 의한 캐패시터 제조 방법{Method for fabricating capacitor by Atomic Layer Deposition}Method for fabricating capacitors by atomic layer deposition {Method for fabricating capacitor by Atomic Layer Deposition}

본 발명은 반도체소자 제조 방법에 관한 것으로, 더욱 상세하게는 원자층 증착법을 이용하여 캐패시터를 제조하는 방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a capacitor using an atomic layer deposition method.

통상적으로 TaON 캐패시터의 하부전극은 급속열처리(Rapid Thermal Process; RTP)에 의해 질화된 폴리실리콘을 사용하였다.Typically, polysilicon nitrided by a rapid thermal process (RTP) was used as a lower electrode of the TaON capacitor.

한편, 소자가 점차 고 집적화됨에 따라 안정된 소자동작을 위한 셀당 캐패시턴스는 변화가 없는 반면 캐패시터 셀 사이즈는 점점 줄어들게 되어 유효산화막의 두께가 30Å 정도인 폴리실리콘을 하부전극으로 하는 MIS(Metal Insulator Semiconductor) 구조에서의 TaON 캐패시터 구조는 한계에 도달하게 되었다.On the other hand, as devices are increasingly integrated, the capacitance per cell for stable device operation remains unchanged, while the capacitor cell size gradually decreases, so the MIS (Metal Insulator Semiconductor) structure using polysilicon as the bottom electrode having an effective oxide thickness of about 30Å is used. The TaON capacitor structure in U.S. has reached its limit.

이러한 문제를 해결하기 위해 하부메탈전극을 도입해 유효산화막 두께를 낮추는 등의 방법이 시도되고 있다.In order to solve this problem, a method of introducing a lower metal electrode to lower the effective oxide film thickness has been attempted.

한편, MIS 또는 MIM 구조의 캐패시터는 유전막(특히, TaON) 상에 상부메탈전극으로서 TiN 박막을 적용하고 있으나, 종래의 TiN 상부전극 형성 방법에서는 그 하부의 유전막을 손상시키거나 치밀한 구조의 TiN 박막을 형성하지 못하여 높은 누설전류의 원인이 된다.On the other hand, the capacitor of the MIS or MIM structure uses a TiN thin film as an upper metal electrode on a dielectric layer (particularly, TaON). However, in the conventional TiN upper electrode formation method, a TiN thin film having a dense structure or damaging the dielectric layer underneath is applied. It can't be formed and causes high leakage current.

도 1은 종래기술에 따라 형성된 MIM 캐패시터를 나타내는 단면도이다.1 is a cross-sectional view showing a MIM capacitor formed according to the prior art.

이하 도 1을 참조하면, 소정공정이 완료된 기판(10) 상에 폴리실리콘 또는 메탈의 하부전극(11)을 증착하고 이후 베리어메탈인 TiN/Ti막(12)을 증착한다. 계속해서 상기 TiN/Ti막(12) 상에 유전막인 TaON막(13)을 증착한 후 상부전극인 TiN막(14)을 증착함으로써 적층구조의 캐패시터가 완성된다.Referring to FIG. 1, a lower electrode 11 of polysilicon or metal is deposited on a substrate 10 on which a predetermined process is completed, and then a TiN / Ti film 12, which is a barrier metal, is deposited. Subsequently, a TaON film 13 as a dielectric film is deposited on the TiN / Ti film 12, and then a TiN film 14 as an upper electrode is deposited to complete a capacitor having a laminated structure.

TiN막은 TiCl4를 소스로 하는 화학기상증착법(Chemical Vapor Deposition; CVD)이 적용되고 있다.As the TiN film, chemical vapor deposition (CVD) using TiCl 4 as a source is applied.

한편, TiN 증착은 가능한 낮은 온도에서 실시하여야 캐패시터의 전기적 특성이 양호하다. 하지만, 소스물질로 TiCl4를 이용하고 있어 낮은 온도에서 TiN을 증착할 경우 다량의 Cl기가 TiN 박막 내에 잔류하게 되고 이로 인해 하부의 TaON이 데미지를 받을 수 있을 뿐만아니라, 낮은 온도에서 상기 TiN을 증착하기 때문에 치밀한 구조를 이루지 못해 TaON막과 TiN막 계면에 환원된 금속계의 Ta가 존재하게 되어 높은 누설전류의 원인이 될 수 있다. 결국, 캐패시터의 전기적 특성이 열화된다.On the other hand, TiN deposition should be carried out at the lowest possible temperature to have good electrical characteristics of the capacitor. However, since TiCl 4 is used as the source material, when TiN is deposited at a low temperature, a large amount of Cl groups remain in the TiN thin film, thereby not only damaging the TaON below but also depositing TiN at a low temperature. Therefore, the metal Ta is reduced at the interface between the TaON film and the TiN film due to the incomplete structure, which may cause a high leakage current. As a result, the electrical characteristics of the capacitor deteriorate.

또한, 캐패시터의 높이가 높아짐에따라 화학기상증착법(CVD)에 의해 상부메탈전극을 증착할 경우 단착 피복성에도 문제가 발생하게 된다.In addition, as the height of the capacitor increases, a problem occurs in the adhesion of the upper metal electrode when the upper metal electrode is deposited by chemical vapor deposition (CVD).

본 발명은 상기와 같은 종래 기술의 문제점을 해결하기 위한 것으로서, 원자층 증착법과 암모니아 플라즈마 표면처리를 이용하여 TiN막을 형성함으로써 열처리 경비를 줄이고 막질 개선과 전기적 특성의 향상시킬 수 있는 캐패시터 제조 방법을 제공하는데 그 목적이 있다.The present invention is to solve the problems of the prior art as described above, by providing a TiN film using atomic layer deposition and ammonia plasma surface treatment to provide a capacitor manufacturing method that can reduce the heat treatment cost, improve the film quality and electrical properties. Its purpose is to.

도 1은 종래기술에 따라 형성된 MIM 캐패시터를 나타내는 단면도,1 is a cross-sectional view showing a MIM capacitor formed according to the prior art;

도 2a 내지 2d는 본 발명의 실시예에 따른 원자층 증착법에 의한 캐패시터 제조 공정을 나타내는 단면도,2A to 2D are cross-sectional views illustrating a capacitor manufacturing process by atomic layer deposition according to an embodiment of the present invention;

* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

10, 20 : 기판10, 20: substrate

11, 21 : 하부전극11, 21: lower electrode

12, 22 : TiN/Ti막12, 22: TiN / Ti film

13, 23 : TaON 유전막13, 23: TaON dielectric film

14, 24 : TiN 상부전극14, 24: TiN upper electrode

상기 목적을 달성하기 위하여 본 발명은 반도체소자 제조 방법에 있어서, 소정공정이 완료된 기판 상에 하부전극과 베리어메탈을 적층하는 단계; 상기 베리어메탈 상에 TaON 유전막을 형성하는 단계; 상기 TaON 유전막 상에 원자층 증착법을 이용하여 TiN 상부전극을 증착하는 단계; 및 상기 TiN 상부전극을 암모니아 플라즈마처리하여 Cl기를 제거하는 단계를 포함한다.In order to achieve the above object, the present invention provides a method of manufacturing a semiconductor device, comprising: stacking a lower electrode and a barrier metal on a substrate on which a predetermined process is completed; Forming a TaON dielectric layer on the barrier metal; Depositing a TiN upper electrode on the TaON dielectric layer using atomic layer deposition; And removing the Cl group by subjecting the TiN upper electrode to an ammonia plasma treatment.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부한 도 2a 내지 도 2d를 참조하여 설명한다.Hereinafter, in order to explain in detail enough to enable those skilled in the art to easily carry out the technical idea of the present invention, refer to FIGS. 2A to 2D attached to the most preferred embodiment of the present invention. Will be explained.

도 2a 내지 도 2d는 본 발명의 캐패시터 제조 공정을 나타내는 단면도이다.2A to 2D are cross-sectional views showing a capacitor manufacturing process of the present invention.

먼저, 도 2a에 도시된 바와 같이 소정공정이 완료된 기판(20) 상에 하부전극(21)을 형성하고 베리어메탈인 TiN/Ti막(22)을 증착한다. 여기서, 상기 TiN/Ti막(22)은 Ti를 50Å 내지 300Å, TiN은 100Å 내지 1000Å의 두께가 되도록 한다. 또한, 상기 하부전극(21) 물질로는 Ru, Ir, Pt 또는 폴리실리콘 등을 이용한다.First, as shown in FIG. 2A, a lower electrode 21 is formed on a substrate 20 on which a predetermined process is completed, and a TiN / Ti film 22, which is a barrier metal, is deposited. Here, the TiN / Ti film 22 has a thickness of 50 kPa to 300 kPa and TiN of 100 kPa to 1000 kPa. In addition, as the material of the lower electrode 21, Ru, Ir, Pt, or polysilicon is used.

다음으로 도 2b에 도시된 것처럼 상기 TiN/Ti막(22) 상에 유전체로서 TaON막(23)을 형성한다.Next, as shown in FIG. 2B, a TaON film 23 is formed on the TiN / Ti film 22 as a dielectric.

TaON막(23) 형성 공정을 구체적으로 살펴보면, 170℃ 내지 190℃의 기상상태로 유지되는 탄탈륨 에칠레이트(Ta(OC2H5)5)를 소스가스로 하여 300℃ 내지 400℃로 웨이퍼 온도를 유지하며 0.1Torr 내지 2Torr의 압력 하에서 10sccm 내지 1000sccm의 암모니아를 반응가스로 하여 TaON을 증착하고, 산소(O2)와 질소(N2)를 1 : 1 ∼ 3의 비율로 하는 플라즈마처리 또는 자외선 오존 처리(Ultra Violet O3; UV/O3)를 300℃ 내지 500℃의 온도 하에서 1분 내지 5분 동안 실시한다. 다음으로 1 : 1 ∼ 3 비율의 산소와 질소를 이용하여 500℃ 내지 650℃의 온도 하에서 30초 내지 60초 동안 급속 열산화(Rapid Thermal Oxidation; RTO)를 실시한다.Looking at the TaON film forming process in detail, using a tantalum acrylate (Ta (OC 2 H 5 ) 5 ) maintained in the gas phase of 170 ℃ to 190 ℃ as a source gas to the wafer temperature from 300 ℃ to 400 ℃ TaON is deposited using 10 sccm to 1000 sccm of ammonia as a reaction gas under a pressure of 0.1 Torr to 2 Torr, and plasma treatment or ultraviolet ozone with oxygen (O 2 ) and nitrogen (N 2 ) in a ratio of 1: 1 to 3. The treatment (Ultra Violet O 3 ; UV / O 3 ) is carried out at a temperature of 300 ° C. to 500 ° C. for 1 to 5 minutes. Next, Rapid Thermal Oxidation (RTO) is performed for 30 seconds to 60 seconds at a temperature of 500 ° C. to 650 ° C. using oxygen and nitrogen at a ratio of 1: 1 to 3.

다음으로 도 2c에 도시된 바와 같이 상기 TaON막(23) 상에 원자층 증착법(Atomic Layer Deposition; ALD)을 이용하여 TiN막(24)을 증착한다.Next, as illustrated in FIG. 2C, a TiN film 24 is deposited on the TaON film 23 using atomic layer deposition (ALD).

구체적으로, 상기 원자층 증착법(ALD)은 소스가스인 TiCl4를 흐르게 한 뒤 퍼지(Purge)하고, 다시 암모니아를 흐르게 한 뒤 퍼지한다. 이때, 소정의 막을 형성하기 위하여 상기의 공정을 반복하여 실시하며, 퍼지가스는 질소를 이용한다. 또한, 상기 TiCl4와 암모니아(NH3)를 0.1초 내지 10초 동안 흐르게 하며 200℃ 내지 400℃의 온도 및 100mTorr 내지 10Torr의 압력 하에서 실시한다.Specifically, the atomic layer deposition method (ALD) is a purge (Purge) after flowing the source gas TiCl 4 , and again purged after flowing ammonia. At this time, the above process is repeated to form a predetermined film, and the purge gas uses nitrogen. In addition, the TiCl 4 and ammonia (NH 3 ) flowing for 0.1 seconds to 10 seconds and is carried out under a temperature of 200 ℃ to 400 ℃ and a pressure of 100 mTorr to 10 Torr.

다음으로 도 2d에 도시된 바와 같이, 상기 TiN막(24)을 암모니아 플라즈마를 야기시켜 표면처리하여 잔류 Cl기를 제거한다. 여기서, 상기 표면처리 공정은 100sccm 내지 1000sccm의 암모니아를 이용하여 30W 내지 1000W의 RF 파워 및 0.1Torr 내지 2Torr의 압력 하에서 5초 내지 100초 동안 실시한다.Next, as shown in FIG. 2D, the TiN film 24 is surface-treated by causing an ammonia plasma to remove residual Cl groups. Here, the surface treatment process is carried out for 5 seconds to 100 seconds using RF power of 30W to 1000W and pressure of 0.1 Torr to 2 Torr using 100sccm to 1000sccm of ammonia.

상기 TiN막 증착 공정과 암모니아 플라즈마처리는 동일 챔버 내에서 인시튜(In situ) 공정으로 실시하는 것이 바람직하다.The TiN film deposition process and the ammonia plasma treatment are preferably performed in an in situ process in the same chamber.

전술한 것처럼 본 발명의 반도체소자 제조 방법은 원자층 증착법을 이용하여상부전극인 TiN막 형성한 후 암모니아 플라즈마로 표면처리함으로써, Cl기를 제거하여 TaON막(23)의 데미지를 줄여 막질을 개선할 수 있으며, 치밀한 구조의 TiN 박막을 형성하여 전기적 특성을 향상시킬 수 있음을 실시예를 통해 알아보았다.As described above, the semiconductor device manufacturing method of the present invention can improve the film quality by reducing the damage of the TaON film 23 by removing the Cl group by forming a TiN film as an upper electrode by using an atomic layer deposition method and then surface treating with ammonia plasma. In addition, it was found through the embodiment that the electrical properties can be improved by forming a thin TiN thin film structure.

또한, 원자층 증착법을 이용하므로 TiN의 단차피복을 개선한다.In addition, the step coating of TiN is improved by using the atomic layer deposition method.

본 발명의 캐패시터 제조 방법은 원통형 또는 오목형 중 어느 하나의 캐패시터를 적용 가능하며, HSG(Hemi Spherical Grain) 폴리실리콘을 이용하는 MIS 구조의 캐패시터에도 적용이 가능하다.The capacitor manufacturing method of the present invention can be applied to any one of a cylindrical or concave type, and can be applied to a capacitor of the MIS structure using HSG (Hemi Spherical Grain) polysilicon.

이상에서 본 발명의 기술 사상을 바람직한 실시예에 따라 구체적으로 기술하였으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical spirit of the present invention has been described in detail according to a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

상기와 같이 본 발명은 반도체소자 제조 방법에 있어서, TaON 유전막의 데미지를 줄이고 TiN막의 치밀도를 높여 캐패시터의 전기적 특성을 향상시킬 수 있다.As described above, in the method of manufacturing a semiconductor device, the electrical properties of the capacitor can be improved by reducing the damage of the TaON dielectric film and increasing the density of the TiN film.

또한, TiN막의 단차피복성을 개선할 수 있다.In addition, the step coverage of the TiN film can be improved.

Claims (16)

반도체소자의 캐패시터 제조 방법에 있어서,In the capacitor manufacturing method of a semiconductor device, 소정공정이 완료된 기판 상에 하부전극과 베리어메탈을 적층하는 단계;Stacking a lower electrode and a barrier metal on a substrate on which a predetermined process is completed; 상기 베리어메탈 상에 TaON 유전막을 형성하는 단계;Forming a TaON dielectric layer on the barrier metal; 상기 TaON 유전막 상에 원자층 증착법을 이용하여 TiN 상부전극을 증착하는 단계; 및Depositing a TiN upper electrode on the TaON dielectric layer using atomic layer deposition; And 상기 TiN 상부전극을 암모니아 플라즈마처리하여 Cl기를 제거하는 단계Removing the Cl group by subjecting the TiN upper electrode to an ammonia plasma treatment 를 포함하여 이루어짐을 특징으로 하는 캐패시터 제조 방법.Capacitor manufacturing method characterized in that it comprises a. 제 1 항에 있어서,The method of claim 1, 상기 TiN 상부전극의 증착은,Deposition of the TiN upper electrode, 소스가스인 TiCl4를 흐르게 한 뒤 퍼지하고, 다시 암모니아를 흐르게 한 뒤 퍼지하는 것을 반복 실시하여 이루어지는 것을 특징으로 하는 캐패시터 제조 방법.A method for producing a capacitor, characterized in that it is made by repeatedly purging after flowing TiCl 4 which is a source gas and flowing ammonia again. 제 2 항에 있어서,The method of claim 2, 상기 TiN 상부전극의 증착은,Deposition of the TiN upper electrode, 상기 TiCl4와 암모니아를 각각 0.1초 내지 10초 동안 흐르게 하는 것을 특징으로 하는 캐패시터 제조 방법.Capacitor manufacturing method characterized in that for flowing the TiCl 4 and ammonia for 0.1 to 10 seconds respectively. 제 2 항에 있어서,The method of claim 2, 상기 TiN 상부전극의 증착은,Deposition of the TiN upper electrode, 200℃ 내지 400℃의 온도 및 100mTorr 내지 10Torr의 압력 하에서 실시하는 것을 특징으로 하는 캐패시터 제조 방법.A method for producing a capacitor, characterized in that it is carried out at a temperature of 200 ℃ to 400 ℃ and a pressure of 100 mTorr to 10 Torr. 제 1 항에 있어서,The method of claim 1, 상기 암모니아 플라즈마처리에서,In the ammonia plasma treatment, 100sccm 내지 1000sccm의 암모니아를 사용하는 것을 특징으로 하는 캐패시터 제조 방법.A method for producing a capacitor, characterized by using ammonia of 100 sccm to 1000 sccm. 제 1 항에 있어서,The method of claim 1, 상기 암모니아플라즈마처리는,The ammonia plasma treatment, 30W 내지 1000W의 RF 파워 하에서 실시하는 것을 특징으로 하는 캐패시터 제조 방법.Capacitor manufacturing method characterized in that carried out under RF power of 30W to 1000W. 제 1 항에 있어서,The method of claim 1, 상기 암모니아 플라즈마처리는,The ammonia plasma treatment, 0.1Torr 내지 2Torr의 압력 하에서 실시하는 것을 특징으로 하는 캐패시터 제조 방법.Capacitor manufacturing method characterized in that carried out under a pressure of 0.1 Torr to 2 Torr. 제 1 항에 있어서,The method of claim 1, 상기 암모니아플라즈마처리는,The ammonia plasma treatment, 5초 내지 100초 동안 실시하는 것을 특징으로 하는 캐패시터 제조 방법.Capacitor manufacturing method characterized in that carried out for 5 seconds to 100 seconds. 제 1 항에 있어서,The method of claim 1, 상기 암모니아플라즈마처리는,The ammonia plasma treatment, 상기 TiN 상부전극 증착 챔버 내에서 인시튜로 실시하는 것을 특징으로 하는 캐패시터 제조 방법.Capacitor manufacturing method characterized in that performed in-situ in the TiN upper electrode deposition chamber. 제 1 항에 있어서,The method of claim 1, 상기 베리어메탈은,The barrier metal, 50Å 내지 300Å의 Ti와 100Å 내지 1000Å의 TiN을 적층하여 형성하는 것을 특징으로 하는 캐패시터 제조 방법.A capacitor manufacturing method characterized by laminating 50 kV to 300 kV Ti and 100 kV to 1000 kV TiN. 제 1 항에 있어서,The method of claim 1, 상기 TaON 유전막 형성 단계는,The TaON dielectric film forming step, TaON을 증착하는 단계;Depositing TaON; 상기 TaON을 질소와 산소의 플라즈마처리 또는 자외선오존처리하는 단계; 및Plasma or ultraviolet ozone treatment of nitrogen and oxygen in the TaON; And 상기 TaON을 후속 열처리하는 단계Subsequent heat treatment of the TaON 를 포함하여 이루어짐을 특징으로 하는 캐패시터 제조 방법.Capacitor manufacturing method characterized in that it comprises a. 제 11 항에 있어서,The method of claim 11, 상기 TaON 증착은,The TaON deposition is, 탄탈륨 에칠레이트를 소스가스로 하고, 암모니아를 반응가스로 하여, 300℃ 내지 400℃의 웨이퍼 온도 및 0.1Torr 내지 2Torr의 압력 하에서 실시하는 것을 특징으로 하는 캐패시터 제조 방법.A method for producing a capacitor, comprising tantalum ethylene as a source gas and ammonia as a reaction gas, under a wafer temperature of 300 ° C. to 400 ° C. and a pressure of 0.1 Torr to 2 Torr. 제 11 항에 있어서,The method of claim 11, 상기 질소와 산소의 플라즈마처리 또는 자외선오존처리는,The plasma treatment or ultraviolet ozone treatment of nitrogen and oxygen, 300℃ 내지 500℃의 온도 하에서 1분 내지 5분 동안 실시하는 것을 특징으로 하는 캐패시터 제조 방법.Method for producing a capacitor, characterized in that carried out for 1 to 5 minutes at a temperature of 300 ℃ to 500 ℃. 제 11 항에 있어서,The method of claim 11, 상기 후속 열처리는,The subsequent heat treatment, 1 : 1 내지 1 : 3의 비율의 산소와 질소를 이용하는 급속열산화를 통하여 500℃ 내지 650℃의 온도 하에서 30초 내지 60초 동안 실시하는 것을 특징으로 하는 캐패시터 제조 방법.A method for producing a capacitor, characterized in that carried out for 30 seconds to 60 seconds at a temperature of 500 ° C to 650 ° C through rapid thermal oxidation using oxygen and nitrogen in a ratio of 1: 1 to 1: 3. 제 1 항에 있어서,The method of claim 1, 상기 하부전극의 물질로,As the material of the lower electrode, Ru, Ir, Pt 또는 폴리실리콘 중 어느 하나를 이용하는 것을 특징으로 하는 캐패시터 제조 방법.A method for producing a capacitor, comprising any one of Ru, Ir, Pt or polysilicon. 제 1 항에 있어서,The method of claim 1, 상기 캐패시터는 원통형 또는 오목형인 것을 특징으로 하는 캐패시터 제조 방법.The capacitor manufacturing method of the capacitor, characterized in that the cylindrical or concave.
KR10-2000-0076627A 2000-12-14 2000-12-14 Method for fabricating capacitor by Atomic Layer Deposition Expired - Fee Related KR100384851B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR10-2000-0076627A KR100384851B1 (en) 2000-12-14 2000-12-14 Method for fabricating capacitor by Atomic Layer Deposition

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR10-2000-0076627A KR100384851B1 (en) 2000-12-14 2000-12-14 Method for fabricating capacitor by Atomic Layer Deposition

Publications (2)

Publication Number Publication Date
KR20020046433A true KR20020046433A (en) 2002-06-21
KR100384851B1 KR100384851B1 (en) 2003-05-22

Family

ID=27681950

Family Applications (1)

Application Number Title Priority Date Filing Date
KR10-2000-0076627A Expired - Fee Related KR100384851B1 (en) 2000-12-14 2000-12-14 Method for fabricating capacitor by Atomic Layer Deposition

Country Status (1)

Country Link
KR (1) KR100384851B1 (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7053432B2 (en) * 2000-08-31 2006-05-30 Micron Technology, Inc. Enhanced surface area capacitor fabrication methods
US7105065B2 (en) 2002-04-25 2006-09-12 Micron Technology, Inc. Metal layer forming methods and capacitor electrode forming methods
US7112503B1 (en) 2000-08-31 2006-09-26 Micron Technology, Inc. Enhanced surface area capacitor fabrication methods
US7217615B1 (en) 2000-08-31 2007-05-15 Micron Technology, Inc. Capacitor fabrication methods including forming a conductive layer
KR100763506B1 (en) * 2005-06-27 2007-10-05 삼성전자주식회사 Capacitor manufacturing method
US7440255B2 (en) 2003-07-21 2008-10-21 Micron Technology, Inc. Capacitor constructions and methods of forming
KR20130093569A (en) * 2012-02-14 2013-08-22 노벨러스 시스템즈, 인코포레이티드 Precursors for plasma activated conformal film deposition
CN110797435A (en) * 2019-10-16 2020-02-14 暨南大学 A composition-tunable inorganic perovskite photoelectric thin film and its low-temperature preparation method and device application
CN115410902A (en) * 2022-09-14 2022-11-29 复旦大学 Method for improving ferroelectric MOS capacitive performance

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100585002B1 (en) 2004-05-31 2006-05-29 주식회사 하이닉스반도체 Capacitor Manufacturing Method of Semiconductor Device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010083697A (en) * 2000-02-21 2001-09-01 윤종용 Formation method of semiconductor capacitor electrode

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7053432B2 (en) * 2000-08-31 2006-05-30 Micron Technology, Inc. Enhanced surface area capacitor fabrication methods
US7112503B1 (en) 2000-08-31 2006-09-26 Micron Technology, Inc. Enhanced surface area capacitor fabrication methods
US7217615B1 (en) 2000-08-31 2007-05-15 Micron Technology, Inc. Capacitor fabrication methods including forming a conductive layer
US7288808B2 (en) 2000-08-31 2007-10-30 Micron Technology, Inc. Capacitor constructions with enhanced surface area
US7105065B2 (en) 2002-04-25 2006-09-12 Micron Technology, Inc. Metal layer forming methods and capacitor electrode forming methods
US7440255B2 (en) 2003-07-21 2008-10-21 Micron Technology, Inc. Capacitor constructions and methods of forming
KR100763506B1 (en) * 2005-06-27 2007-10-05 삼성전자주식회사 Capacitor manufacturing method
KR20130093569A (en) * 2012-02-14 2013-08-22 노벨러스 시스템즈, 인코포레이티드 Precursors for plasma activated conformal film deposition
KR20190126256A (en) * 2012-02-14 2019-11-11 노벨러스 시스템즈, 인코포레이티드 Precursors for plasma activated conformal film deposition
CN110797435A (en) * 2019-10-16 2020-02-14 暨南大学 A composition-tunable inorganic perovskite photoelectric thin film and its low-temperature preparation method and device application
CN115410902A (en) * 2022-09-14 2022-11-29 复旦大学 Method for improving ferroelectric MOS capacitive performance

Also Published As

Publication number Publication date
KR100384851B1 (en) 2003-05-22

Similar Documents

Publication Publication Date Title
KR100622609B1 (en) Thin Film Formation Method
KR100384850B1 (en) Method for forming Ta2O5 dielectric layer
KR100363081B1 (en) Thin film formation apparatus
KR100390831B1 (en) Method for forming Ta2O5 dielectric layer by Plasma Enhanced Atomic Layer Deposition
US6673668B2 (en) Method of forming capacitor of a semiconductor memory device
KR100507860B1 (en) Capacitor having oxidation barrier and method for fabricating the same
KR100670747B1 (en) Capacitor Manufacturing Method Of Semiconductor Device
KR100384851B1 (en) Method for fabricating capacitor by Atomic Layer Deposition
US6635524B2 (en) Method for fabricating capacitor of semiconductor memory device
KR100655140B1 (en) Capacitor and manufacturing method thereof
KR20020048617A (en) Method for forming ta2o5 dielectric layer by plasma enhanced atomic layer deposition
KR20030002905A (en) Method for fabricating capacitor
KR100772101B1 (en) Capacitor Formation Method of Semiconductor Device
KR100382742B1 (en) Method for forming capacitor of semiconductor device
KR20010088207A (en) Method of forming composite dielectric film of tantalum oxide and titanium oxide
KR100780631B1 (en) Deposition method of titanium oxide film and manufacturing method of capacitor using same
KR100809336B1 (en) Manufacturing Method of Memory Device
KR100422596B1 (en) Method for fabricating capacitor
US20070264770A1 (en) Capacitor forming method
KR100476374B1 (en) Method for fabricating semiconductor device
KR100761406B1 (en) Method for manufacturing a capacitor having a tantalum oxide film as a dielectric film
KR100382611B1 (en) Method for forming of capacitor the cell used high-integrated DRAM
KR100414868B1 (en) Method for fabricating capacitor
KR100404481B1 (en) Method for manufacturing capacitor semiconductor device
KR100772100B1 (en) Capacitor Formation Method of Semiconductor Device

Legal Events

Date Code Title Description
A201 Request for examination
PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

PN2301 Change of applicant

St.27 status event code: A-3-3-R10-R13-asn-PN2301

St.27 status event code: A-3-3-R10-R11-asn-PN2301

PN2301 Change of applicant

St.27 status event code: A-3-3-R10-R13-asn-PN2301

St.27 status event code: A-3-3-R10-R11-asn-PN2301

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U11-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 6

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 7

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 8

FPAY Annual fee payment

Payment date: 20110429

Year of fee payment: 9

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 9

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-PN2301

St.27 status event code: A-5-5-R10-R11-asn-PN2301

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20120510

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-PN2301

St.27 status event code: A-5-5-R10-R11-asn-PN2301

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20120510

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-PN2301

St.27 status event code: A-5-5-R10-R11-asn-PN2301

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000