KR20020042903A - A method and a device of clock signal phase controlling for exchange - Google Patents

Abstract

The present invention relates to synchronizing a phase of a clock signal when a trunk matching board of an exchange is switched, the analog PEL generating and outputting a clock signal synchronized with an input system clock signal; A delay unit for delaying the clock signal output from PEL in multiple stages and outputting the clock signal delayed for each stage; A latch unit receiving a clock signal delayed in steps from a delay unit and a clock signal output from the redundant board, and checking a phase difference between the clock output from the PEL and the clock signal output from the redundant board; A phase inversion checking unit configured to receive an output signal of the latch unit and a clock signal of the duplex board, and to check whether the phase of the clock signal output from the PEL and the clock signal output from the duplex board is the same or inverted; Phase coincidence checking unit which checks the phases of the clock signal output from the PLL and the clock signal output from the redundant board and the phases of the delayed signals most similarly among the delay stages output from the delay unit. Wow; And a clock selector configured to receive a signal output from a delay unit and a phase match checker, and to select and output a clock signal output from the redundant board at a position coinciding with the control signal.

Description

Clock signal phase control device of switch and its method {A METHOD AND A DEVICE OF CLOCK SIGNAL PHASE CONTROLLING FOR EXCHANGE}

The present invention relates to the synchronization of the phase of the clock signal in the trunk matching board of the STM (Synchronous Transmission Module) class 1 switch, in particular, when the redundant trunk matching board is switched, the phase of each clock signal generated It is about controlling to transfer at a time.

Trunk matching block or board of STM-1 class exchange that transmits data signal by synchronous transmission at high speed of 155 Mbps is 8 from T (Time) switch connecting path. A system clock of MHz is applied, and an internal clock signal of 19.44 MHz synchronized with the system clock is generated and used.

Trunk matching boards of STM-1 class exchanges are redundant for switching in case of a trouble in the operating board, and each board generates clock signals and transmits each other to the redundant counterpart board. Thus, when switched, each board selects and uses one clock signal from its own clock and the clock applied from the redundant board.

The clock signal output from each trunk matching board as described above may have the same frequency but have a different phase. In the state where the phase difference is as described above, the clock signal is converted into a clock signal of a redundant board. In the case of switching, an error occurs in a data signal that is matched and transmitted from the trunk line.

Hereinafter, a clock signal duplication apparatus of a trunk trunk matching board according to the prior art will be described with reference to the accompanying drawings.

Attached to explain the prior art, Figure 1 is a functional block diagram of the clock signal redundancy device of the switch trunk matching board according to the prior art.

Referring to FIG. 1, the clock signal redundancy device of the trunk trunk matching board 10 according to the prior art receives a system clock Tclk of 8 MHz from a T switch of an STM-1 switch and receives a clock of 19.44 MHz. An analog PLL (APLL) 12 which generates and outputs a signal Sclk,

A 19.44 MHz clock signal (Sclk) input from the APLL 12 and a 19.44 MHz clock signal (Oclk) input from another redundant trunk matching board 20 are simultaneously input, and a control signal is applied from the controller. And a clock selector 14 which selects one clock signal by (Act: Act / Standby signal) and outputs the selected clock signal (Selclock).

Hereinafter, with reference to the accompanying drawings, a clock signal duplication apparatus of the trunk matching board of the STM-1 class switch according to the related art having the above-described configuration will be described in detail.

A system clock Tclk of 8 MHz is input from the trunk matching board 10 having the above configuration from a T-switch that sets a path of the exchange through time division switching.

The trunk matching board 10 applies an 8 MHz system clock (Tclk) signal input from a T-switch to an analog (A) analog PLL 12, which is relatively inexpensive, and the APLL 12 A 19.44 MHz clock signal Sclk, which is synchronized with the system clock Tclk, is generated and output.

The clock signal Sclk output from the APLL 12 is outputted to the redundant trunk matching board 20 and simultaneously to the clock selector 14.

The duplicated trunk matching board 20 generates and outputs a clock signal Octl of 19.44 MHz by the same configuration and operation as that of the trunk matching board 10, and simultaneously outputs the same to the clock selecting unit 14.

The clock selector 14 receives both a clock signal Sclk applied from the APLL 12 and a clock signal Oklk output from the redundant trunk matching board 20, and is controlled from the corresponding controller. One clock signal is selected and output (Selclock) by the signal Act.

The clock signals output from the trunk matching boards 10 and 20 according to the prior art having the above-described configuration have the same frequency, but may have a difference in phase, and as described above, a difference in phase. If a clock signal having a switch is selected by the control signal Act signal, a data error such as a frame synchronization error occurs in a high speed STM-1 signal processed by the trunk matching board.

If an error occurs in the data transmitted due to the phase difference of the clock signal as described above, an error occurs in the data transmitted by the subscriber subscribed to the exchange, and the reliability of the system is deteriorated.

According to the present invention, in the trunk matching board of the STM-1 class switch, the phases of the clock signals output from the two redundant trunk matching boards are matched so that the phase difference does not occur in the clock signal when switching. It is therefore an object of the present invention to provide an apparatus and a method for controlling a phase of a clock signal of an exchange such that an error does not occur in data.

In order to achieve the above object, the present invention provides a clock signal selection apparatus of a redundant trunk trunk matching board, comprising: an analog PEL for generating and outputting a clock signal synchronized with an input system clock signal; A delay unit for delaying the clock signal output from the PEL in multiple stages and outputting the clock signal delayed in each stage; A latch unit configured to receive a clock signal delayed step by step from the delay unit and a clock signal output from the redundant board, and to check a phase difference between the clock output from the PEL and the clock signal output from the redundant board; A phase inversion checking unit receiving the output signal of the latch unit and the clock signal of the redundant board, and checking whether the phase of the clock signal output from the PEL and the clock signal output from the redundant board is the same or inverted; A phase for confirming that the phase of the clock signal outputted from the latching unit after receiving the signal outputted from the latch unit and the clock signal outputted from the redundant board coincide most closely among the respective delay stages outputted from the delay unit. A matching confirmation unit; And a clock selector configured to receive the signals output from the delay unit and the phase coincidence checker, and to select and output a clock signal output from the redundant board at a position coinciding with the control signal.

In addition, the present invention, the act of determining whether the trunk matching board currently operating by the control unit of the switch is operating normally; A phase checking step of determining whether the trunk matching board currently operating in the act process is identical to a signal output from the first flip-flop and a signal output from the second flip-flop in the latch unit; A phase coincidence step of determining whether there is an identical value by reading all outputs of the first exclusive or gate and all outputs of the second exclusive or gate when the phase matching process is not the same; If there is a same value in the phase matching process, there is also a feature consisting of a selection process for checking the position of the step and selecting and outputting the clock.

1 is a functional block diagram of a clock signal redundancy device of a trunk trunk matching board according to the prior art;

2 is a functional configuration diagram of a clock signal phase control apparatus of an exchange according to the present invention;

3 is a detailed functional block diagram of a delay unit according to the present invention;

4 is a detailed functional block diagram of a latch unit according to the present invention;

5 is a detailed functional block diagram of a phase inversion confirming unit according to the present invention;

6 is a detailed functional block diagram of a phase matching unit according to the present invention;

7 is a state diagram of input and output signals of a clock selector according to the present invention;

8 is a timing diagram of a clock signal according to the present invention;

9 is a flowchart of a clock signal phase control method according to the present invention.

** Explanation of symbols on the main parts of the drawing **

10,20,100,200: Trunk matching board 12,110: Analog PLL

14, 160: clock selector 120: delay unit

121, 122, 123, 124, 125: Buffer 130: Latch

141 ~ 146,251 ~ 255,351 ~ 355: Exclusive Or Gate

140: phase inversion check unit 150: phase match check unit

231 to 236,331 to 336: flip-flop 300: control unit

451 ~ 455: And Gate

Hereinafter, an output signal phase control apparatus and method thereof of an exchange according to the present invention will be described with reference to the accompanying drawings.

2 is a functional block diagram of a clock signal phase control apparatus of an exchange according to the present invention, FIG. 3 is a detailed functional block diagram of a delay unit according to the present invention, and FIG. Fig. 5 is a detailed functional block diagram of a latch unit according to the present invention, and Fig. 5 is a detailed functional block diagram of a phase inversion confirming unit according to the present invention. 7 is a state diagram of the input / output signal of the clock selection unit according to the present invention, FIG. 8 is a timing diagram of the clock signal according to the present invention, and FIG. 9 is a flowchart of a method of controlling the phase of the clock signal according to the present invention.

2 to 7, the apparatus for controlling a clock signal phase of an exchange according to the present invention receives an 8 MHz system clock signal output from a T-switching unit of an exchange and inputs the system clock signal to the system clock signal. An analog phase locked loop (APLL) 110 for generating and outputting a synchronized 19.44 MHz clock signal;

Receives a 19.44 MHz clock signal output from the analog PLL 110 and delays it in multiple stages, and outputs the delayed clock signals Sclk, Sclkd1, Sclkd2, Sclkd3, Sclkd4, and Sclkd5 respectively. As an example, a delay unit 120 having first to fifth buffers 121 to 125 connected in series with a delay time of about 5 ns, respectively,

Input the clock signals Sclk, Sclkd1, Sclkd2, Sclkd3, Sclkd4, Sclkd5, which are delayed and output from the delay unit 120, and the 19.44 MHz clock signal Oclk output from the redundant trunk matching board 200. The delay unit 120 by checking a phase difference between the clock signal Sclk output from the analog PEL 110 and the clock signal Oclk output from the duplex board 200. Receive clock signals Sclk, Sclkd1, Sclkd2, Sclkd3, Sclkd4, and Sclkd5, respectively, as clock signals clk, and output clock signals Oklk output from the duplex board 200, respectively. A first flip-flop unit 230 including a plurality of flip-flops (FF) 231, 232, 233, 234, 235, and 236 that are inputted as a data signal data; Clock signals Sclk, Sclkd1, Sclkd2, Sclkd3, Sclkd4, and Sclkd5, which are delayed and output from the delay unit 120 step by step, are respectively input as data signals, and the clock signals output from the redundant board 200 are provided. A latch including a second flip-flop portion 330 including a plurality of flip-flops (FF) 331, 332, 333, 334, 335, and 336, each of which receives an input of an occlk as a clock signal clk. (Latch) unit 130,

The analog clock 220 is received by the clock signals Sclk, Sclkd1, Sclkd2, Sclkd3, Sclkd4, Sclkd5, which are delayed from the latch unit 130, and the clock signal Oklk of the redundant board 200, The latch is checked by checking whether the phase (Phase) of the clock signal (Sclk) output from the clock signal and the clock signal (Oclk) output from the duplex board (200) is the same (0 degrees) or inverted (180 degrees). The clock signals Sclk, Sclkd1, Sclkd2, Sclkd3, Sclkd4, and Sclkd5, which are output from the first flip-flop 230 of the unit 130 and delayed step by step, are respectively input to one input terminal and simultaneously output from the redundant board 200. A plurality of exclusive or gates 141, 142, 143, 144, 145, and 146 which receive a clock signal Oklk through the other input terminal and perform an exclusive OR operation, respectively, and output the exclusive OR gate. Output signal of (141, 142, 143, 144, 145, 146) Soclk, Soclk1, Soclk2, Soclk3, Soclk4, and Soclk5 are the phase inversion checker 140 output to the controller 300 to be described later,

The signals Schk0, Schk1, Schk2, Schk3 Schk4, Schk5, Ochk0, Ochk1, Ochk2, Ochk3, Ochk4, and Ochk5, respectively, are output from the latch unit 130 and are output from the analog PEL 110. The phase Phase of the signal Sclk and the clock signal Oclk output from the duplication board 200 are delayed from the delay unit 120 to be the most similar among the clock signals outputted step by step. By checking the clock signal, the bit signals Schk0, Schk1, Schk2, Schk3, Schk4, and Schk5 sequentially output from the first flip-flops 230 of the latch unit 130 in sequence. A plurality of first exclusive OR gates 251, 252, 253, 254, and 255 which output by performing an exclusive OR operation by adjacent two bits; The bit signals Ochk0, Ochk1, Ochk2, Ochk3, Ochk4, and Ochk5 sequentially outputted from the second flip-flops 230 of the latch unit 130 in steps are sequentially adjacent to each other by two bits. A plurality of second exclusive OR gates 351, 352, 353, 354, and 355 which output by performing an exclusive OR operation; The signals of the same stage are respectively output from the signals output from the plurality of first exclusive or gates 251, 252, 253, 254 and 255 and the plurality of second exclusive or gates 351, 352, 353, 354 and 355, respectively. A phase coincidence checker 150 including a plurality of AND gates 451, 452, 453, 454, and 455 which are inputted and operated on and outputted;

Stepwise clock signals Sclk, Sclkd1, Sclkd2, Sclkd3, Sclkd4, and Sclkd5 that are delayed and output from the delay unit 120 and signals that are output step by step from the phase matching unit 150 (Selclk0, Selclk1, Selclk2, Selclk3, The clock signal Oklk output from the redundant board 200 at a position where the phase is matched by the control signals Act and Swsel output from the control unit 300 to which Selclk4 is applied and described later. A clock selector 160 for selecting and outputting the clock (Selclock),

A signal Swsel and a signal for controlling a redundancy state for receiving all signals output from the phase inversion confirming unit 140 and the phase matching confirming unit 150 and selecting a point at which phases coincide. The control unit 300 for outputting to the clock selector 160.

In addition, the clock signal phase control method of the switch according to the present invention, the control step 300 of the switch 300 and the actuating step (S100) of determining whether the trunk matching board 100 currently operating (Act), and

In operation S100, when the trunk matching board 100 currently operating abnormally, the signal output from the first flip-flop 230 of the latch unit 130 and the second flip-flop 330 are determined. (B) reading a signal output from the step S110, and comparing the phases to determine whether the same value is determined at step S120;

If it is determined in the phase checking process (S120) that is not the same value, all output signals of the first exclusive or gate (251, 252, 253, 254, 255) of the phase matching unit 150 and all output signals of the second exclusive or gate (351, 352, 353, 354, 355) Phase matching check step of reading (S130), determining whether there is the same value (S140),

If there is the same value as determined in the phase matching process (S140), it reads and confirms the position of the corresponding step (S150), and selects and outputs the corresponding clock signal (Selclock) (S160).

Hereinafter, the apparatus for controlling the clock signal phase of the exchanger according to the present invention and its method will be described in detail with reference to the accompanying drawings.

When trouble occurs in the redundant trunk matching board 200 that transmits data by matching with the STM-1 class line at the exchange, the trunk matching board 100 takes over the function by switching. In the case of replacing the function as described above, the clock signal frequency and phase, which are a reference for processing the data signal, must be matched or synchronized.

As described above, the frequency of the clock signal output from each trunk matching board 100 and 200 is almost identical due to the use of components having the same characteristics, but the phase of the clock signal generated from each board is different. If there is a difference in the phase (Phase) as described above, an error occurs in the data to be processed.

Therefore, when the trunk matching boards 100 and 200 are duplicated, it is a technique of the present invention to control the phases of clock signals that may be generated to be the same.

As an example, a phase control apparatus and method will be described by a process in which a trouble occurs during operation of the redundant trunk matching board 200 and is switched to the trunk matching board 100.

The trunk matching boards 100 and 200 of the switch according to the present invention receive an 8 MHz system clock Tclk from a T-switch switching a path in a time division manner, and synchronize with the system clock signal. It generates and outputs a 19.44 MHz clock signal (Sclk) that is synchronized.

The 8 MHz system clock Tclk is inputted from a relatively inexpensive analog PLL 110, and the APLL 110 generates a 19.44 MHz clock signal Sclk synchronized with the input system clock Tclk. The trunk matching board 100 and the delay unit 120 are output to the same configuration.

The delay unit 120 receiving the clock signal Sclk of 19.44 MHz may be configured by serially connecting a plurality of buffers 121, 122, 123, 124, and 125 having a delay time of 5 ns. Detailed configuration of the delay unit 120 as shown in Figure 3 is configured in detail.

Referring to FIG. 3, by inputting the clock signal Sclk input from the APLL 110 into the first buffer 121, for example, a clock signal Sclkd1 delayed by about 5 ns is generated. By outputting the same, the second buffer 122 generates a clock signal Sclk2 delayed by about 5 ns and outputs the same.

The clock signal Sclkd2 output from the second buffer 122 is input to the third buffer 123 to generate and output a clock signal Sclkd3 delayed by about 5 ns, and the clock signal Sclkd3 is output to the fourth buffer. The clock signal Sclk4, which is inputted to 124 and is further delayed by 5 ns, is output, and the clock signal Sclkd4 is further input to the fifth buffer 125 to output the clock signal Sclkd5 which is delayed by another 5 ns, that is, At the same time, the delayed clock signal is output.

Timing states of clock signals Sclk, Sclkd1, Sclkd2, Sclkd3, Sclkd4, and Sclkd5 that are delayed and output from the delay unit 120 in steps are shown in detail in FIG. 8 as an example. As shown in FIG. 2, the output signal is output to the latch unit 130 and the clock signal selector 160, respectively.

The latch unit 130 receives the clock signals Sclk, Sclkd1, Sclkd2, Sclkd3, Sclkd4, and Sclkd5 delayed in steps from the delay unit 120, and is output from the trunk matching board 200 at 19.44 MHz. The clock signal Oclk is received.

4 is a detailed functional block diagram of the latch unit 130, and includes a first flip-flop unit 230 and a second flip-flop unit 330 each including a plurality of flip-flops FF.

As an example, the first flip-flop part 230 may include first to sixth flip-flops 231, 232, 233, 234, 235, and 236, and the second flip-flop part 230 may include a seventh flip-flop part 230. And the twelfth flip-flops 331, 332, 333, 334, 335, and 336.

The first to sixth flip-flops 231, 232, 233, 234, 235, and 236 of the first flip-flop unit 230 may receive a clock signal occlk input from the redundant board 200. The clock signals Sclk, Sclkd1, Sclkd2, Sclkd3, Sclkd4, and Sclkd5, which are respectively inputted through the data terminal as signals and are delayed and outputted from the delay unit 120 step by step, are clock signals (clk) through the clock terminal clk. clk), each of which is input one by one.

In addition, the seventh to twelfth flip-flops 331, 332, 333, 334, 335, and 336 of the second flip-flop unit 330 may receive a clock signal Oklk input from the duplex board 200. Each of the clock signals Sclk, Sclkd1, Sclkd2, Sclkd3, Sclkd4, and Sclkd5, which are respectively input as the clock signal clk through the clk, and are delayed and output from the delay unit 120 step by step, respectively, are provided for the respective data terminals (clk). Data is sequentially input one by one as a data signal (data).

The latch unit 130 outputs the clock signals Sclk, Sclkd1, Sclkd2, Sclkd3, Sclkd4, and Sclkd5 which are delayed by the input step by step, and the test signal processed by the first flip-flop unit 230 ( Schk0, Schk1, Schk2, Schk3, Schk4, and Schk5 are output, and the test signals Ochk0, Ochk1, Ochk2, Ochk3, Ochk4, and Ochk5 processed by the second flip-flop unit 330 are output.

As an example. When the clock signal as shown in FIG. 8 from the delay unit 120, that is, a clock signal delayed in steps, is input to the latch unit 130, the first flip-flop 230 may be removed. The output value is '000001' and the output value of the second flip-flop 330 is '111110'.

When analyzing the output value of the bit unit as described above, among the clock signals outputted by being delayed step by step from the delay unit 120, the phase signal from the Sclk clock signal to the Sclkd4 clock signal is faster than the Oclk clock signal and Sclkd5 It can be seen that the delay is.

Each functional unit for confirming the phase change as described above is described below.

The signal output from the latch unit 130 is output to the phase inversion confirming unit 140 and the phase match confirming unit 150, respectively.

The phase inversion confirming unit 140 receives the clock signals Sclk, Sclkd1, Sclkd2, Sclkd3, Sclkd4, and Sclkd5 which are delayed in steps from the latch unit 130, and is redundant from the redundant trunk matching board 200. A detailed functional unit is shown in FIG. 5 and the output of the clock signal Sclk output from the APLL 110 and the duplex board 200 are outputted by receiving the received clock signal Octl. The phase (Phase) of the duplicated clock signal (Oclk) is 0 degrees or 180 degrees, it is confirmed whether the match or inverted, and the output of the result is input to the controller 300.

Referring to FIG. 5, the phase inversion checker 140 includes a plurality of exclusive OR gates 141 to 146, and the exclusive OR gate 141 is output from the redundant board 200. An exclusive OR operation is performed on the clock signal (Oclk) and the clock signal (Sclk) output from the delay unit (120) and outputted (Soclk); An exclusive OR gate 142 performs an exclusive OR operation on the clock signal Oclk and the clock signal Sclkd1 output from the delay unit 120 to output an exclusive OR-Soclk1; An exclusive OR gate 143 performs an exclusive OR operation on the clock signal Oklk and the clock signal Sclkd2 output from the delay unit 120 to output Soclk2; An exclusive OR gate 144 performs an exclusive OR operation on the clock signal Oklk and the clock signal Sclkd3 output from the delay unit 120 to output Soclk3; An exclusive OR gate 145 performs an exclusive OR operation on the clock signal Oklk and the clock signal Sclkd4 output from the delay unit 120 to output Soclk4; The exclusive OR gate 145 performs an exclusive OR operation on the clock signal Oclk and the clock signal Sclkd5 output from the delay unit 120 and outputs the output Soclk5.

Each output signal (Soclk, Soclk1, Soclk2, Soclk3, Soclk4, Soclk5, Soclk5), when the output value is '0', the phase difference between the clock signal of Oclk and the delayed Sclk signal of each stage is 0 degrees. When the output value is '1', it indicates that the phase difference between the clock signal of the Oclk and the delayed Sclk signal has been inverted by 180 degrees, and the output value is applied to the control unit 300 to process the trunk matching board. When the 100 is transferred to the redundant board 200, the phase is transferred at the same stage.

If the phases from the phase inversion confirming unit 140 coincide, the control unit 300 processes it. However, if the phases do not coincide exactly, the phase coincidence checker 150 processes the process.

Referring to FIG. 6, a detailed functional diagram of the phase matching unit 150 includes six bit unit signals output from the first flip-flop unit 230 of the latch unit 130. Schk0, Schk1, Schk2, Schk3, Schk4, and Schk5) are sequentially inputted so that two bits are overlapped, and an exclusive OR operation is performed to output corresponding values (Sechk0, Sechk1, Sechk2, Sechk3, Sechk4). A first exclusive or gate consisting of a plurality of exclusive or gates 251 to 255; The six bit unit signals Ochk0, Ochk1, Ochk2, Ochk3, Ochk4, and Ochk5 output from the second flip-flop unit 330 of the latch unit 130 are sequentially inputted so as to overlap two bits. A second exclusive or gate consisting of a plurality of exclusive or gates 351 to 355 for performing an exclusive or (E-OR) operation and outputting corresponding values, respectively (Oechk0, Oechk1, Oechk2, Oechk3, Oechk4); The signals Sechk0, Sechk1, Sechk2, Sechk3, and Sechk4 output from the first exclusive or gate and the signals Oechk0, Oechk1, Oechk2, Oechk3, and Oechk4 output from the second exclusive or gate are the same steps (Sechk0). , Oechk0) ... (Sechk4, Oechk4), and a plurality of AND gates 451 to 455 are inputted and ANDed to output corresponding values (Selclk0, Selclk1, Selclk2, Selclk3, Selclk4). When the output values Selclk0, Selclk1, Selclk2, Selclk3, and Selclk4 of the AND gate have a value of '1', the clock signal Sclk and the clock signal Oklk at the position of the corresponding step are composed of an AND gate. Check that the phases of P are close and coincident.

In more detail, when the value output from the first flip-flop 230 of the latch unit 130 is '000001' and the value output from the second flip-flop 330 is '111110', the first exclusive The output values of the OR gates 251 to 255 are '00001', and the output values of the second exclusive OR gates 351 to 355 are '00001', and the two values are the same, and the bit values at the same position are '1'.

If the bit values are not the same, the clock signal Sclk of the trunk matching board 100 currently in operation and the frequency of the clock signal Octl of the redundant board 200 are different. Therefore, the control unit 300 does not alternately use the clock signal.

The output values '00001' of the first exclusive or gates 251 to 255 and the output values '00001' of the second exclusive or gates 351 to 355 are inputted to the respective AND gates in the same order, and As it is output, the value of '00001' is output.

Since the above output value is '1' in Selclk4, it indicates that there is a moment when the phases of the clock signals Sclk and Oclk are synchronized or matched between Selclk3 and Selclk4, and the clock signal to be finally selected is Sclk4 among the delayed clock signals. And one of Sclk5.

The controller 300 considers that the phase difference between Sclk4 and Sclk5 is 5 ns and the clock signal Oclk is a clock signal input from the redundant board 200 which is another board. The control signal Swsel for selecting Sclk4 is output to the clock selector 160 and the control signal Act for selecting Sclk4 is output.

Signals applied to the clock selector 160 are shown in detail in FIG. 7.

In the method using the clock signal phase control device having the configuration and function as described above, the controller 300 determines whether a trouble has occurred in the board 200 currently operating (S100), and the trouble occurs. In case of normal operation without occurrence, the feedback is fed back to the start stage. If a trouble occurs, the value output from the first flip-flop 230 and the second flip-flop 230 of the latch unit 130 The value output from 330 is read (S110), and it is checked whether the value of the read bit is the same value at the same position (S120).

If the check result (S120) is the same, it is fed back to the initial process (S100). If the value is not the same, the first exclusive or gate constituting the phase match check unit 150 is the same. The value (Sechk [0..4]) outputted from and the value (Oechk [0..4]) outputted from the second exclusive or gate are read (S130).

The controller 300 analyzes the read value to determine whether the two values have the same value at the same position (S140). If the same value is not the same value, the control unit 300 changes the clock signals Sclk and Oclk because they are different. Therefore, it returns to the said initial process (S100).

If the same value in the determination (S140), since the frequency is the same and there is a difference in phase, the control unit 300 is a value output from the AND gate of the phase matching unit 150 (Selclk [0..4]) After reading (S150), the control signal (Act, Swsel) for finally selecting a clock signal of the same phase is output to the clock selector 160.

The clock selector 160 may be optimally matched in phases among the delayed clock signals applied from the delay unit 120 by control signals Act and Swsel output from the controller 300. The clock signal is selected and output.

According to the present invention having the above-described configuration, it is possible to switch by controlling the phases of the clock signals respectively output from the redundant boards without using an expensive digital PLL (DPLL) so as to be switched, and to control the controller according to the needs of the user. Thus, the phase of the clock signal to be selected can be controlled.

According to the configuration of the present invention, in order to improve the reliability and stability of the exchange, in redundancy of the trunk matching board, when the duplicated board is switched, the phases of the clock signals generated in each case are matched so that they are processed at the exchange. This has the effect of preventing errors in the data.

In addition, instead of using a relatively expensive digital PLL, a relatively inexpensive analog PLL can be used, so that the price of the exchange can be lowered.

Claims (6)

In the clock signal selection device of the redundant switch trunk matching board, An analog PEL that generates and outputs a clock signal synchronized with an input system clock signal; A delay unit for delaying the clock signal output from the PEL in multiple stages and outputting the clock signal delayed for each stage; A latch unit receiving a clock signal output from the delay unit and a clock signal output from the redundant board, respectively, and checking a phase difference between the clock output from the PEL and the clock signal output from the redundant board; A phase inversion checking unit receiving the output signal of the latch unit and the clock signal of the duplex board, and checking whether the phase of the clock signal output from the PEL and the clock signal output from the duplex board is the same or inverted; The phase of the clock signal output from the latch unit and the clock signal output from the PEL and the clock signal output from the redundant board are most similar in phase among the clock signals output by being delayed step by step from the delay unit. A phase matching check unit for checking a clock signal of And a clock selector configured to receive the signals output from the delay unit and the phase coincidence checker, and to select and output a clock signal output from the redundant board at a position coinciding with the control signal. Clock signal phase control device. According to claim 1, And a controller configured to receive a signal output from the phase inversion confirming unit and a phase match confirming unit, and to output a signal for selecting a time point at which phases match and a signal for controlling a redundancy state to the clock selecting unit. A clock signal phase control apparatus of an exchanger. According to claim 1, And said delay unit is configured by connecting a plurality of buffers having a predetermined delay time in series. An act of determining, by the controller of the exchange, whether the trunk matching board currently operating normally operates; A phase checking process of determining whether the trunk matching board currently operating in the act process is the same value by reading a signal output from the first flip-flop and a signal output from the second flip-flop; A phase matching process of reading all outputs of the first exclusive or gate and all outputs of the second exclusive or gate when the phase matching process is not the same, and determining whether there is the same value; If there is the same value in the phase matching process, the clock signal phase control method of the switch, characterized in that consisting of a selection process for confirming the position of the step and selecting and outputting the clock signal. The method of claim 4, wherein the checking of phase matching is performed. And determining whether a signal having the same step has the same value among the signals output from the first exclusive or gates and the second exclusive or gates, respectively. The method of claim 4, wherein the selection process, The clock signal phase control method of the exchange, characterized in that for selecting the clock signal in consideration of the delay time among the clock signal in the step of reading all the signal values output from the AND gate of the phase matching unit.