KR20020041594A - Method for Fabricating of Semiconductor Device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device that secures a process margin by directly forming a bit line on a poly plug without forming a bit line contact hole. Forming a plurality of word lines on the semiconductor substrate, forming an interlayer insulating film on the entire surface including the word lines, and electrically connecting the semiconductor substrate through the interlayer insulating film of the cell region. Forming a plurality of poly plugs, forming a contact hole by selectively removing the interlayer insulating film of the peripheral region, forming a metal plug inside the contact hole, and a metal electrically connected to the metal plug Forming a wiring and at least a portion of the poly plug at the same time as the formation of the metal wiring; It characterized by forming, including the step of forming a bit line.

Description

Method for manufacturing a semiconductor device {Method for Fabricating of Semiconductor Device}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device for improving productivity by forming bit lines directly on a poly plug without forming bit line contact holes.

In general, a dynamic random access memory (DRAM) device includes a cell region in which a plurality of memory cells are regularly arranged in the X and Y directions, and a peripheral region formed around the cell region. According to the chip, a logic region for controlling the memory cells is further configured in the peripheral region.

In this case, each of the memory cells includes a row signal line called a word line, a column signal line called a bit line, and a capacitor for storing data applied to the bit line or outputting the stored data to the bit line.

As the DRAM device is highly integrated, it is difficult to secure a margin of the photo and etching process, and thus it is very difficult to secure a yield during mass production.

Hereinafter, a method of manufacturing a semiconductor device according to the prior art will be described with reference to the accompanying drawings.

1A to 1F are cross-sectional views of a manufacturing process of a semiconductor device according to the prior art.

Referring to a method of fabricating a semiconductor device according to the related art, first, as shown in FIG. 1A, an isolation region 11 is formed on a silicon substrate 10 including a cell region, a peripheral region, and a logic region to form an active region. Define.

A plurality of word lines 13 are formed on the active region defined as described above, and a polysilicon film, a tungsten silicide film, and a silicon nitride film are sequentially stacked on top of each other. Form.

Subsequently, after forming the active region low concentration impurity region in the semiconductor substrate 10 using the word lines 13 as a mask, an insulating film is deposited on the semiconductor substrate 10 including the word lines 10. The insulating film sidewall 14 is formed by etching back the insulating film so as to remain only on both sides of the word line 13.

Source / drain impurity regions 22 are formed in the semiconductor substrate 10 on both sides of the word line 13 through high concentration impurity ion implantation using the word line 13 and the insulating layer side wall 14 as a mask. .

Next, as shown in FIG. 1B, a first interlayer insulating film 15 is formed and planarized on the entire surface including the word line 13.

The first interlayer insulating layer 15 is selectively etched to form a plurality of trenches for exposing the source / drain impurity regions 22 of the cell region.

Subsequently, polysilicon is deposited on the entire surface including the trench, and then planarized to form a plug 16 having a polysilicon embedded in the trench, and the first interlayer insulating layer 15 including the plug 16. A second interlayer insulating film 17 is formed on the top.

At this time, the second interlayer insulating film 17 is an oxide film.

Next, as shown in FIG. 1C, after applying the photoresist 18 on the second interlayer insulating layer 17, a mask for forming a bit line contact hole on the photoresist 18 (not shown). ), And then the photoresist 18 is exposed using the mask.

At this time, a phase shift mask (PSM) is mainly used as the mask 18.

The exposure method using the PSM is a method of appropriately adjusting the reinforcement interference and the extinction interference by using the phase difference of light to form a finer contact hole than when exposed using ordinary illumination and photomask.

However, close attention is required because exposure conditions may be exposed to undesired areas even if the exposure conditions are slightly changed.

Subsequently, as shown in FIG. 1D, the second interlayer insulating layer 17 is selectively removed by an etching process using the photoresist 18 patterned by an exposure and development process as a mask, thereby forming a bit line contact hole 19a. , The peripheral circuit contact hole 19b and the logic contact hole 19c are formed.

Thereafter, as shown in FIG. 1E, polysilicon or metal silicide is filled to the point where the bit line contact hole 19a, the peripheral circuit contact hole 19b, and the logic contact hole 19c are completely filled, and the material remains. The bit line plug 20a, the peripheral circuit plug 20b, and the logic plug 20c are formed by performing an etch-back or chemical and mechanical polishing process so as not to.

Finally, as shown in FIG. 1F, tungsten is deposited and patterned on each of the bit line plugs 20a, the peripheral circuit plugs 20b, and the logic plugs 20c, thereby forming the bit line 21a and peripheral circuits. The wiring 21b and the logic wiring 21c are formed.

This completes the predetermined semiconductor element.

However, the conventional method of manufacturing a semiconductor device as described above has the following problems.

That is, in the conventional method of forming a bit line plug in a contact hole in which an insulating film on a poly plug is selectively removed and forming a bit line thereon, a PSM is mainly used as a mask for forming a fine contact hole. There is a problem in that it is difficult to control the exposure to an undesired area even if the condition is slightly changed.

In particular, in MDL (Merge DRAM & Logic), which forms DRAM and logic as one chip, PSM is more difficult to use because the contact density required for each region is different.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and provides a method of manufacturing a semiconductor device which secures a process margin by directly patterning bit lines on a poly plug without forming bit line contact holes. There is a purpose.

1A to 1F are cross-sectional views of a manufacturing process of a semiconductor device according to the prior art.

2A through 2F are cross-sectional views illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention.

* Explanation of symbols on the main parts of the drawings

110 semiconductor substrate 111 device isolation film

112: gate oxide film 113: word line

114: insulating film side wall 115: first interlayer insulating film

116: poly plug 118: mask

119b: Peripheral Contact Hole 119c: Logic Contact Hole

120b: peripheral circuit plug 120c: logic plug

121a: Bit line 121b: Peripheral circuit wiring

121c: logic wiring 122: impurity region for source / drain

A method of manufacturing a semiconductor device of the present invention for achieving the above object comprises the steps of: forming a plurality of word lines on the semiconductor substrate in a semiconductor substrate defined by a cell region and a peripheral region; Forming an interlayer insulating film on the entire surface; forming a plurality of poly plugs electrically connected to the semiconductor substrate through the interlayer insulating film of the cell region; and selectively removing the interlayer insulating film of the peripheral region. Forming a metal plug, forming a metal plug inside the contact hole, forming a metal wiring electrically connected to the metal plug, and simultaneously forming the metal wiring on a portion of the poly plug. And forming a bit line.

As described above, the present invention is characterized in that the bit line of the cell region is formed by directly depositing and patterning tungsten on the poly plug without forming bit line contact holes.

Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

2A through 2F are cross-sectional views illustrating a process of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

In the method of manufacturing a semiconductor device according to the present invention, as shown in FIG. 2A, a device isolation film (STI) is formed on a semiconductor substrate 110 including a cell region, a peripheral region, and a logic region using a shallow trench isolation (STI) technique. isolation 111, thereby defining the active region.

In addition, a gate oxide film 112 is formed on the active region defined as described above, and a plurality of word lines 113 are formed by sequentially stacking a polysilicon film, a tungsten silicide film, and a silicon nitride film thereon. .

In this case, the silicon nitride film serves as a cap insulating film to insulate the conductive layers of the polysilicon film and the tungsten silicide film from the outside.

Subsequently, an active region low concentration impurity region is formed in the semiconductor substrate 110 using the word lines 113 as a mask, and then an insulating film is deposited on the semiconductor substrate 110 including the word lines 110. The insulating film sidewall 114 is formed by etching back the insulating film so as to remain only on both sides of the word line 113.

Source / drain impurity regions 122 are formed in the semiconductor substrate 110 on both sides of the word line 113 through the implantation of high concentration impurity ions using the word line 113 and the insulating film side wall 114 as a mask. .

Next, as shown in FIG. 2B, the first interlayer insulating film 115 is formed and planarized on the entire surface including the word line 113.

In this case, a chemical mechanical polishing (CMP) process may be applied to planarize the first interlayer insulating film 115.

The first interlayer insulating layer 115 is selectively etched to form a plurality of trenches for exposing the source / drain impurity regions 122 of the cell region.

Subsequently, polysilicon is deposited on the entire surface including the trench, and then planarized to form a plug 116 in which polysilicon is embedded in the trench.

Next, as shown in FIG. 2C, after the photoresist 118 is coated on the first interlayer insulating film 115, the photoresist 118 is covered after the binary mask 118 is covered on the photoresist 118. ) Is exposed.

Subsequently, as shown in FIG. 2D, the first interlayer dielectric layer 115 and the silicon nitride layer of the word line in the logic region are etched by an etching process using the photoresist 118 patterned by the exposure and development process as a mask. The peripheral circuit contact hole 119b and the logic contact hole 119c are formed.

In this case, the bit contact hole is not formed.

Thereafter, as shown in FIG. 2E, tungsten, which is a low-resistance metal, is sufficiently filled to completely fill the peripheral circuit contact hole 119b and the logic contact hole 119c, and an etch-back or chemical and mechanical polishing process is performed. The material is planarized so that the material does not remain to form the peripheral circuit plug 120b and the logic plug 120c.

Finally, as illustrated in FIG. 2F, tungsten is deposited and patterned on the first interlayer insulating layer to form a bit line 121a and various wirings to complete a desired semiconductor device.

That is, a bit line 121a is formed on a part of the poly plug 116, a peripheral circuit wiring 121b is formed on the peripheral circuit plug 120b, and a logic is formed on the logic plug 120c. The wiring 121c is formed.

At this time, a conductive material such as polysilicon or titanium silicide may be used in addition to tungsten as a material for the bit line, various wirings, peripheral circuit plugs, and logic plugs.

Although the present invention is particularly effective for MDL in which DRAM and logic are formed of one chip, the present invention may be applied to a chip composed only of DRAM.

The method of manufacturing a semiconductor device of the present invention as described above has the following effects.

First, by forming the bit line directly on the poly plug without forming the bit line plug, the number of processes is reduced and productivity is improved.

Second, when forming the contact hole in the MDL, because the bit line contact hole is not formed, process defects due to contact hole density unevenness are eliminated.

Third, since the bit line contact hole is not formed, the exposure conditions can be improved to secure a large process margin, and a low-cost binary mask can be used instead of the phase inversion mask used previously, thereby lowering the process cost.

Claims (7)

In the MDL device which has one-chip DRAM and logic, Defining a semiconductor substrate as an active region and a field region; Forming a plurality of word lines on the substrate of the active region; Forming an interlayer insulating film on the entire surface including the word line; Forming a plurality of first plugs penetrating the interlayer insulating film and connected to the substrate in the cell region; Forming second and third plugs connected to the substrate of the peripheral region and the word line of the logic region; And forming bit lines connected to the first plug and metal wires connected to the second plug and the third plug. The method of claim 1, wherein the bit line is directly formed on the first poly plug. The method of claim 1, further comprising forming impurity regions in the substrates of the active regions on both sides of the word lines after forming the word lines. The method of claim 1, wherein the forming of the first and second plugs and the third plug comprises: Forming a contact hole by forming an interlayer insulating film over the substrate including the word lines, and selectively removing the interlayer insulating film in the cell region; Embedding a conductive material in the contact hole to form first plugs; Forming a mask to selectively expose the peripheral region and the logic region, and then selectively removing the interlayer insulating layer using the mask; And a residual system forming a second plug and a third plug in a portion where the interlayer insulating film is removed. The method of claim 4, wherein the mask uses a binary mask. The method of claim 1, wherein the first and second plugs are made of metal. The method of claim 6, wherein the metal is formed using any one of tungsten (W) and titanium (Ti).