KR20020037851A - Semiconductor device having bit line and method for forming the same - Google Patents

Abstract

A semiconductor device having a bit line and a manufacturing method thereof are disclosed. An insulating film, a bit line conductive film, and a mask layer are sequentially formed on the semiconductor substrate, and then patterned to form a bit line stack in which an insulating film pattern, a bit line, and a mask pattern are sequentially stacked. A portion of the bit line is etched to form an undercut, and then a material layer pattern is formed to fill the undercut. Then, bit lines are formed in which both side walls are surrounded by the material layer pattern. Due to the material layer pattern formed on both sidewalls of the bit line, parasitic capacitance generated between the bit line and the adjacent conductive layer may be reduced.

Description

A semiconductor device having a bit line and a manufacturing method therefor {SEMICONDUCTOR DEVICE HAVING BIT LINE AND METHOD FOR FORMING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a bit line capable of reducing parasitic capacitance between a bit line and a contact plug for a storage node, and a method of manufacturing the same.

As DRAMs become more integrated, design rules for implementing integrated circuits are also decreasing. Accordingly, the process of forming a memory cell becomes increasingly difficult, and in particular, it is difficult to secure a process margin of a contact plug for a storage node formed between bit lines in a COB (capacitor over bit line) structure.

In order to solve this problem, a self aligned contact (SAC) process, which is used in a process of forming contact pads between gate patterns, is applied to a process of forming a contact plug for a storage node.

Hereinafter, the problems of the prior art will be described with reference to the accompanying drawings.

1A to 1E are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

Referring to FIG. 1A, an isolation layer, a gate pattern, and a source / drain region (not shown) are formed on a semiconductor substrate 10 in a conventional process. The first insulating layer 12 is formed on the entire surface of the semiconductor substrate 10 including the gate pattern. A self-aligned contact forming process is used to form contact pads 14 electrically connected to the source / drain regions between the gate patterns.

Referring to FIG. 1B, the second insulating layer 17 is formed on the entire surface of the resultant in which the contact pads 14 are formed. The second insulating layer 17 is patterned to form a bit line contact hole (not shown) that exposes a predetermined region of the contact pad 14. A conductive film 18 filling the contact hole is formed on the second insulating film 17 including the contact hole. On the conductive film 18, a mask layer 19 for applying a self-aligned contact forming process is formed.

Referring to FIG. 1C, the mask layer 19, the conductive layer 18, and the second insulating layer 19 are sequentially patterned to form the bit line stack 20. The bit line stack 20 includes an insulating layer pattern 17a, a bit line 18a, and a mask pattern 19a that are sequentially stacked.

Referring to FIG. 1D, spacers 21 are formed on both sidewalls of the bit line stack 20 by anisotropic etching after forming an insulating film for spacers on the entire surface of the bit line stack 20. The third insulating layer 25 is formed on the entire surface of the resultant product in which the spacers 21 are formed.

Referring to FIG. 1E, a third insulating layer 25 is patterned by a self-aligned contact forming process to form a contact hole for a storage node (not shown) exposing the contact pads 14. As a result, the third insulating layer pattern 25a remains on the bit line stack 20. In the contact hole etching process, the spacer 21 and the mask pattern 19a serve as an etch stop layer. A conductive film filling the contact hole is formed on the entire surface of the resultant in which the contact hole for the storage node is formed, and then the planar etching is performed to form the contact plug 27 for the storage node.

As described above, when the contact plugs 27 for the storage nodes are formed by the self-aligned contact forming process between the bit line stacks 20, only the thin spacers 21 between the bit lines 18a and the contact plugs 27 are formed. It exists. Typically, the spacer 21 is formed of a silicon nitride film. Since the silicon nitride film has a high dielectric constant, parasitic capacitance is generated between the bit line 18a and the contact plug 27. Due to such parasitic capacitance, the operation speed and sensing efficiency of the device are lowered, and the effective capacitance of the capacitor is reduced.

The present invention has been proposed to solve the above-mentioned problems, and an object thereof is to provide a method of manufacturing a semiconductor device capable of reducing parasitic capacitance occurring between a bit line and a contact plug for a storage node.

Another object of the present invention is to provide a semiconductor device capable of reducing parasitic capacitance caused by bit lines.

1A to 1E are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

2A to 2G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

10, 100: semiconductor substrate 12, 102: first insulating film

14 and 105: contact pads 17 and 108: second insulating film

18, 110: first conductive film 19, 111: mask layer

17a, 108a: insulating film pattern 18a, 110a: bit line

19a and 111a mask pattern 116 material layer pattern

20, 112: bit line stack 21, 120: spacer

25, 123: third insulating film

27, 126: contact plug for storage node

(Configuration)

In order to achieve the above object, the semiconductor device manufacturing method according to the present invention sequentially forms an insulating film, a bit line conductive film, and a mask layer on a semiconductor substrate. The mask layer, the conductive layer, and the insulating layer are sequentially patterned to form a bit line stack in which an insulating layer pattern, a bit line, and a mask pattern are sequentially stacked. A portion of the bit line of the bit line stack is wet etched to form an undercut. A material layer pattern is formed to fill the undercut portion. Spacers are formed on both sidewalls of the bit line stack.

The method may further include forming a contact hole exposing a predetermined region of the semiconductor substrate by patterning the insulating layer before forming the bit line conductive layer.

In addition, the material layer pattern may be formed of a silicon oxide film or a silicon nitride film.

In order to achieve the above object, a semiconductor device according to the present invention comprises a semiconductor substrate, an insulating film pattern formed in a predetermined region of the semiconductor substrate, a bit line formed on a predetermined region of the insulating film pattern, formed on the insulating film pattern, And a material layer pattern surrounding both sidewalls of the bit line, the material layer pattern and a mask pattern formed on the bitline, the insulating layer pattern, the material layer pattern, and spacers formed on both sidewalls of the mask pattern. do.

In the present invention, it is preferable that the bit line is electrically connected to a predetermined region of the semiconductor substrate through the insulating film pattern.

In addition, the insulating film pattern is preferably a silicon nitride film or a silicon oxide film.

(Example)

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A to 2G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 2A, a device isolation film (not shown) and a transistor (not shown) including a gate pattern and a source / drain region are formed on the semiconductor substrate 100 in a conventional process. The first insulating layer 102 is formed on the entire surface of the semiconductor substrate 100 on which the transistor is formed. The self-aligned contact forming process forms a contact pad 105 electrically connected to the source / drain regions between the gate patterns. In detail, the first insulating layer 102 is patterned to form contact holes exposing predetermined regions of the semiconductor substrate 100 between the gate patterns. A first conductive layer, for example, a polysilicon layer, is formed on the entire surface of the resultant in which the contact hole is formed. The first conductive layer is planarized and etched to expose the top surface of the gate pattern to form a contact pad 105 electrically connected to the semiconductor substrate 100, that is, the source / drain region.

Referring to FIG. 2B, a second insulating film 108 is formed on the first insulating film 102 and the contact pad 105. The second insulating layer 108 is patterned to form a bit line contact hole (not shown) that exposes a predetermined region of the contact pad 105. A second conductive film 110 filling the contact hole, for example, a tungsten film, is formed on the second insulating film 108 including the contact hole. A mask layer 111, for example, a silicon nitride layer, is formed on the second conductive layer 110 to prevent the bit line from being etched in a subsequent process.

Referring to FIG. 2C, the bit line stack 112 is formed by sequentially etching the mask layer 111, the second conductive layer 110, and the second insulating layer 108 by a patterning process. Accordingly, the bit line stack 112 includes an insulating layer pattern 108a, a bit line 110a, and a mask pattern 111a that are sequentially stacked. At this time, the CD (critical dimension) of the bit line (110a) is formed larger than the final target in consideration of the undercut process for the bit line (110a) proceeds to a subsequent process, so as not to affect the operation speed and other characteristics of the device do.

Referring to FIG. 2D, a process of forming an undercut 114 by etching a portion of the bit line 110a is performed as a feature of the present invention. The etching of the bit line 110a may be performed by, for example, a wet etching process. For wet etching, it is preferable to use an insulating layer pattern 108a, a mask pattern 111a, and a process having a high etching selectivity between the contact pad 105 and the bit line 110a, preferably an etching process using an etching solution containing hydrogen peroxide. Do. Then, the bit line 110a between the insulating layer pattern 108a and the mask pattern 111a is partially etched to form an undercut 114.

Referring to FIG. 2E, the material layer filling the undercut 114 is formed on the entire surface of the resultant undercut 114, and then anisotropically etched to form the material layer pattern 116 on both sidewalls of the bit line 110a. The material layer is formed of, for example, an insulating film such as a silicon nitride film or a silicon oxide film. Preferably, the silicon oxide film is formed of a silicon oxide film having a lower dielectric constant than the silicon nitride film, for example, a high temperature oxide (HTO) film or a medium temperature oxide (MTO) film.

Referring to FIG. 2F, an insulating layer for forming a spacer, for example, a silicon nitride layer, is formed on the entire surface of the resultant material layer pattern 116. The insulating layer is anisotropically etched to form spacers 120 on both sidewalls of the bit line stack 112. Then, both sidewalls of the bit line 110a may be surrounded by the material layer pattern 116 and the spacer 120. The third insulating layer 123 is formed on the entire surface of the semiconductor substrate 100 including the bit line stack 112 on which the spacers 120 are formed. The third insulating layer 123 is planarized by a process such as chemical mechanical polishing (CMP) to planarize the upper surface of the third insulating layer 123.

Referring to FIG. 2G, a photoresist pattern (not shown) is formed on the planarized third insulating layer 123 to form a self-aligned contact hole. The third insulating layer 123 is etched using the photoresist pattern as an etch mask to form contact holes (not shown) for the storage node exposing the contact pads 105 between the bit line stacks 112. In this case, the spacer 112 and the mask pattern 111a are used as the etch stop layer in the contact hole forming process. When the contact holes are formed, the third insulating layer pattern 123a remains on the bit line stack 112. A third conductive layer filling the contact holes is formed on the entire surface of the product in which the contact holes are formed. The third conductive layer may be planarized and etched by a CMP process or the like until the third insulating layer pattern 123a is exposed to form a storage node contact plug 126 electrically connected to the contact pad 105.

According to this method, the material layer pattern 116 is formed on both sidewalls of the bit line 110a, thereby forming the material layer pattern 116 and the spacer (between the bit line 110a and the contact plug 126 for the storage node. 120) is present. As a result, the parasitic capacitance is reduced by increasing the effective thickness of the insulating film formed between the bit line 110a and the contact plug 126 compared to the prior art. In the case where the material layer pattern 116 is formed of the silicon oxide film, the parasitic capacitance may be further reduced since the dielectric constant of the silicon oxide film is smaller than that of the silicon nitride film.

Next, a semiconductor device having a bit line manufactured by an embodiment of the present invention will be described in detail with reference to FIG. 2G.

Referring to FIG. 2G, a contact pad 105 is formed on the semiconductor substrate 100 to be connected to the first insulating layer 102 and a predetermined region of the semiconductor substrate 100. The bit line stack 112 including the bit line 110a is formed on the contact pad 105 and the first insulating layer 102. The bit line stack 112 may include the second insulating layer pattern 108a, the material layer pattern 116 and the bit surrounding both sidewalls of the bit line 110a and the bit line 110a formed on the second insulating layer pattern 108a. The mask pattern 111a is formed on the line 112 and the material layer pattern 116. Here, the material layer pattern 116 is preferably a silicon oxide film or a silicon nitride film. In addition, spacers 112 are formed on both sidewalls of the bit line stack 112. Although not shown, the bit line 110a may be electrically connected to a predetermined region of the contact pad 105 through the second insulating layer pattern 108a. The third insulating layer pattern 123a is formed on the mask pattern 111a of the bit line stack 112. A contact plug 126 for a storage node is formed between the bit line stack 112 and the third insulating layer patterns 123a.

According to the present invention, a parasitic capacitance generated between the bit line and the contact plug is formed by forming a material layer pattern on both sidewalls of the bit line to increase the effective thickness of the insulating film existing between the bit line and the contact plug for the storage node adjacent to the bit line. Can be reduced. Accordingly, since the RC delay phenomenon is reduced, there is an effect that can improve the operating speed and the sensing efficiency of the device.

Claims (9)

Forming an insulating film on the semiconductor substrate; Forming a bit line conductive film on the insulating film; Forming a mask layer on the conductive film; Patterning the mask layer, the conductive film, and the insulating film in order to form a bit line stack in which an insulating film pattern, a bit line, and a mask pattern are sequentially stacked; Wet etching a portion of the bit line of the bit line stack to form an undercut; Forming a material layer pattern filling the undercut portion; And And forming spacers on both sidewalls of the bit line stack including the material layer pattern. The method of claim 1, And forming a contact hole exposing a predetermined region of the semiconductor substrate by patterning the insulating film before forming the conductive film. The method of claim 1, And the material layer pattern is formed of a silicon oxide film or a silicon nitride film. The method of claim 3, wherein And the silicon oxide film is formed of a high temperature oxide (HTO) film or a medium temperature oxide (MTO) film. The method of claim 1, And said bit line conductive film is formed of a tungsten film. The method of claim 1, And the mask layer and the spacer are formed of a silicon nitride film. Semiconductor substrates; An insulating film pattern formed on a predetermined region of the semiconductor substrate; A bit line formed on a predetermined region of the insulating layer pattern; A material layer pattern formed on the insulating layer pattern and surrounding both sidewalls of the bit line; A mask pattern formed on the material layer pattern and the bit line; And And a spacer formed on both sidewalls of the insulating layer pattern, the material layer pattern, and the mask pattern. The method of claim 7, wherein And the bit line is electrically connected to a predetermined region of the semiconductor substrate through the insulating film pattern. The method of claim 7, wherein The material layer pattern is a semiconductor device, characterized in that the silicon oxide film or silicon nitride film.