KR20020034436A - Integrator for skip circuit in rambus dram - Google Patents

Abstract

The present invention relates to an integrator for a skip circuit of a Rambus DRAM. The present invention can operate stably by increasing the sensing sensitivity of data to obtain an accurate output value. To this end, an integrator for a skip circuit of a Rambus DRAM according to the present invention includes pull-up and pull-down driver means for supplying pull-up voltage and pull-down voltage to the pull-up and pull-down bias potential of the integrator, and the pull-up bias potential of the first control signal. First switching means for transmitting to the first node by an inversion signal, second switching means for transmitting the second pull-up bias potential to the second node by an inversion signal of a second control signal, and a signal of the first node Third switching means for transmitting the signal to the pull-down bias potential by the second control signal, fourth switching means for transmitting the signal of the second node to the pull-down bias potential by the first control signal, and the second Fifth switching means for transmitting a signal of one node to a first latch means for storing data by a third control signal; Sixth switching means for transmitting the output signal of the first latching means to the second node by the third control signal, and a second inputting signal of the second node to latch the output signal until data is transferred. And latching means and equalizing means for equalizing the potentials at both ends of the first latching means before data is input to the first latching means.

Description

INTEGRATOR FOR SKIP CIRCUIT IN RAMBUS DRAM}

The present invention relates to an integrator for a skip circuit of a Rambus DRAM. In particular, the present invention relates to an integrator capable of stable operation by increasing the sensing sensitivity of data to obtain an accurate output value. It is about.

1 is a circuit diagram illustrating an integrator for a skip circuit of a rambus DRAM according to the prior art.

In the conventional integrator, as shown, PMOS transistors P1 and P2 having a current mirror structure supply a power supply voltage Vdd to a node Nd1 and a pull-up bias node Nd2 of the integrator, respectively. The integrator discharges the potentials of the node Nd1 and the pull-down bias node Nd3 of the integrator to ground voltage Vss by the current mirror NMOS transistors N1 and N2 operated by the potential of Nd1. Make it work.

The PMOS transistor P3 operated by the inverted signal of the skip-up signal skipp transfers the voltage of the pull-up bias node Nd2 to the node Nd4 and operates by the inverted signal of the skip-down signal skipDn. The PMOS transistor P4 transfers the voltage of the pull-up bias node Nd2 to the node Nd7. A capacitor C1 is connected between the node Nd4 and the ground voltage Vss to charge the voltage of the node Nd4, and a capacitor C2 is connected between the node Nd7 and the ground voltage Vss. To charge the voltage of the node Nd7.

In addition, the NMOS transistor N3 operated by the skip down signal skipDn transfers the voltage of the node Nd4 to the pull-down bias node Nd3, and the NMOS transistor N3 operated by the skip up signal skipp N4 transfers the voltage of the node Nd7 to the pull-down bias node Nd3.

The signal of the node Nd4 is a transfer gate composed of a PMOS transistor P5 operated by a latchskip bar signal LSB and an NMOS transistor N5 operated by a latchskip signal LS. By P5 and N5, they are stored in the latch circuit portion composed of the inverter INV3 and the inverter INV4. The signal of the output node Nd7 of the latch circuit portion composed of the inverter INV3 and the inverter INV4 is a PMOS transistor P6 and a latchskip signal operated by the latchskip bar signal LSB. It is transferred to the node Nd7 by the transfer gates P6 and N6 constituted by the NMOS transistor N6 operated by LS.

The latch circuit part configured of the D flip-flop 2 inputs the delay signal of the latch skip signal LS as a reset signal and latches a skip value that is an output signal by inputting an inverted signal of the node Nd7 as a set signal. do.

As in the above configuration, the conventional integrator charges or discharges the capacitor C1 and the capacitor C2 according to the skip up signal skipp and the skip down signal skipDn, and the nodes Nd4 and Nd7 Make a constant voltage level. When the latch skip signal LS is kept low and becomes high, the voltage difference between the node Nd4 and node Nd7 is formed by a latch circuit composed of the inverter INV3 and the inverter INV4. Is sensed to latch a skip value that is an output signal in the latch circuit portion of the D flip-flop 2.

However, when the voltage difference between the node Nd4 and the node Nd7 is small, the latch circuit unit composed of the inverter INV3 and the inverter INV4 storing any previous value may not sense the voltage difference properly. There was a problem displaying the value stored in.

Accordingly, the present invention has been made to solve the above problems, and an object of the present invention is to equalize and sense data input nodes before data is input, thereby enabling accurate detection of Rambus DRAMs with low potential difference. To provide an integrator for the skip circuit.

In order to achieve the above object, an integrator for a skip circuit of a Rambus DRAM according to the present invention,

Pull-up and pull-down driver means for supplying a pull-up voltage and a pull-down voltage respectively with the pull-up and pull-down bias potentials of the integrator;

First switching means for transferring the pull-up bias potential to a first node by an inverted signal of a first control signal;

Second switching means for transferring the second pull-up bias potential to a second node by an inverted signal of a second control signal;

Third switching means for transmitting the signal of the first node to the pull-down bias potential by the second control signal;

Fourth switching means for transmitting a signal of the second node to the pull-down bias potential by the first control signal;

Fifth switching means for transmitting the signal of the first node to a first latch means for storing data by a third control signal;

Sixth switching means for transmitting the output signal of the first latching means to the second node by the third control signal;

Second latch means for inputting a signal of the second node to latch an output signal until data is transitioned;

And equalizing means for equalizing the potentials at both ends of the first latching means before data is input to the first latching means.

In an integrator for a skip circuit of a rambus DRAM according to the present invention, the pull-up driver means is a PMOS transistor, and the pull-down driver means is an NMOS transistor.

In an integrator for a skip circuit of a rambus DRAM according to the present invention, the pull-up driver means is configured with a current mirror type PMOS transistor, and the pull-down driver means is configured with a current mirror type NMOS transistor.

In an integrator for a skip circuit of a Rambus DRAM according to the present invention, the first and second switching means are PMOS transistors.

In an integrator for a skip circuit of a rambus DRAM according to the present invention, the third and fourth switching means are NMOS transistors.

In the integrator for the skip circuit of the Rambus DRAM according to the present invention, the fifth and sixth switching means are characterized in that the transfer gate consisting of a PMOS transistor and an NMOS transistor.

In an integrator for a skip circuit of a Rambus DRAM according to the invention, the first latch means is characterized in that it consists of two inverters connected in parallel.

In an integrator for a skip circuit of a Rambus DRAM according to the present invention, the second latch means is a flip-flop circuit.

In an integrator for a skip circuit of a rambus DRAM according to the present invention, the equalizing means is constituted by a MOS transistor.

In an integrator for a skip circuit of a Rambus DRAM according to the present invention, the MOS transistor is a PMOS transistor.

1 is a circuit diagram of an integrator for a skip circuit of a Rambus DRAM according to the prior art.

2 is a circuit diagram of an integrator for a skip circuit of a Rambus DRAM according to the present invention.

3 is a waveform diagram of each signal used in the present invention

Explanation of symbols on the main parts of the drawings

1: Delay circuit part 2: D flip-flop circuit part

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In addition, in all the drawings for demonstrating an embodiment, the thing with the same function uses the same code | symbol, and the repeated description is abbreviate | omitted.

FIG. 2 is a circuit diagram illustrating an integrator for a skip circuit of a Rambus DRAM according to the present invention, and a pull-up supplying a pull-up voltage Vdd and a pull-down voltage Vss to a pull-up Nd2 and pull-down Nd3 bias potential, respectively. PMOS transistors P3 and P2 and pull-down N1 and N2 driver means, PMOS transistors P3 for transferring the pull-up bias potential Nd2 to the node Nd4 by the inverted signal of the control signal skipup, and the second The PMOS transistor P4 which transfers the pull-up bias potential Nd2 to the node Nd7 by the inverted signal of the control signal skipDn, and the pull-down bias of the node Nd4 by the control signal skipDn. An NMOS transistor N3 for transferring to the potential Nd3, an NMOS transistor N4 for transferring the signal of the node Nd7 to the pull-down bias potential Nd3 by the control signal skipup, and the node ( The data of Nd4) is stored by the control signals LSB and LS. The transfer gates P5 and N5 for transmitting to the first latch means INV3 and INV4 and the output signal Nd6 of the first latch means INV3 and INV4 are controlled by the control signals LSB and LS. Transfer gates P6 and N6 passing to the node Nd7, second latch means 2 for inputting an inverted signal of the node Nd7 to latch the output signal until data is transferred, and the first It consists of a PMOS transistor P7 which equalizes the potentials of both ends of the first latch means INV3 and INV4 before data is input to the latch means INV3 and INV4. The equalizing signal EQ for controlling the operation of the PMOS transistor P7 performs NAND operation on the inverted signal of the control signal BLatchSkip BLS and the control signal LatchSkip LS.

The integrator of the present invention, as shown, the PMOS transistor (P7) for equalizing the nodes (Nd5 and Nd6) of the first latch circuit (INV3 and INV4), and the first latch circuit (INV3) to remove power consumption And a signal EQ for controlling the operation of the PMOS transistor P7 to equalize both nodes Nd5 and Nd6 of the first latch circuits INV3 and INV4 only for a predetermined time before data is input to INV4. An equalizing signal generator (INV12, NAND1) for generating a is further configured in the conventional integrator circuit.

As in the operation timing shown in FIG. 3, when the control signal BLS becomes 'high', the equalizing signal EQ becomes 'low' to operate the PMOS transistor P7 to thereby operate the first latch circuit part. Both nodes Nd5 and Nd6 of INV3 and INV4 are equalized.

After that, when the control signal LS is in the 'high' state, the equalizing signal EQ is in the 'high' state, ending the equalization, and the voltage difference between the nodes Nd5 and Nd6 of the first latch circuits INV3 and INV4. Is sensed to latch the output signal (skipvalue) in the second latch circuit portion (2).

As described above, the integrator according to the present invention senses data after equalizing after equalizing the voltages of the nodes Nd5 and Nd6 of the first latch circuits INV3 and INV4 before data sensing, so that a small voltage difference can be accurately sensed. It can stabilize the operation.

As described above, according to the integrator for the skip circuit of the Rambus DRAM of the present invention, the data having a small potential difference can be accurately sensed by equalizing and sensing the input node before the data is input. Therefore, the integrator of the present invention can operate stably even for the input of data having a small potential difference.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to various modifications, changes, additions, etc. within the spirit and scope of the present invention, these modifications and changes should be seen as belonging to the following claims. something to do.

Claims (10)

In the integrator for the skip circuit of Rambus DRAM, Pull-up and pull-down driver means for supplying a pull-up voltage and a pull-down voltage respectively with the pull-up and pull-down bias potentials of the integrator; First switching means for transferring the pull-up bias potential to a first node by an inverted signal of a first control signal; Second switching means for transferring the second pull-up bias potential to a second node by an inverted signal of a second control signal; Third switching means for transmitting the signal of the first node to the pull-down bias potential by the second control signal; Fourth switching means for transmitting a signal of the second node to the pull-down bias potential by the first control signal; Fifth switching means for transmitting the signal of the first node to a first latch means for storing data by a third control signal; Sixth switching means for transmitting the output signal of the first latching means to the second node by the third control signal; Second latch means for inputting a signal of the second node to latch an output signal until data is transitioned; And an equalizing means for equalizing a potential of both ends of the first latching means before data is input to the first latching means. The method of claim 1, The pull-up driver means is a PMOS transistor, The integrator for a skip circuit of a Rambus DRAM, wherein the pull-down driver means is an NMOS transistor. The method of claim 1, And the pull-up driver means comprises a PMOS transistor of a current mirror type structure, and the pull-down driver means consists of an NMOS transistor of a current mirror type structure. The method of claim 1, And the first and second switching means are PMOS transistors. The method of claim 1, The integrator for the skip circuit of a Rambus DRAM, wherein said third and fourth switching means are NMOS transistors. The method of claim 1, And the fifth and sixth switching means are transfer gates composed of PMOS transistors and NMOS transistors. The method of claim 1, The integrator for a skip circuit of a rambus DRAM, wherein the first latching means comprises two inverters connected in parallel. The method of claim 1, And said second latching means is a flip-flop circuit. The method of claim 1, An integrator for a skip circuit of a rambus DRAM, characterized in that said equalizing means comprises a MOS transistor. The method of claim 9, The MOS transistor is an integrator for a skip circuit of Rambus DRAM, characterized in that the PMOS transistor.