KR20020032706A - Method of forming a wordline in a flash memory device - Google Patents

Abstract

PURPOSE: A method for forming a word line of a flash memory device is provided to improve an operating speed by smoothing a seam of a tungsten silicide. CONSTITUTION: An isolation layer(22) is formed on a semiconductor substrate(21). A tunnel oxide layer(23) and the first polysilicon layer(24) are formed on a whole surface of the above structure. A photoresist layer is formed on the first polysilicon layer(24). An incline profile pattern is formed by etching the first polysilicon layer(24) and the tunnel oxide layer(23). The patterned photoresist layer is removed. A dielectric layer(26), the second polysilicon layer(27), and a tungsten silicide layer(28) are formed sequentially on the whole surface of the above structure. A control gate is formed by patterning the tungsten silicide layer(28), the second polysilicon layer(27), and the dielectric layer(26). A floating gate is formed by etching the first polysilicon layer(24) and the tunnel oxide layer(23). A word line is formed by laminating the floating gate and the control gate.

Description

Method of forming a wordline in a flash memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a word line forming method of a flash memory device, and more particularly, to forming a second polysilicon film and a tungsten silicide film used as a control gate by forming a first polysilicon film used as a floating gate to have a gradient profile. A word line forming method of a flash memory device capable of preventing the generation of seams in a silicide film.

Since the word line of the flash memory device has a floating gate, the topology is very complicated, and the word line of the flash memory device is very difficult to form due to the step of the first polysilicon film acting as the floating gate. Next, a word line forming method of a conventional flash memory device will be described with reference to FIG. 1 as follows.

After the trench type device isolation layer 12 is formed in a predetermined region on the semiconductor substrate 11, the tunnel oxide layer 13 and the first polysilicon layer 14 are formed on the entire structure. The first polysilicon layer 14 and the tunnel oxide layer 13 are patterned by a lithography process and an etching process using a floating gate mask. At this time, the profile of the floating gate has a vertical and negative profile by using a relatively thin polysilicon film. A dielectric film 15, a second polysilicon film 16, and a tungsten silicide film 17 are formed over the entire structure. The tungsten silicide layer 17, the second polysilicon layer 16, and the dielectric layer 15 are etched by a lithography process and an etching process using a control gate mask to form a control gate, and the first self-aligned etching process is performed. The polysilicon film 14 and the tunnel oxide film 13 are etched to form a floating gate. As a result, a stack gate type word line is formed.

However, in the gate forming process proceeding as described above, a step is present along a narrow space between the first polysilicon films. This lowers the deposition rate of the second polysilicon film and the tungsten silicide film for forming subsequent control gates, causing a seam A to occur in the tungsten silicide film. That is, since the tungsten silicide film is deposited vertically along the topology of the second polysilicon film used as the buffer layer, the tungsten silicide film does not fill a narrow space and a seam is generated. Such a seam will vary depending on the narrow space between the floating gates and the thickness of the second polysilicon film used as the buffer layer. Such a seam increases the resistance of the flash memory device to decrease the speed of the device, which is the biggest problem in the operation of the flash memory device.

However, the seam cannot be fundamentally improved, and the degree of seam is reduced by improving the topology of the first polysilicon film used as the floating gate and the second polysilicon film used as the buffer layer of the control gate. In order to reduce the seam, it is most preferable to planarize the topology of the first polysilicon film used as the floating gate before forming the control gate. However, this also requires a CMP process for planarization, which is difficult to apply due to the problem of process reproducibility and uniformity in the wafer of the first polysilicon film to be CMP. Even if the CMP process is applied, problems such as process TAT, cost increase, and new equipment investment remain.

SUMMARY OF THE INVENTION An object of the present invention is to provide a word line forming method of a flash memory device capable of relieving the core of tungsten silicide to prevent the operation speed of the device from decreasing.

Another object of the present invention is to provide a method of forming a word line of a flash memory device which relieves the core of a tungsten silicide film by improving the profile of the first polysilicon film used as the floating gate to relax the topology.

In the present invention, the topology is relaxed by inclining the profile of the first polysilicon film used as the floating gate, thereby relaxing the core of the tungsten silicide film.

1 is a cross-sectional view of a device for explaining a word line forming method of a conventional flash memory device.

2 (a) to 2 (c) are cross-sectional views of devices sequentially shown for explaining a word line forming method of a flash memory device according to the present invention.

<Explanation of symbols for the main parts of the drawings>

11 and 21: semiconductor substrate 12 and 22: device isolation film

13 and 23: tunnel oxide film 14 and 24: first polysilicon film

15 and 26: dielectric film 16 and 27: second polysilicon film

17 and 28: tungsten silicide film A: shim

25 photosensitive film

A word line forming method of a flash memory device according to the present invention includes forming a tunnel oxide film and a first polysilicon film on a semiconductor substrate on which a device isolation film is formed in a predetermined region, and a photosensitive film having an inclined profile on the first polysilicon film. Forming a pattern, etching the first polysilicon film and the tunnel oxide film using the photosensitive film pattern having the inclined profile as a mask to have the inclined profile, and forming a dielectric film, a second polysilicon film, and tungsten on the entire structure Sequentially forming a silicide layer, sequentially etching the tungsten silicide layer, the second polysilicon layer, and the dielectric layer to form a control gate, and then performing a self-aligned etching process to etch the first polysilicon layer and the tunnel oxide layer. Forming a floating gate by The features.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

2 (a) to 2 (c) are cross-sectional views of devices sequentially shown to explain a word line forming method of a flash memory device according to the present invention.

Referring to FIG. 2A, a trench type isolation layer 22 is formed in a predetermined region on the semiconductor substrate 21. The tunnel oxide film 23 and the first polysilicon film 24 are formed on the entire structure. The photosensitive film 25 is formed on the first polysilicon film 24. The photosensitive film 25 is patterned by an exposure and development process using a floating gate mask, but patterned to have an inclined profile having a predetermined slope.

Referring to FIG. 2B, the first polysilicon layer 24 and the tunnel oxide layer 23 are etched using the photosensitive layer 25 patterned to have the inclined profile as a mask to form a pattern having the inclined profile. At this time, in order to etch the first polysilicon film 24 to have an inclined profile, etching equipment using a plasma of TCP or ICP type is used. At this time, Cl ₂ and N ₂ are introduced into the etching equipment in amounts of 70 to 130 sccm and 5 to 8 sccm, respectively, and 40 to 80 W is applied at a temperature of 20 ° C. or lower and a pressure of 3 to 8 mTorr. When the etching process is performed under these conditions, the polymer generated by etching the first polysilicon film 24 together with damaging the sidewall of the photosensitive film 25 is adsorbed onto the sidewall of the photosensitive film 25. Etching the first polysilicon film 24 at a low etching rate causes the first polysilicon film 24 to have an inclined profile as the adsorption of the polymer due to chemical reaction is activated rather than physical ion sputtering.

Referring to FIG. 2C, after the patterned photoresist layer 25 is removed, the dielectric layer 26 and the second polysilicon layer 27 and the tungsten silicide layer 28 are sequentially formed on the entire structure. At this time, the tungsten silicide film 28 does not generate seams because the topology of the lower first polysilicon film 24 is improved. However, as the design rule is highly integrated, even if the gap between the first polysilicon films 24 is narrowed and a seam is generated in the tungsten silicide film 28, it is not generated to affect the operation of the device. Thereafter, the tungsten silicide layer 28, the second polysilicon layer 27, and the dielectric layer 26 are patterned by a lithography process and an etching process using a control gate mask to form a control gate. The first polysilicon layer 24 and the tunnel oxide layer 23 are etched by a self-aligned etching process to form a floating gate. As a result, a word line in which the floating gate and the control gate are stacked is formed.

As described above, according to the present invention, the core of the tungsten silicide film can be improved without introducing a CMP process, and thus existing equipment can be used without introducing additional processes or introducing additional equipment. In addition, by improving only the profile of the first polysilicon film, there is no major problem in the subsequent process, thereby preventing polysilicon residue and attack occurring in the seam void line of the gate line, which may cause during the gate forming process. Stable In addition, since the area may be improved while the first polysilicon film is formed to have an inclined profile, the electrical reliability of the device may be improved due to the improvement in the coupling ratio.

Claims (3)

Forming a tunnel oxide film and a first polysilicon film on the semiconductor substrate having the device isolation film formed in a predetermined region; Forming a photoresist pattern having an inclined profile on the first polysilicon layer; Etching the first polysilicon film and the tunnel oxide film using the photoresist pattern having the inclined profile as a mask to have an inclined profile; Sequentially forming a dielectric film, a second polysilicon film, and a tungsten silicide film on the entire structure; Forming a control gate by sequentially etching the tungsten silicide layer, the second polysilicon layer, and the dielectric layer, and then performing a self-aligned etching process to etch the first polysilicon layer and the tunnel oxide layer to form a floating gate. And a word line forming method of a flash memory device. The word line forming method of claim 1, wherein the first polysilicon layer patterned to have the inclined profile is formed by an etching process using an etching apparatus using TCP or ICP type plasma. According to claim 2, wherein the etching process is in the amount of 70 to 130sccm and 5 to 8sccm inflow of Cl ₂ and N ₂ , 40 to 80W at a temperature of 20 ℃ or less and the pressure of 3 to 8mTorr A word line forming method of a flash memory device, characterized in that the power is applied.