KR20020020557A - A device of frequency control for wll terminal - Google Patents

Abstract

The present invention relates to a frequency control device for controlling a digital PLL frequency synthesizer for generating intermediate frequencies in a wireless subscriber network terminal, and more particularly, to an apparatus for controlling a transmission / reception frequency by replacing a function of a processor. A control unit for monitoring and controlling the entire terminal and outputting a data signal for controlling a transmission frequency and a reception frequency of a high frequency unit and an address signal to which the data signal is applied; The controller receives a data signal and an address signal output from the controller, outputs a frequency data signal controlling an intermediate frequency for transmission and reception frequencies, a clock signal for operating a transmission and reception high frequency unit, and a selection signal for selecting a transmission and reception frequency synthesis unit. A conversion unit to perform; And a high frequency unit configured to receive a signal output from the conversion unit, generate an intermediate frequency for transmission and an intermediate frequency for reception, and control a transmission frequency and a reception frequency. By performing other control of, there is an industrial and industrial use effect to improve the reliability of the terminal and to enhance the function.

Description

Frequency control device of wireless subscriber network terminal {A DEVICE OF FREQUENCY CONTROL FOR WLL TERMINAL}

The present invention relates to a frequency control device for controlling a digital PLL frequency synthesizer for generating an intermediate frequency (IF) in a wireless local loop (WLL) terminal. It relates to a device to.

A wireless subscriber network (WLL) system is a full duplex communication system capable of transmitting and receiving at the same time. The WLL system is divided into a transmitter unit, a receiver unit, a baseband unit, and the like. After up-converting, the transmitter transmits and outputs a high frequency (RF) signal, and the receiver outputs a base band signal after down-converting the received signal at high frequency (RF).

A wireless subscriber network (WLL) system utilizes a cellular mobile communication system that provides two-way mobile communication service using multiple communication channels. The WLL system not only has different transmit and receive channel frequencies, but also occupies the communication state. There is a characteristic that the frequency of each transmit and receive channel may change from time to time.

The transmitter or transmitter high frequency unit (TXRF) and the receiver or receiver high frequency unit (RXRF) comprise a digital phase locked loop (PLL) frequency synthesizer that generates an intermediate frequency (IF) signal for a corresponding up-modulation and down-modulation function. Each is required.

As described above, the digital PLL frequency synthesizer is directly controlled by a control unit in order to quickly respond to a frequency change of a communication channel for transmission / reception, which is frequently changed due to system characteristics, and the controller has a relatively high operation clock time. The direct control of the late digital PLL frequency synthesizer requires a large number of clock times or cycles to be allocated, causing a load on the controller.

Hereinafter, a frequency control apparatus of a wireless subscriber network terminal according to the prior art will be described.

Attached to explain the prior art, FIG. 1 is a functional block diagram of a frequency control device of a wireless subscriber network terminal according to the prior art, and FIG. 2 is a timing diagram of a frequency control device according to the prior art.

Referring to FIG. 1, the wireless subscriber network frequency control apparatus according to the prior art monitors and controls the entire apparatus, and includes a first enable (ENA1) signal, a second enable (ENA2) signal, and a digital frequency synthesizer. A control unit 10 for outputting control data PLL_DATA and a digital frequency synthesizer control clock PLL_CLK;

A receiving high frequency unit 20 for receiving a corresponding high frequency (RF) signal of a wireless subscriber network and down-modulating the base band signal and outputting the base band signal;

A first frequency synthesizing unit 30 for outputting a corresponding intermediate frequency signal for down-modulating the reception high frequency unit 20 according to a control signal of the control unit 10;

A transmission high frequency unit 40 receiving a baseband signal, up-modulating the corresponding high frequency signal of the wireless subscriber network, and outputting the same;

A second frequency synthesizing unit 50 for outputting a corresponding intermediate frequency signal which causes the transmission high frequency unit 40 to up-modulate according to a control signal of the control unit 10;

The high frequency signal output from the transmitting high frequency unit 40 is output through the antenna, and the high frequency signal received through the antenna is configured as a duplexer 60 to be applied to the receiving high frequency unit 20.

Hereinafter, an apparatus for controlling a frequency of a wireless subscriber network terminal according to the related art having the above configuration will be described in detail with reference to the accompanying drawings.

Since the wireless subscriber network (WLL) system is a full-duplex wireless communication system, the transmission frequency and the reception frequency are different from each other, and also a cellular method for improving frequency efficiency, and the transmission and reception frequencies are frequently changed during communication.

In order to change the transmission and reception frequency as described above, the intermediate frequency (IF) should be changed. Since the change of the intermediate frequency is unspecifically changed according to the system operating state, the control of the controller 10 is directly controlled. Should receive

The control unit 10 monitors and controls each function unit and at the same time selects a signal (ENA1) for controlling the first frequency synthesizing unit 30 to receive data; A selection signal ENA2 for controlling the second frequency synthesizer 50 to receive data; A data signal PLL_DATA for controlling an intermediate frequency synthesized by the first and second frequency synthesizing units 30 and 50; The clock signal PLL_CLK, which is an operation reference of the first and second frequency synthesizing units 30 and 50, is output. The interoperation relationship between the signals is shown in detail in FIG. 2.

Referring to FIG. 2, the operation of each functional unit will be described. For example, when a communication channel is changed due to a change in operating environment of a WLL system, a transmission frequency and a reception frequency are simultaneously changed.

As soon as the control unit 10 recognizes the change of the communication channel as described above, the control unit 10 controls to change the frequencies of the reception high frequency unit 20 and the transmission high frequency unit 40.

As an example, when the reception frequency of the reception high frequency unit 20 is changed, the controller 10 outputs the corresponding data signal PLL_DATA, and the data signal PLL_DATA is the first frequency synthesizer ( 30) and the second frequency synthesizer 50 at the same time.

The first frequency synthesizing unit 30 and the second frequency synthesizing unit 50 temporarily store the data signal PLL_DATA applied from the control unit 10 in an internal input buffer, and then a selection signal is applied. Read only if

According to the above example, the controller 10 outputs a control signal ENA1 for selecting the first frequency synthesizer 30 and receives the first frequency synthesizer 30 to which the control signal ENA1 is applied. ) Reads the data signal PLL_DATA temporarily stored in the internal input buffer, generates a corresponding intermediate frequency IF, and outputs it to the reception high frequency unit 20, thereby receiving a signal having the corresponding frequency.

When the above process is completed, the controller 10 should also change the transmission frequency due to the channel change, and thus outputs the corresponding data signal PLL_DATA, and the data signal PLL_DATA as described above is the first frequency synthesizer 30. And read only from the second frequency combining unit 50 by the control signal ENA2 applied to the second frequency combining unit 50 and selecting the second frequency combining unit 50, and corresponding intermediate frequency IF. ).

The second frequency synthesizing section 50 outputs the intermediate frequency IF generated by the change to the transmitting high frequency section 40, so that the transmitting high frequency section 40 transmits through the changed channel to communicate.

As a data signal output from the controller to control the first frequency synthesizer 30 and the second frequency synthesizer 50, for example, each of 22 bits (Bit) is used, and thus a total of 44 bits are used. shall.

In addition, as an example, the clock frequency used by the controller 10 is 50 MHz, and the clock frequencies used by the first frequency synthesizer 30 and the second frequency synthesizer 50 are 1 MHz or less.

Accordingly, the control unit 10 does not perform other operations for many cycles and applies 22 bits to apply the control signal of 1 bit to the first frequency synthesizer 30 or the second frequency synthesizer 50. In order to apply all of the data signals of, the other operation cannot be performed for hundreds or thousands of cycles, and in order to control both the first frequency synthesizer 30 and the second frequency synthesizer 50, There is an inefficient problem that prevents you from doing anything else for thousands of cycles.

In addition, after controlling the first and second frequency synthesizing units 30 and 50 as described above, the next operation waiting is to be performed, so that the load of the control unit 10 becomes very large. there was.

SUMMARY OF THE INVENTION An object of the present invention is to provide a converter that reduces the load of the control unit by receiving only a data signal and an address signal from the control unit and generating a signal for controlling the frequency synthesizer, a signal selected, and an operation clock signal, respectively.

The present invention devised to achieve the above object, in the wireless subscriber network terminal, the data signal for controlling the transmission frequency and the reception frequency of the high-frequency unit and the address to which the data signal is applied while monitoring and controlling the entire terminal; A control unit for outputting a signal; The controller receives a data signal and an address signal output from the controller, outputs a frequency data signal controlling an intermediate frequency for transmission and reception frequencies, a clock signal for operating a transmission and reception high frequency unit, and a selection signal for selecting a transmission and reception frequency synthesis unit. A conversion unit to perform; And a high frequency unit configured to receive a signal output from the converter and generate an intermediate frequency for transmission and an intermediate frequency for reception to control the transmission frequency and the reception frequency.

1 is a functional block diagram of a frequency control apparatus for a wireless subscriber network terminal according to the prior art;

2 is a timing diagram of a frequency control apparatus according to the prior art,

3 is a functional block diagram of a wireless subscriber network terminal frequency control apparatus according to the present invention;

4 is a timing diagram of a signal according to the present invention;

5 is a detailed functional block diagram of a conversion unit according to the present invention;

** Explanation of symbols on the main parts of the drawing **

10,70 control unit 20 receiving high frequency unit

30: first frequency synthesizer 40: transmission high frequency unit

50: second frequency synthesizer 60: duplexer

80: conversion unit 90: high frequency unit

Hereinafter, a frequency control apparatus for a wireless subscriber station terminal according to the present invention will be described with reference to the accompanying drawings.

3 is a functional block diagram of a radio subscriber network terminal frequency control apparatus according to the present invention, FIG. 4 is a timing diagram of a signal according to the present invention, and FIG. Detailed functional block diagram of the conversion unit according to the invention technology,

3 to 5, the apparatus for controlling a frequency of a wireless subscriber network terminal according to the present invention, in the wireless subscriber network (WLL) terminal, monitors and controls the entire terminal and at the same time the high frequency unit 90 A control unit 70 for outputting a data signal Data for controlling a transmission frequency and a reception frequency of the signal and an address signal to which the data signal Data is to be applied;

A frequency data signal PLL_DATA for receiving the data signal Data and the address signal Address output from the control unit 70 and controlling the intermediate frequency IF for transmission and reception frequencies, and a transmission / reception high frequency unit 20, Outputting the clock signal PLL_CLK for operating 40 and the first and second selection signals ENA1 and ENA2 for selecting the transmit and receive frequency synthesizing units 30 and 50 from the control unit 70. The data signal Data and the address signal Address are received and interpreted to output a first selection signal ENA1, a second selection signal ENA2, and a clock signal CLK, and at the same time, the data signal Data An analysis unit 81 for dividing the output into 8 bit units and outputting the divided outputs; First, second, and third buffers 82, 83, and 84 which are divided into 8-bit units from the analysis unit 81 and receive and store data output in parallel; First to third shift registers (85,86,87) for receiving signals output from the plurality of buffers (82,83,84), respectively, and converting the signals into serial signals; Receives and counts the clock signal CLK output from the analyzer 81 to operate the plurality of shift registers 85, 86, and 87 in order to operate the high frequency unit 90. A counter 88 for outputting a high frequency clock signal PLL_CLK; A conversion consisting of a mux section 89 which receives the serial data sequentially from the plurality of shift registers 85, 86, and 87 according to the signal output from the counter 88 and outputs it as a frequency data signal PLL_DATA. Section 80,

It is configured to include a high frequency unit 90 that receives the signal output from the conversion unit 80, generates a transmission intermediate frequency (IF) and a reception intermediate frequency (IF) to control the transmission frequency and the reception frequency. .

Hereinafter, with reference to the accompanying drawings, a frequency control apparatus for a wireless subscriber network terminal according to the present invention having the above configuration will be described in detail.

Cellular wireless subscriber network system that can perform simultaneous two-way communication wirelessly by using full duplex communication method, and maximize utilization efficiency of limited frequency resources. Used by dividing into multiple channels with regular intervals.

The terminal communicating using the channel initially allocated by the wireless subscriber network system checks the frequency environment of the other channel of the cell, and if the received signal strength and sensitivity are better than the frequency environment of the channel currently being communicated with, By changing to an excellent channel and proceeding with communication, it automatically secures excellent communication quality.

Therefore, since the communication channel is automatically changed from time to time in the wireless subscriber network, the terminal should automatically tune to the transmission and reception frequency of the corresponding channel.

The wireless subscriber network terminal is a state in which the controller 70 recognizes a new channel set at the beginning of operation or a channel changed during communication operation by data communication with a base station not shown in the drawing, and is set as described above. Alternatively, the transmitting high frequency unit 40 and the receiving high frequency unit 20 of the high frequency unit 90 should be controlled by the changed channel.

For the above control, the signal output from the control unit 70, for example, to control the frequency of the transmission and reception high frequency unit 40, 20, 22 bits (Bit) data signal (Data), and The 22-bit data signal Data is output to the converter 80 to control the output signal 40 to be transmitted to the transmit high frequency unit 40 or the receive high frequency unit 20.

The conversion unit 80 receives a 22-bit data signal Data and an address signal through the analysis unit 81, and the analysis unit 81 analyzes and receives an address signal. If it is a signal for controlling the frequency of the high frequency unit 20, the first selection signal (ENA1) is output, and if it is a signal for controlling the frequency of the transmission high frequency unit 40, the second selection signal (ENA2) and at the same time output The clock CLK signal is output and applied to the counter 88.

The counter 88 is a control signal for processing the applied clock (CLK) signal to operate the plurality of shift registers (85, 86, 87) in sequence, and the specified shift register by controlling the mux (89). 85, 86 and 87, a signal for receiving the signal output from the high frequency unit 90, the high frequency unit clock signal (PLL_CLK) for operating the first frequency synthesizer 30 and the second frequency synthesizer 50 )

In addition, the analyzer 81 divides the received 22-bit data signal Data by 8 bits and applies them to the first to third buffers 82, 83, and 84 as parallel signals, respectively.

Accordingly, the first buffer 82 and the second buffer 83 receive an 8-bit parallel data signal, and the third buffer 84 receives 6-bit parallel data. You will receive a signal.

The first shift register 85 connected to the first buffer 82 receives 8-bit parallel data, converts the serial data into serial data, and stores the converted data. The first shift register 85 is connected to the second buffer 83. The 2 shift register 86 also receives 8 bits of parallel data, converts it into serial data, and stores it. A third shift register 87 connected to the third buffer 84 receives 6 bits of parallel data and receives 6 bits of parallel data. Convert to serial data and save it.

Each of the shift registers 85, 86, and 87 outputs serial data stored by the control signal applied from the counter 88 to the mux 89, and the mux 89 is applied from the counter 88. The signal output from the shift registers 85, 86, and 87 is received by the corresponding control signal.

In more detail, when the counter 88 attempts to output serial data stored in the first shift register 85, the counter 88 outputs a control signal to the first shift register 85 and the mux 89. Also, a control signal is output so that only a signal output from the first shift register 85 is input.

When the signals stored in the second and third shift registers 86 and 87 are outputted, the same process is performed as described above.

The signal output from the conversion unit 80 as described above is input to the high frequency unit 90.

The first selection signal ENA1 output from the conversion unit 80 is input to the first frequency synthesis unit 30 of the high frequency unit 90, and the second selection signal ENA2 is connected to the second frequency synthesis unit ( 50 is input to the frequency data signal PLL_DATA and the high frequency part clock signal PLL_CLK to the first frequency synthesizer 30 and the second frequency synthesizer 50 at the same time.

The first frequency synthesizer 30 and the second frequency synthesizer 50 receive an input without being influenced by an external control signal in the case of the high frequency clock signal PLL_CLK, but the frequency data signal PLL_DATA signal may be It is input only when the first and second selection signals ENA1 and ENA2 are applied.

Referring to FIG. 4, in detail, when the first selection signal ENA1 is output from the converter 80, the frequency data signal PLL_DATA is the first frequency synthesizer 30. ) Is inputted only and the second selection signal ENA2 is output from the converter 80, the frequency data signal PLL_DATA is inputted and processed only by the second frequency synthesizer 50.

That is, when the first selection signal ENA1 is applied to the high frequency unit 90, the first frequency synthesizing unit 30 receives the frequency data signal PLL_DATA and processes the data signal to the intermediate frequency. By generating (IF) and outputting to the reception high frequency unit 20, a high frequency signal of a corresponding frequency is received, down-converted and output as a base band signal as a base band signal, not shown in the drawing. Done.

In addition, when the second selection signal ENA2 is applied, the frequency data signal PLL_DATA is input from the second frequency synthesizing unit 50 of the high frequency unit 90, and the intermediate frequency ( By generating IF) and outputting to the transmitting high frequency unit 40, the baseband signal is up-converted to a high frequency signal of a corresponding frequency and applied to the duplexer 60 and output through the antenna.

According to the present invention having the above configuration, the first frequency synthesizer 30 and the second frequency synthesizer 50 of the high frequency unit 90 are not directly controlled by the control unit 70, and thus, the control unit 70. Since only outputs the address signal (Data) and the data signal (Data), and can perform other control operations, the load is reduced and the reliability of the wireless subscriber network terminal is improved.

According to the present invention having the configuration described above, the control unit only outputs a data signal and an address signal for controlling the transmission / reception channel frequency of the high frequency unit, and then generates and applies the corresponding clock signal and control signal by the conversion unit. It is effective to alleviate.

In addition, the control unit has an industrial and industrial use effect of improving the reliability and enhancing the function of the terminal by performing other control of the terminal.

Claims (2)

In the wireless subscriber network terminal, A control unit for monitoring and controlling the entire terminal and outputting a data signal for controlling a transmission frequency and a reception frequency of a high frequency unit and an address signal to which the data signal is applied; The controller receives a data signal and an address signal output from the controller, outputs a frequency data signal controlling an intermediate frequency for transmission and reception frequencies, a clock signal for operating a transmission and reception high frequency unit, and a selection signal for selecting a transmission and reception frequency synthesis unit. With conversion part to say, A frequency control device for a wireless subscriber network terminal, comprising: a high frequency unit configured to receive a signal output from the conversion unit, generate an intermediate frequency for transmission and an intermediate frequency for reception, and control a transmission frequency and a reception frequency. According to claim 1, The converting unit analyzes the data signal and the address signal applied from the controller, and outputs the first selection signal, the second selection signal, and the clock signal, and simultaneously divides the data signal into 8 bit units and outputs the data signal. Wealth, A plurality of buffers which receive data which is divided into 8-bit units from the analysis unit and are temporarily stored; A plurality of shift registers each receiving signals output from the plurality of buffers and converting the signals into serial signals; A counter which receives and counts a clock signal output from the analyzing unit, and outputs a signal for controlling the plurality of shift registers in order to output the high frequency unit clock signal for operating the high frequency unit; Frequency control device for a wireless subscriber network terminal comprising a mux unit for receiving serial data sequentially from the plurality of shift registers by a signal output from the counter and outputting the serial data as a frequency data signal.