KR20020015214A - Semiconductor package - Google Patents

Abstract

The present invention relates to a semiconductor package, in which semiconductor chips can be stacked without being limited in size, and also have a first surface and a second surface so as not to cause any damage to conductive wires when the semiconductor chips are stacked. A first semiconductor chip having a plurality of input / output pads formed on a surface thereof; A second semiconductor chip having a first surface and a second surface, wherein a plurality of input / output pads are formed on the second surface, the first surface facing the second surface of the first semiconductor chip; A substrate that is bonded to the first surface of the first semiconductor chip and has a plurality of circuit patterns formed on the first and second surfaces of the resin layer having a first surface and a second surface; A plurality of conductive wires electrically connecting the input / output pads of the first semiconductor chip and the second semiconductor chip and the circuit patterns of the substrate; An adhesive layer bonded between the second surface of the first semiconductor chip and the first surface of the second semiconductor chip, the adhesive layer being thicker than the loop height of the conductive wire connected to the input / output pad of the first semiconductor chip; An encapsulant for encapsulating one surface of the first semiconductor chip, the second semiconductor chip, the conductive wire, and the substrate; It characterized in that it comprises a conductive ball connected to each borland of the substrate.

Description

Semiconductor Package {Semiconductor package}

The present invention relates to a semiconductor package, and more particularly, to a stacked semiconductor package in which a plurality of semiconductor chips are stacked on each other.

In general, the semiconductor package not only protects the semiconductor chip from the external environment, but also means that the electrical signal between the semiconductor chip and the motherboard is easily exchanged.

Recently, a multilayer semiconductor package having high functionality by stacking a plurality of semiconductor chips inside the semiconductor package has been released. Such a conventional multilayer semiconductor package 100 'is shown in FIG.

As shown, a circuit pattern 20 'having a bond finger 20a' and a borland 20b 'is formed on the upper and lower surfaces of the resin layer 18', and the circuit pattern 20 'is formed. The surface of the circuit board 16 'is coated with a cover coat 23'. In addition, the first semiconductor chip 2 'is bonded to the center of the upper surface of the circuit board 16' by the adhesive layer, and the second semiconductor chip 6 'is bonded to the upper surface of the first semiconductor chip 2'. It is bonded together. Of course, a plurality of input / output pads 4 'and 8' are formed on the upper surfaces of the first semiconductor chip 2 'and the second semiconductor chip 6'. The I / O pads 4 'and 8' of the first semiconductor chip 2 'and the second semiconductor chip 6' are bonded fingers 20a 'of the circuit patterns 20' formed on the circuit board 16 ', respectively. ) Is connected to the conductive wire 60 '. In addition, the upper surface of the first semiconductor chip 2 ', the second semiconductor chip 6', the conductive wire 60 ', and the circuit board 16' is sealed with an encapsulant 40 '. A plurality of conductive balls 50 'are fused to the ball lands 20b' among the circuit patterns 20 'formed on the bottom surface of the circuit board 16', and the conductive balls 50 'are subsequently fixed on the motherboard. Is connected to the pattern. In the figure, reference numeral 20c 'denotes a conductive via hole.

In the semiconductor package 100 ', the electrical signals of the first semiconductor chip 2' and the second semiconductor chip 6 'are transmitted to the conductive wire 60', the bond finger 20a 'of the circuit board 16', It is exchanged with the motherboard through the conductive via hole 20c ', the borland 20b', and the conductive ball 50 ', and since the two semiconductor chips are stacked, the semiconductor package can have high capacity, high functionality, and high mounting density. There is an advantage.

However, in order to avoid contact with conductive wires connected to the input / output pads of the first semiconductor chip, an area or volume of the second semiconductor chip must be smaller than the width or volume of the first semiconductor chip. That is, when the volume of the second semiconductor chip is equal to or larger than the volume of the first semiconductor chip, the bottom surface of the second semiconductor chip and the conductive wire are shorted to each other, thereby causing paralysis of the electrical function of the first semiconductor chip. On the contrary, the size of the second semiconductor chip should be smaller than that of the first semiconductor chip.

This problem is applicable to a memory semiconductor package (for example, a semiconductor package in which a plurality of DRAMs are stacked) in which a plurality of semiconductor chips of the same size must be stacked.

If the size of the second semiconductor chip is larger than the size of the first semiconductor chip, it cannot be applied at all, and the type of semiconductor chips that can be packaged is extremely limited.

Accordingly, the present invention has been made to solve the above-mentioned conventional problems, and to provide a semiconductor package that can be stacked without being limited to the size of the semiconductor chip.

It is another object of the present invention to provide a semiconductor package in which no damage occurs to the conductive wires even if the size of the semiconductor chip is the same or larger.

1 is a cross-sectional view showing a conventional semiconductor package.

2 to 6 are cross-sectional views showing semiconductor packages according to the first to fifth embodiments of the present invention.

-Description of the main symbols in the drawings-

101-105; Semiconductor package according to the present invention

One; First semiconductor chip 1a, 2a, 11a; Front page

1b, 2b, 11b; Second page 1c, 2c; I / O pad

2; Second semiconductor chip 3; Stud bump

10; Suprate 11; Resin layer

12; Circuit pattern 12a; Bondfinger

12b; Borland 13; Via Hole

14; Covercoat 20; Adhesive layer

30; Coating layer 40; Conductive Wire

50; Encapsulant 60; Conductive ball

In order to achieve the above object, the semiconductor package according to the present invention includes a first semiconductor chip having a first surface and a second surface, and a plurality of input / output pads formed on the second surface; A second semiconductor chip having a first surface and a second surface, wherein a plurality of input / output pads are formed on the second surface, the first surface facing the second surface of the first semiconductor chip; A substrate that is bonded to the first surface of the first semiconductor chip and has a plurality of circuit patterns formed on the first and second surfaces of the resin layer having a first surface and a second surface; A plurality of conductive wires electrically connecting the input / output pads of the first semiconductor chip and the second semiconductor chip and the circuit patterns of the substrate; An adhesive layer bonded between the second surface of the first semiconductor chip and the first surface of the second semiconductor chip, the adhesive layer being thicker than the loop height of the conductive wire connected to the input / output pad of the first semiconductor chip; An encapsulant for encapsulating one surface of the first semiconductor chip, the second semiconductor chip, the conductive wire, and the substrate; It characterized in that it comprises a conductive ball connected to each borland of the substrate.

In addition, another semiconductor package according to the present invention to achieve the above object has a first surface and a second surface, the second surface and the first semiconductor chip is formed with a plurality of input and output pads; A second semiconductor chip having a first surface and a second surface, wherein a plurality of input / output pads are formed on the second surface, the first surface facing the second surface of the first semiconductor chip; A substrate that is bonded to the first surface of the first semiconductor chip and has a plurality of circuit patterns formed on the first and second surfaces of the resin layer having a first surface and a second surface; A plurality of conductive wires electrically connecting the input / output pads of the first semiconductor chip and the second semiconductor chip and the circuit patterns of the substrate; A coating layer coated on a second surface of the first semiconductor chip; An encapsulant for encapsulating one surface of the first semiconductor chip, the second semiconductor chip, the conductive wire, and the substrate; It characterized in that it comprises a conductive ball connected to each borland of the substrate.

Here, the size of the second semiconductor chip may correspond to any one of smaller, equal, or larger than the size of the first semiconductor chip.

The semiconductor package for achieving the second object may be the adhesive layer is interposed on the surface of the coating layer coated on the second surface of the first semiconductor chip may be bonded to the first surface of the second semiconductor chip.

The conductive wire may be a coated wire coated with a resin.

The substrate may be one of a printed circuit board, a circuit tape, and a circuit film.

The adhesive layer may be any one of an epoxy resin, a film adhesive, or a double-sided adhesive.

The adhesive layer may be formed in a substantially rectangular lattice form between the second surface of the first semiconductor chip and the first surface of the second semiconductor chip.

The semiconductor package for achieving the second object may be formed by coating the coating layer on the entire conductive wire connected to the first semiconductor chip and the input and output pads of the first semiconductor chip, the coating layer is preferably formed of a liquid encapsulation material Do.

As described above, the semiconductor package according to the present invention has an effect of minimizing damage to the conductive wire because an adhesive layer or coating layer larger than the loop height of the conductive wire is formed between the first semiconductor chip and the second semiconductor chip.

In addition, since various sizes of semiconductor chips can be stacked regardless of the size of the semiconductor chips, there is no difficulty in the arrangement of semiconductor chips, and the degree of freedom in designing the patterns is increased.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings such that those skilled in the art can easily implement the present invention.

First, the semiconductor packages 101 and 102 according to the first and second embodiments of the present invention will be described with reference to FIGS. 2 and 3.

As illustrated, the first semiconductor chip 1 has a first plane 1a and a second plane 1b that are substantially planar, and a plurality of input / output pads 1c are formed near the inner circumference of the second surface 1b. ) Is provided.

An adhesive layer 20 having a predetermined thickness (5 mil or less) is formed on the second surface 1b of the first semiconductor chip 1, and the adhesive layer 20 may include a loop height of a conductive wire 40 to be described below. Loop Height, the height from the second surface 1b of the first semiconductor chip 1 to the highest bending point of the conductive wire 40).

As shown in FIG. 2, the adhesive layer 20 is bonded to the entire second surface 1b of the first semiconductor chip 1, that is, the entire second surface 1b including the input / output pad 1c. The pad 1c is positioned inside the adhesive layer 20. Of course, the conductive wire 40 connected to the input / output pad 1c is also positioned inside the adhesive layer 20.

In addition, the adhesive layer 20 may be formed only near the region where the input / output pad 1c of the first semiconductor chip 1 is formed. That is, it may be formed only along the input / output pad 1c of the first semiconductor chip 1.

As the adhesive layer 20, a conventional epoxy adhesive, a film adhesive, or a double-sided adhesive may be used, but the material of the adhesive layer 20 is not limited thereto.

In addition, the first surface 2a and the second surface 2b are substantially planar, and a plurality of input / output pads 2c are formed near the inner circumference of the second surface 2b, and the first surface ( 2a) is provided with a second semiconductor chip (2) bonded to the adhesive layer (20).

Here, the adhesive layer 20 which bonds the first semiconductor chip 1 and the second semiconductor chip 2 to each other may be filled with a plurality of non-conductive, granular spacers. When the plurality of spacers are filled in the adhesive layer 20 as described above, the second semiconductor chip 2 may be horizontally bonded to the first semiconductor chip 1. That is, since the adhesive layer 20 has a certain degree of elasticity, the second semiconductor chip 2 may be attached to the first semiconductor chip 1 while being skewed, but the adhesive layer 20 filled with the spacer prevents the same. Do it.

Meanwhile, the size or volume of the second semiconductor chip 2 may be smaller than, equal to, or larger than the size or volume of the first semiconductor chip 1. The reason for stacking the second semiconductor chip 2 of various sizes on the first semiconductor chip 1 is because the thickness of the adhesive layer 20 is larger than the loop height of the conductive wire 40 as described above. This is because the wire 40 and the first surface 2a of the second semiconductor chip 2 are not shorted to each other.

Subsequently, on the first surface 1a of the first semiconductor chip 1, the circuit pattern 12 is formed on both surfaces of the resin layer 11 having the first surface 11a and the second surface 11b. Is formed, and the substrate 10 is bonded.

The substrate 10 may include a conventional printed circuit board, a circuit film, a circuit tape, a lead frame, or the like. Here, the printed circuit board may be used. It demonstrates as an example. However, the substrate 10 is not limited to the printed circuit board.

The substrate 10 includes a circuit pattern 12 including conductive ball lands 12b on the first surface 11a around the resin layer 11 having the first surface 11a and the second surface 11b. Is formed, and the circuit pattern 12 including the bond finger 12a is formed on the second surface 11b. Of course, all surfaces except for the bond finger 12a and the ball land 12b are coated by an insulating cover coat 14, and the bond finger 12a and the ball land 12b penetrate the resin layer 11. The conductive via holes 13 are connected to each other.

Bond fingers 12a of the circuit patterns 12 of the input / output pads 1c and 2c of the first semiconductor chip 1 and the second semiconductor chip 2 and the substrate 10 may be formed of gold wire or au wire. They are interconnected by conductive wires 40 such as aluminum wires.

In addition, the conductive wire 40 is a conductive wire 40 and the semiconductor chip (1, 2) by using a coated wire coated with an insulating polymer resin (eg, polyimide) on the surface (not shown) Alternatively, the shorting problem between the conductive wires 40 may be completely solved.

2 and 3, the loop height of the conductive wire 40 is preferably formed very close to the surfaces of the first semiconductor chip 1 and the second semiconductor chip 2.

Thus, the method of forming the loop height of the conductive wire 40 small can be performed by using a conventional reverse wire bonding, edge bonding, or the like.

An example of the reverse wire bonding method is briefly described as follows.

First, on the input / output pads 1c and 2c of the first semiconductor chip 1 or the second semiconductor chip 2, the stud bump 3 (Stud Bump) is formed with the conductive wire 40 first. After forming, the end of the conductive wire 40 is cut off. Next, one end of the conductive wire 40 is first bonded to the bond finger 12a of the substrate 10, and the other end thereof is an input / output pad of the first semiconductor chip 1 or the second semiconductor chip 2. Stitch bonding (also called Stitch bonding, Second Bonding) is performed on the stud bump 3 formed on 2c). The reverse wire bonding uses a capillary used during thermosonic Au ball bonding (a method of bonding heat by bonding heat to an area to be bonded simultaneously with ultrasonic energy during bonding).

In addition, instead of the reverse wire bonding, an end of the conductive wire 40 is edged or ribboned on the input / output pads 1c and 2c of the first semiconductor chip 1 or the second semiconductor chip 2. ) There is also a method of bonding and connecting. The edge or ribbon bonding method is conventionally known as Ultrasonic Al Wedge Bonding (Ultrasonic Al Wedge Bonding, a method of bonding only the ultrasonic vibration energy to the edge and bonding the frictional heat to the first and second bonding areas are formed in the edge shape) Use the edge used for.

By this bonding method, the loop height of the conductive wire 40 can be formed from a maximum of 5 mils to a minimum of 1 mil (1 mil = 0.0254 mm).

Of course, in addition to the reverse wire bonding, edge bonding, and ribbon bonding methods, a conventional normal wire bonding method may also be used. When the normal wire bonding method is used as described above, the thickness of the adhesive layer 20 may be changed. It should be thicker.

Subsequently, the whole of the first semiconductor chip 1, the second semiconductor chip 2, the conductive wire 40 and the second surface 11b of the substrate 10 may be formed of an epoxy molding compound or a liquid phase. It is encapsulated with an encapsulant 50 such as an encapsulant (Glop Top) to be protected from the external environment.

In addition, conductive balls 60 such as solder balls are welded to the ball lands 12b of the circuit patterns 12 formed on the first surface 11a of the substrate 10 so that the mother boards are connected to each other. It is possible to mount on a predetermined pattern.

4 to 6 are cross-sectional views showing semiconductor packages 103, 104, and 105 according to the third to fifth embodiments of the present invention.

Since the third to fifth embodiments are similar to the semiconductor packages 101 and 102 according to the first and second embodiments described above, only the differences will be described so as not to obscure the subject matter of the present invention.

4 and 5, a coating layer 30 and an adhesive layer 20 are formed between the first semiconductor chip 1 and the second semiconductor chip 2. The coating layer 30 is larger than the loop height of the conductive wire 40 connected to the input / output pad 1c of the first semiconductor chip 1 as shown in FIG. 4 or as shown in FIG. 5. It may be set to a thickness (5 mil or less) that covers only the pad 1c.

Subsequently, the second semiconductor chip 2 may be stacked on the coating layer 30 via the adhesive layer 20.

On the other hand, the coating layer 30 as described above may be made of a conventional insulating polymer resin, for example, a resin such as polyimide, and may also use a conventional liquid sealing material.

When the coating layer 30 is used as described above, the crack of the first semiconductor chip 1 when the second semiconductor chip 2 is adhered to the second surface 1b of the first semiconductor chip 1. ) And cracks due to impact can be prevented.

In addition, according to the semiconductor package 105 according to the fifth embodiment of the present invention shown in FIG. 6, the coating layer 30 may include the first semiconductor chip 1 and the input / output pad 1c of the first semiconductor chip 1. It may also be formed on the entire conductive wire 40 connected to it. At this time, it is preferable that the coating layer 30 uses a liquid encapsulant. When the coating layer 30 is formed using the liquid encapsulant as described above, since the coating layer 30 has some viscosity, the second semiconductor chip 2 is adhered to the coating layer 30, and wire bonding is performed. The semiconductor package may be provided in a stacked structure. Of course, the conductive wire 40 connected to the coating layer 30, the second semiconductor chip 2, and its input / output pad 2c is encapsulated by an encapsulant 50 such as an epoxy molding compound.

As described above, although the present invention has been described with reference to the above embodiments, the present invention is not limited thereto, and various modifications may be made without departing from the scope and spirit of the present invention.

Therefore, the semiconductor package according to the present invention has an effect of minimizing damage to the conductive wire because an adhesive layer or coating layer larger than the loop height of the conductive wire is formed between the first semiconductor chip and the second semiconductor chip.

In addition, since various sizes of semiconductor chips can be stacked regardless of the size of the semiconductor chips, there is no difficulty in arranging semiconductor chips, and the degree of freedom in designing the pattern of the substrate is also increased.

In addition, when a coating layer made of a liquid encapsulant is used, since the coating layer itself is viscous, there is an effect that the second semiconductor chip can be directly stacked on the coating layer without a separate adhesive layer.

Claims (10)

A first semiconductor chip having a first surface and a second surface and having a plurality of input / output pads formed thereon; A second semiconductor chip having a first surface and a second surface, wherein a plurality of input / output pads are formed on the second surface, the first surface facing the second surface of the first semiconductor chip; A substrate that is bonded to the first surface of the first semiconductor chip and has a plurality of circuit patterns formed on the first and second surfaces of the resin layer having a first surface and a second surface; A plurality of conductive wires electrically connecting the input / output pads of the first semiconductor chip and the second semiconductor chip and the circuit patterns of the substrate; An adhesive layer bonded between the second surface of the first semiconductor chip and the first surface of the second semiconductor chip, the adhesive layer being thicker than the loop height of the conductive wire connected to the input / output pad of the first semiconductor chip; An encapsulant for encapsulating one surface of the first semiconductor chip, the second semiconductor chip, the conductive wire, and the substrate; A semiconductor package comprising conductive balls connected to each borland of the substrate. A first semiconductor chip having a first surface and a second surface and having a plurality of input / output pads formed thereon; A second semiconductor chip having a first surface and a second surface, wherein a plurality of input / output pads are formed on the second surface, the first surface facing the second surface of the first semiconductor chip; A substrate that is bonded to the first surface of the first semiconductor chip and has a plurality of circuit patterns formed on the first and second surfaces of the resin layer having a first surface and a second surface; A plurality of conductive wires electrically connecting the input / output pads of the first semiconductor chip and the second semiconductor chip and the circuit patterns of the substrate; A coating layer coated on the second surface of the first semiconductor chip including the input / output pad; An encapsulant for encapsulating one surface of the first semiconductor chip, the second semiconductor chip, the conductive wire, and the substrate; A semiconductor package comprising conductive balls connected to each borland of the substrate. The semiconductor package of claim 1, wherein the size of the second semiconductor chip corresponds to any one of smaller, equal, or larger than the size of the first semiconductor chip. The semiconductor package of claim 2, wherein an adhesive layer is interposed on a surface of the coating layer coated on the second surface of the first semiconductor chip, to which the first surface of the second semiconductor chip is adhered. The semiconductor package according to claim 1 or 2, wherein the conductive wire is a coated wire coated with a resin on a surface thereof. The semiconductor package of claim 1, wherein the substrate is one of a printed circuit board, a circuit tape, and a circuit film. The semiconductor package according to claim 1 or 4, wherein the adhesive layer is any one of an epoxy resin, a film adhesive layer, and a double-sided adhesive layer. The semiconductor package according to claim 1, wherein the adhesive layer is formed in a substantially rectangular lattice shape between the second surface of the first semiconductor chip and the first surface of the second semiconductor chip. The semiconductor package of claim 2, wherein the coating layer is formed by coating the first semiconductor chip and the entire conductive wire connected to the input / output pads of the first semiconductor chip. The semiconductor package according to claim 2 or 9, wherein the coating layer is a liquid encapsulant.