KR20020015875A - Method of fabricating a semiconductor device - Google Patents
Method of fabricating a semiconductor device Download PDFInfo
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- KR20020015875A KR20020015875A KR1020000049006A KR20000049006A KR20020015875A KR 20020015875 A KR20020015875 A KR 20020015875A KR 1020000049006 A KR1020000049006 A KR 1020000049006A KR 20000049006 A KR20000049006 A KR 20000049006A KR 20020015875 A KR20020015875 A KR 20020015875A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 title abstract description 17
- 238000000034 method Methods 0.000 claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 238000001039 wet etching Methods 0.000 claims abstract description 6
- 230000003247 decreasing effect Effects 0.000 claims abstract description 3
- 229920002120 photoresistant polymer Polymers 0.000 claims description 5
- 238000000206 photolithography Methods 0.000 claims 1
- 230000009977 dual effect Effects 0.000 abstract description 13
- 230000003647 oxidation Effects 0.000 description 8
- 238000007254 oxidation reaction Methods 0.000 description 8
- 238000004380 ashing Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000012876 topography Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010405 reoxidation reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0144—Manufacturing their gate insulating layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28211—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer
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- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
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- Chemical Kinetics & Catalysis (AREA)
- Chemical & Material Sciences (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
본 발명은 반도체장치의 제조방법에 관한 것으로서 특히, 제 1 영역과 제 2 영역이 정의된 반도체기판상에 하나의 절연막을 형성한 후 제 1 영역을 마스크층으로 덮은 다음 노출된 제 2 영역의 절연막 두께를 감소시킨 후 마스크층을 제거하고 잔류한 절연막의 두께를 동시에 조절하여 제 1 영역과 제 2 영역에 서로 다른 두께의 제 1 게이트절연막과 제 2 게이트절연막을 형성하므로서 제조공정을 단순화하여 문턱전압 등의 소자특성을 개선하고 생산원가를 감소시키도록한 반도체장치의 듀알 게이트절연막 형성방법에 관한 것이다. 본 발명에 따른 반도체장치의 제조방법은 제 1 영역과 제 2 영역이 정의된 반도체 기판상에 동일한 절연막으로 제 1 절연막과 제 2 절연막을 각각 형성하는 제 1 단계와, 상기 제 1 절연막을 포함하는 상기 제 1 영역을 마스크층으로 덮는 제 2 단계와, 상기 제 2 절연막의 두께를 일부 감소시키는 제 3 단계와, 상기 마스크층을 제거하는 제 4 단계와, 상기 제 2 절연막과 상기 제 1 절연막의 두께를 동일한 조건에서 증감시키는 제 5 단계를 포함하여 이루어진 공정을 구비한다. 바람직하게, 상기 제 5 단계는 습식식각을 노출된 상기 제 1, 제 2 절연막에 동시에 실시하는 것으로 이루어진다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, after forming one insulating film on a semiconductor substrate on which a first region and a second region are defined, the first region is covered with a mask layer, and then the insulating layer of the exposed second region is formed. After reducing the thickness, the mask layer was removed and the remaining insulating film was simultaneously adjusted to form first and second gate insulating films having different thicknesses in the first region and the second region, thereby simplifying the manufacturing process, thereby providing a threshold voltage. The present invention relates to a method for forming a dual gate insulating film of a semiconductor device for improving device characteristics and reducing production costs. A method of manufacturing a semiconductor device according to the present invention includes a first step of forming a first insulating film and a second insulating film with the same insulating film on a semiconductor substrate having a first region and a second region defined therein, and including the first insulating film. A second step of covering the first region with a mask layer, a third step of partially reducing the thickness of the second insulating film, a fourth step of removing the mask layer, a second step of the second insulating film and the first insulating film And a fifth step of increasing or decreasing the thickness under the same conditions. Preferably, the fifth step consists of simultaneously performing wet etching on the exposed first and second insulating films.
Description
본 발명은 반도체장치의 제조방법에 관한 것으로서 특히, 제 1 영역과 제 2 영역이 정의된 반도체기판상에 하나의 절연막을 형성한 후 제 1 영역을 마스크층으로 덮은 다음 노출된 제 2 영역의 절연막 두께를 감소시킨 후 마스크층을 제거하고 잔류한 절연막의 두께를 동시에 조절하여 제 1 영역과 제 2 영역에 서로 다른 두께의 제 1 게이트절연막과 제 2 게이트절연막을 형성하므로서 제조공정을 단순화하여 문턱전압 등의 소자특성을 개선하고 생산원가를 감소시키도록한 반도체장치의 듀알 게이트절연막 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, after forming one insulating film on a semiconductor substrate on which a first region and a second region are defined, the first region is covered with a mask layer, and then the insulating layer of the exposed second region is formed. After reducing the thickness, the mask layer was removed and the remaining insulating film was simultaneously adjusted to form first and second gate insulating films having different thicknesses in the first region and the second region, thereby simplifying the manufacturing process, thereby providing a threshold voltage. The present invention relates to a method for forming a dual gate insulating film of a semiconductor device for improving device characteristics and reducing production costs.
최근에 화상, 음성 및 문자 등을 동시에 표현하는 멀티미디어(multimedia) 등과 같은 시스템(system)은 다양하고 복잡하며 향상된 기능을 가지면서 소형화 및 경량화가 요구되고 있다. 이와 같이 요구를 충족시키기 위해서는 시스템을 구성하는 서로 다른 기능을 갖는 반도체회로들을 통합하여 동일한 칩에 형성하는 1칩(one chip)화 하는 기술이 개발되고 있다.Recently, systems such as multimedia, which simultaneously display images, voices, and texts, are required to be miniaturized and lightweight while having various, complex, and improved functions. In order to meet the demand as described above, a technology of forming a single chip in which semiconductor circuits having different functions constituting a system are integrated and formed on the same chip has been developed.
1칩화된 반도체회로는 서로 다른 기능을 가지며 서로 다른 전원에서 동작하는 다수의 회로가 동일한 반도체기판에 본래의 기능과 성능이 유지되도록 형성되어야 한다. 즉, 동일한 반도체기판 상에 서로 다른 구동 전압을 갖는 트랜지스터의 구성이 필요하며, 이를 구현하기 위해서는 소자들의 문턱전압(threshold voltage)을 서로 다르도록 조절하여야 한다.Single-chip semiconductor circuits have different functions, and a plurality of circuits operating in different power sources must be formed such that the original functions and performances are maintained on the same semiconductor substrate. That is, a configuration of transistors having different driving voltages is required on the same semiconductor substrate, and in order to implement this, the threshold voltages of the devices must be adjusted to be different from each other.
반도체소자의 입력/출력단자 부위와 실질적으로 로직(logic)이 동작하는 코아(core) 부위의 동작전압이 각기 다르게 요구되는 경우의 제품에 대하여 듀알 게이트산화막 형성공정으로 그 요구를 충족시키는데 본 발명에서는 상술한 공정을 단일공정으로 단순화하하는데 그 목적이 있다.In the present invention, a dual gate oxide film forming process satisfies the requirements for a product in which an input voltage of a semiconductor device and an operation voltage of a core portion where logic is substantially operated are required differently. The purpose is to simplify the above process into a single process.
종래 기술에서는 하나의 칩에서 서로 다른 동작전압을 요구하는 소자제작에 있어서 게이트산화막의 두께를 다르게하기 위하여 듀알 게이트산화막 프로세스(dual gate oxide process)를 채용한다. 즉, 종래 기술에서는 바도체기판에 대한 초기 산화공정 후 일측의 산화막을 제거하고 동시에 타측의 잔류한 산화막의 두께를 낮춘후, 다시 재산화공정으로 산화막을 양측에 모두 성장시켜 두께가 서로 다른 산화막을 하나의 칩에 형성한다.In the prior art, a dual gate oxide process is employed to change the thickness of the gate oxide film in fabricating a device requiring different operating voltages on one chip. That is, in the prior art, the oxide film on one side is removed after the initial oxidation process on the conductor substrate, the thickness of the remaining oxide film on the other side is lowered, and the oxide film is grown on both sides by the reoxidation process to form oxide films having different thicknesses. Form on one chip.
도 1a 내지 도 1e는 종래 기술에 따른 반도체장치의 듀알 게이트산화막 형성 공정단면도이다.1A to 1E are cross-sectional views of a process of forming a dual gate oxide film of a semiconductor device according to the related art.
도 1a에 있어서, 두꺼운 절연막이 형성되는 제 1 영역(TK1)과 상대적으로 얇은 절연막이 형성되는 제 2 영역(TN1)이 정의된 반도체 기판인 실리콘 기판(10) 상부 표면에, 서로 다른 구동전압을 갖는 모스전계효과트렌지스터(MOSFET) 제조공정으로서, 소자 격리용 트렌치 형성한 다음 채널스톱 및 문턱전압을 조절하기 위하여 이온주입을 실시한다.In FIG. 1A, different driving voltages are applied to an upper surface of a silicon substrate 10 that is a semiconductor substrate in which a first region TK1 in which a thick insulating film is formed and a second region TN1 in which a relatively thin insulating film is formed are defined. In the manufacturing process of a MOSFET having a MOSFET, a trench for isolation of an element is formed, followed by ion implantation to adjust the channel stop and threshold voltage.
그리고 트렌치 부위에 소자격리용 필드산화막을 증착한 다음 평탄화공정 등을 수행하여 기판(10)의 전표면에 토포그래피를 균일하게 만든 후, 게이트절연막을 형성하기 위하여 제 1 절연막(120, 121)을 노출된 기판(10) 표면을 열산화시켜 제 1 영역(TK1)과 제 2 영역(TN1)에 각각 두껍게 형성한다.After depositing a field oxide film for isolation of a device in the trench, and then performing a planarization process, the topography is uniformly formed on the entire surface of the substrate 10, and then the first insulating films 120 and 121 are formed to form a gate insulating film. The surface of the exposed substrate 10 is thermally oxidized to be thickly formed in the first region TK1 and the second region TN1, respectively.
도 1b를 참조하면, 제 1 절연막(120)을 포함하는 제 1 영역(TK1)을 덮는 마스크층(13)을 기판상에 형성한다. 이때, 마스크층(13)은 기판(13)상에 포토레지스트를 도포한 후, 노광 및 현상을 실시하여 제 2 절연막(121) 표면을 포함하는 제 2 영역(TN1)의 기판을 노출시키고 제 1 영역(TK1)은 덮는 포토레지스트패턴(13)을 형성하여 제작한다.Referring to FIG. 1B, a mask layer 13 covering the first region TK1 including the first insulating layer 120 is formed on the substrate. At this time, the mask layer 13 is coated with a photoresist on the substrate 13, and then subjected to exposure and development to expose the substrate of the second region TN1 including the surface of the second insulating film 121 and the first layer. The region TK1 is formed by forming a covering photoresist pattern 13.
도 1c를 참조하면, 노출된 제 2 영역(TN1)의 제 2 절연막(122)을 스핀 에치(spin etch)등의 방법으로 소정 두께만큼 제거하여 잔류시킨다. 따라서, 에치된 제 2 절연막(122)의 두께는 마스크층(13)으로 보호된 제 1 절연막(120)의 두께보다 얇아지게 된다.Referring to FIG. 1C, the second insulating layer 122 of the exposed second region TN1 is removed by a predetermined thickness, such as by spin etch, and left. Accordingly, the thickness of the etched second insulating layer 122 is thinner than the thickness of the first insulating layer 120 protected by the mask layer 13.
도 1d를 참조하면, 마스크층을 산소 애슁(O2ashing) 등의 방법으로 제거하여 제 1 절연막의 표면을 노출시킨다.Referring to FIG. 1D, the mask layer is removed by a method such as oxygen ashing (O 2 ashing) to expose the surface of the first insulating film.
그리고, 제 2 영역(TN1)의 기판 표면을 노출시키기 위하여 상대적으로 두꺼운 제 2 절연막과 얇은 제 1 절연막에 식각을 실시한다. 이때, 식각종료점은 제 2 절연막이 완전히 제거되어 제 2 영역의 기판 표면이 완전히 노출되는 시점으로 하며, 습식식각을 사용한다.In order to expose the substrate surface of the second region TN1, etching is performed on the relatively thick second insulating film and the thin first insulating film. In this case, the etching end point is a time point at which the second insulating layer is completely removed to completely expose the substrate surface of the second region, and wet etching is used.
따라서, 제 1 영역(TK1)에는 상대적으로 두꺼운 제 1 절연막(123)이 소정 두께만큼 얇아진 상태로 잔류하게 된다.Accordingly, the relatively thick first insulating layer 123 remains in the first region TK1 in a state of being thinned by a predetermined thickness.
도 1e를 참조하면, 최종 산화공정을 기판(10)에 실시하여 제 1 절연막(124)의 두께를 성장시키는 동시에, 제 2 영역(TN1)에 새로운 제 3 절연막(14)을 성장시켜 형성한다. 이때, 제 3 절연막(14)의 성장 두께를 조절하여 서로 다른 동작전압이 요구되는 소자제작을 가능하게 한다.Referring to FIG. 1E, a final oxidation process is performed on the substrate 10 to grow the thickness of the first insulating film 124 and to grow a new third insulating film 14 in the second region TN1. At this time, by controlling the growth thickness of the third insulating film 14, it is possible to manufacture a device that requires a different operating voltage.
따라서, 제 1 영역(TK1)에는 두꺼운 제 1 절연막(124)이 형성되고 제 2 영역(TN1)에는 상대적으로 얇은 제 3 절연막(14)이 형성된다.Therefore, a thick first insulating layer 124 is formed in the first region TK1, and a relatively thin third insulating layer 14 is formed in the second region TN1.
상술한 바와 같이 종래의 기술에서는 듀알 게이트산화막 구조를 실현하기 위하여 게이트절연막 형성용 산화공정을 2회 실시하여야 하므로 공정단계가 증가하여 공정이 복잡하고, 또한, 2회에 걸친 고온의 열산화공정으로 트랜지스터 소자의 문턱전압이 변화할 수 있는 문제점이 있다.As described above, in order to realize the dual gate oxide film structure in the related art, since the oxidation process for forming the gate insulating film must be performed twice, the process step is increased and the process is complicated, and the high temperature thermal oxidation process is performed twice. There is a problem that the threshold voltage of the transistor element can be changed.
본 발명의 목적은 동일한 칩 내에 구동 전압이 서로 다른 소자를 형성하는데 있어서, 제 1 영역과 제 2 영역이 정의된 반도체기판상에 하나의 절연막을 형성한 후 제 1 영역을 마스크층으로 덮은 다음 노출된 제 2 영역의 절연막 두께를 감소시킨후 마스크층을 제거하고 잔류한 절연막의 두께를 동시에 조절하여 제 1 영역과 제 2 영역에 서로 다른 두께의 제 1 게이트절연막과 제 2 게이트절연막을 형성하므로서 제조공정을 단순화하여 문턱전압 등의 소자특성을 개선하고 생산원가를 감소시키도록 한 반도체장치의 듀알 게이트절연막 형성방법을 제공함에 있다.SUMMARY OF THE INVENTION An object of the present invention is to form a device having different driving voltages in the same chip, and to form a single insulating film on a semiconductor substrate on which a first region and a second region are defined, and then cover the first region with a mask layer and then expose it. By reducing the thickness of the insulating film in the second region, and removing the mask layer and simultaneously adjusting the thickness of the remaining insulating film to form first and second gate insulating films having different thicknesses in the first and second regions. The present invention provides a method for forming a dual gate insulating film of a semiconductor device which simplifies the process to improve device characteristics such as threshold voltages and reduce production costs.
상기 목적들을 달성하기 위한 본 발명에 따른 반도체장치의 제조방법은 제 1 영역과 제 2 영역이 정의된 반도체 기판상에 동일한 절연막으로 제 1 절연막과 제 2 절연막을 각각 형성하는 제 1 단계와, 상기 제 1 절연막을 포함하는 상기 제 1 영역을 마스크층으로 덮는 제 2 단계와, 상기 제 2 절연막의 두께를 일부 감소시키는 제 3 단계와, 상기 마스크층을 제거하는 제 4 단계와, 상기 제 2 절연막과 상기 제 1 절연막의 두께를 동일한 조건에서 증감시키는 제 5 단계를 포함하여 이루어진 공정을 구비한다. 바람직하게, 상기 제 5 단계는 습식식각을 노출된 상기 제 1, 제 2 절연막에 동시에 실시하는 것으로 이루어진다.A method of manufacturing a semiconductor device according to the present invention for achieving the above objects comprises a first step of forming a first insulating film and a second insulating film with the same insulating film on a semiconductor substrate in which a first region and a second region are defined; A second step of covering the first region including the first insulating film with a mask layer, a third step of partially reducing the thickness of the second insulating film, a fourth step of removing the mask layer, and the second insulating film And a fifth step of increasing and decreasing the thickness of the first insulating film under the same conditions. Preferably, the fifth step consists of simultaneously performing wet etching on the exposed first and second insulating films.
도 1a 내지 도 1e는 종래 기술에 따른 반도체장치의 듀알 게이트산화막 형성 공정단면도1A to 1E are cross-sectional views of a process of forming a dual gate oxide film of a semiconductor device according to the related art.
도 2a 내지 도 2d는 본 발명에 따른 반도체장치의 듀알 게이트산화막 형성공정 단면도2A to 2D are cross-sectional views of a dual gate oxide film forming process of a semiconductor device according to the present invention.
본 발명은 듀알 게이트산화막을 1회의 산화막 형성공정으로 구현한다. 즉 셀부와 페리부 등의 서로 다른 영역에 두께가 서로 상이한 게이트산화막을 갖는 트렌지스터를 제조할 수 있다.The present invention implements the dual gate oxide film in one oxide film formation process. That is, it is possible to manufacture a transistor having a gate oxide film having different thicknesses in different regions such as a cell portion and a ferry portion.
듀알 게이트산화막이 요구되는 경우를 예로 들면, 직(logic)의 경우 입출력부위와 메인 코아(main core) 부위의 동작전압을 다르게 하여 설계되고 시스템 경우에서도 그와 같이 요구하는 경향이 커지고 있다. 이는 데이타의 입출력시 외부전압을 그대로 수용하여 로직을 동작시키고 메인 코아에서는 낮은 전압으로 동작시키려는 의도때문이다. 따라서 이에 따른 게이트산화막의 항복전압(breakdown voltage)과 문턱전압(threshold voltage)의 문제가 제기되는데 이를 위하여 듀알 게이트산화막 형성공정을 사용한다.For example, a dual gate oxide film is required. In the case of logic, the operating voltages of the input / output part and the main core part are designed differently, and in the case of a system, the demand tends to increase. This is due to the intention to operate the logic by accepting the external voltage as it is in the input / output of data and to operate the low voltage in the main core. Accordingly, problems of breakdown voltage and threshold voltage of the gate oxide film are raised. For this, a dual gate oxide film forming process is used.
본 발명에서는 게이트절연막 형성을 위한 산화공정을 1회로 제한하여 제조공정을 단순화하는데, 1회 산화공정에 의하여 서로 다른 영역에 산화막을 형성한 후, 선태적인 식각으로 산화막의 두께를 차별화한다.The present invention simplifies the manufacturing process by limiting the oxidation process for forming the gate insulating film to one time. After the oxide films are formed in different regions by a single oxidation process, the thicknesses of the oxide films are differentiated by selective etching.
이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2d는 본 발명에 따른 반도체장치의 듀알 게이트산화막 형성공정 단면도이다.2A to 2D are cross-sectional views of a process of forming a dual gate oxide film of a semiconductor device according to the present invention.
도 2a에 있어서, 두꺼운 절연막이 형성되는 제 1 영역(TK2)과 상대적으로 얇은 절연막이 형성되는 제 2 영역(TN2)이 정의된 반도체 기판인 실리콘 기판(20) 상부 표면에, 서로 다른 구동전압을 갖는 모스전계효과트렌지스터(MOSFET) 제조공정으로서, 소자 격리용 트렌치 형성한 다음 채널스톱 및 문턱전압을 조절하기 위하여 이온주입을 실시한다.In FIG. 2A, different driving voltages are applied to an upper surface of a silicon substrate 20, which is a semiconductor substrate in which a first region TK2 in which a thick insulating film is formed and a second region TN2 in which a relatively thin insulating film is formed are defined. In the manufacturing process of a MOSFET having a MOSFET, a trench for isolation of an element is formed, followed by ion implantation to adjust the channel stop and threshold voltage.
그리고 트렌치 부위에 소자격리용 필드산화막을 증착한 다음 평탄화공정 등을 수행하여 기판(20)의 전표면의 토포그래피를 균일하게 만든 후, 절연막을 형성하기 위하여 제 1 절연막(220, 221)을 노출된 기판(10) 표면을 열산화시켜 제 1 영역(TK1)과 제 2 영역(TN1)에 산화막을 소정의 두께로 각각 형성한다. 따라서, 제 1 절연막(220)과 제 2 절연막(221)의 두께는 동일하다.After depositing a field oxide film for isolation of a device in the trench, the planarization process is performed to uniformly topography the entire surface of the substrate 20, and then expose the first insulating films 220 and 221 to form an insulating film. The surface of the substrate 10 is thermally oxidized to form oxide films in predetermined thicknesses in the first region TK1 and the second region TN1, respectively. Therefore, the thicknesses of the first insulating film 220 and the second insulating film 221 are the same.
도 2b를 참조하면, 제 1 절연막(220)을 포함하는 제 1 영역(TK2)을 덮는마스크층(23)을 기판상에 형성한다. 이때, 마스크층(23)은 기판(23)상에 포토레지스트를 도포한 후, 노광 및 현상을 실시하여 제 2 절연막(221) 표면을 포함하는 제 2 영역(TN2)의 기판을 노출시키고 제 1 영역(TK2)은 덮는 포토레지스트패턴(23)을 형성하여 제작한다.Referring to FIG. 2B, a mask layer 23 covering the first region TK2 including the first insulating layer 220 is formed on the substrate. In this case, the mask layer 23 is coated with a photoresist on the substrate 23, and then subjected to exposure and development to expose the substrate of the second region TN2 including the surface of the second insulating film 221, and then expose the first layer. The region TK2 is formed by forming a covering photoresist pattern 23.
도 2c를 참조하면, 노출된 제 2 영역(TN2)의 제 2 절연막(222)을 스핀 에치(spin etch)등의 방법으로 소정 두께만큼 제거하여 잔류시킨다. 따라서, 에치된 제 2 절연막(222)의 두께는 마스크층(23)으로 보호된 제 1 절연막(220)의 두께보다 얇아지게 된다.Referring to FIG. 2C, the second insulating layer 222 of the exposed second region TN2 is removed by a predetermined thickness, such as by spin etch, and left. Accordingly, the thickness of the etched second insulating layer 222 becomes thinner than the thickness of the first insulating layer 220 protected by the mask layer 23.
도 2d를 참조하면, 마스크층을 산소 애슁(O2ashing) 등의 방법으로 제거하여 제 1 절연막의 표면을 노출시킨다.Referring to Figure 2d, by removing the mask layer, for example by oxygen ashing (O 2 ashing) to expose the surface of the first insulating film.
따라서, 제 1 영역(TK2)과 제 2 영역(TN2)의 제 1 절연막과 제 2 절연막 표면이 동시에 노출된다.Therefore, the surfaces of the first insulating film and the second insulating film of the first region TK2 and the second region TN2 are simultaneously exposed.
그리고, 상대적으로 두꺼운 제 2 절연막과 얇은 제 1 절연막에 습식식각을 실시하여 양 절연막의 두께를 감소시킨다. 이때, 제 1 절연막(224)과 제 2 절연막(223)은 열산화방법으로 형성된 동일한 산화막으로 이루어졌고, 동일한 습식식각조건에서 식각되므로 제거되는 두께가 동일하게 된다.Then, wet etching is performed on the relatively thick second insulating film and the thin first insulating film to reduce the thickness of both insulating films. In this case, the first insulating film 224 and the second insulating film 223 are made of the same oxide film formed by the thermal oxidation method, and are etched under the same wet etching conditions, so that the removed thickness is the same.
따라서, 제 1 영역(TK2)에는 상대적으로 두꺼운 제 1 절연막(224)이 소정 두께만큼 얇아진 상태로 잔류하게 되고, 제 2 영역(TN2)에는 동일한 두께만큼 감소하여 제 1 절연막(224)보다 얇은 제 1 절연막(223)이 최종적으로 잔류하게 된다.Accordingly, a relatively thick first insulating film 224 remains in the thinned state by a predetermined thickness in the first region TK2, and is reduced by the same thickness in the second region TN2 so as to be thinner than the first insulating film 224. 1 The insulating film 223 finally remains.
이후, 도시되지는 않았지만, 최종 제 1 절연막(224)과 제 2 절연막(223)을 게이트산화막으로 이용하여 서로 다른 동작전압을 요구하는 모스 트랜지스터 소자작을 진행한다.Subsequently, although not shown, the MOS transistor device operation requiring different operating voltages is performed using the final first insulating film 224 and the second insulating film 223 as gate oxide films.
따라서, 본 발명은 서로 다른 두께의 제 1 게이트절연막과 제 2 게이트절연막을 1 회의 산화공정으로 형성하므로서 제조공정을 단순화하여 문턱전압 등의 소자특성을 개선하고 생산원가를 감소시키는 장점이 있다.Therefore, the present invention has the advantage of improving the device characteristics such as threshold voltage and reducing the production cost by simplifying the manufacturing process by forming the first gate insulating film and the second gate insulating film of different thicknesses in one oxidation process.
Claims (5)
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| KR19980052318A (en) * | 1996-12-24 | 1998-09-25 | 문정환 | Method of manufacturing a semiconductor device having a dual gate insulating film |
| JPH11330262A (en) * | 1998-05-15 | 1999-11-30 | Mitsubishi Electric Corp | Method for manufacturing semiconductor device |
| JP2000003965A (en) * | 1998-06-15 | 2000-01-07 | Mitsubishi Electric Corp | Semiconductor device and method of manufacturing the same |
| KR20000026819A (en) * | 1998-10-23 | 2000-05-15 | 김영환 | Method of manufacturing dual gate oxide layer |
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| KR19980052318A (en) * | 1996-12-24 | 1998-09-25 | 문정환 | Method of manufacturing a semiconductor device having a dual gate insulating film |
| JPH11330262A (en) * | 1998-05-15 | 1999-11-30 | Mitsubishi Electric Corp | Method for manufacturing semiconductor device |
| JP2000003965A (en) * | 1998-06-15 | 2000-01-07 | Mitsubishi Electric Corp | Semiconductor device and method of manufacturing the same |
| KR20000026819A (en) * | 1998-10-23 | 2000-05-15 | 김영환 | Method of manufacturing dual gate oxide layer |
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| KR100908784B1 (en) * | 2002-08-28 | 2009-07-22 | 후지쯔 마이크로일렉트로닉스 가부시키가이샤 | Manufacturing Method of Semiconductor Device |
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