KR20020010808A - Method for forming gate electrode in semiconductor device - Google Patents
Method for forming gate electrode in semiconductor device Download PDFInfo
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- KR20020010808A KR20020010808A KR1020000044292A KR20000044292A KR20020010808A KR 20020010808 A KR20020010808 A KR 20020010808A KR 1020000044292 A KR1020000044292 A KR 1020000044292A KR 20000044292 A KR20000044292 A KR 20000044292A KR 20020010808 A KR20020010808 A KR 20020010808A
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- forming
- gate electrode
- tungsten nitride
- film
- tungsten
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- 238000000034 method Methods 0.000 title claims abstract description 22
- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 36
- 239000010937 tungsten Substances 0.000 claims abstract description 36
- -1 tungsten nitride Chemical class 0.000 claims abstract description 27
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 14
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 6
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims description 14
- 229910001936 tantalum oxide Inorganic materials 0.000 claims description 14
- 239000007789 gas Substances 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 2
- 239000012299 nitrogen atmosphere Substances 0.000 claims 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 abstract description 5
- 238000000137 annealing Methods 0.000 abstract 2
- 239000010408 film Substances 0.000 description 38
- 238000010438 heat treatment Methods 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910044991 metal oxide Inorganic materials 0.000 description 4
- 150000004706 metal oxides Chemical class 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000009257 reactivity Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
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- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
본 발명은 반도체소자의 제조 방법에 관한 것으로, 텅스텐질화막(WN)을 이용한 게이트전극의 형성 방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device, and to a method of forming a gate electrode using a tungsten nitride film (WN).
최근에, 디자인룰(Design rule)이 작아지면서 서브-0.1㎛급 소자에서는 게이트산화막(Gateoxide)으로서 사용되고 있는 SiO2산화막보다 탄탈륨산화막(Ta2O5) 등의 고유전율을 갖는 고유전율 메탈산화막(High permitivity metal oxide)을 사용해야 한다. 그리고, 상기 메탈산화막은 일반적으로 화학적기상증착법(Chemical Vapor Deposition; CVD)을 이용하여 증착한다.Recently, as the design rule becomes smaller, a high-k metal oxide film having a higher dielectric constant such as a tantalum oxide film (Ta 2 O 5 ) than a SiO 2 oxide film used as a gate oxide in a sub-0.1 μm class device ( High permitivity metal oxides should be used. In addition, the metal oxide layer is generally deposited using chemical vapor deposition (CVD).
그러나, 상기 탄탈륨산화막은 고온 열처리시 열안정성이 떨어지기 때문에 소스/드레인(Source/Drain) 열처리시 탄탈륨산화막의 열안정성이 떨어져 유전막으로서 기능을 잃게 된다.However, since the tantalum oxide film has poor thermal stability during high temperature heat treatment, the tantalum oxide film loses its function as a dielectric film due to poor thermal stability of the tantalum oxide film during source / drain heat treatment.
상기의 문제점을 해결하기 위해 다마신(Damascene) 구조가 제안되었는데, 상기 다마신 구조로 반도체소자를 제조할 경우, 소스/드레인 열처리를 받지 않고 탄탈륨산화막을 증착할 수 있다.In order to solve the above problem, a damascene structure has been proposed. When fabricating a semiconductor device using the damascene structure, a tantalum oxide film may be deposited without source / drain heat treatment.
상기 탄탈륨산화막상에 게이트전극을 형성해야하는데, 상기 금속게이트전극으로는 주로 CVD WSi, PVD W, WN, TiN, 또는 폴리실리콘(PolySilicon) 등이 사용되고 있다. 상기 게이트전극으로 이용되는 박막은 게이트전극의 면저항을 낮추면서 탄탈륨산화막(Ta2O5)과 접촉했을 때 게이트전극과 탄탈륨산화막 사이에 반응성이 없는 물질이어야 한다.A gate electrode should be formed on the tantalum oxide film. The metal gate electrode is mainly CVD WSi, PVD W, WN, TiN, polysilicon, or the like. The thin film used as the gate electrode should be a material having no reactivity between the gate electrode and the tantalum oxide film when contacted with the tantalum oxide film Ta 2 O 5 while lowering the sheet resistance of the gate electrode.
상기 조건을 만족하는 물질로는 텅스텐(W), 텅스텐질화막(WN)이 있는데, 이 중 텅스텐은 텅스텐질화막보다 탄탈륨산화막의 산소와 결합하기 쉬우므로 텅스텐질화막이 게이트전극으로 주로 이용되고 있다.Materials satisfying the above conditions include tungsten (W) and tungsten nitride film (WN). Among them, tungsten nitride film is mainly used as a gate electrode because tungsten is more easily bonded with oxygen of tantalum oxide film than tungsten nitride film.
도 1에 도시된 종래기술에서는 반도체기판(11)상에 탄탈륨산화막(12)을 형성한 다음, 물리적기상증착방법(Physical Vapor Deposition; PVD)으로 텅스텐질화막 (13)을 증착하였는데, 다마신 금속게이트(Damascene metal gate)에 적용하기 위해서는 단차피복성(Step coverage)이 우수한 금속막이 필요하기 때문에 상기 물리적기상증착법에 의한 텅스텐질화막은 단차피복성이 떨어지는 단점을 가지고 있다.In the prior art illustrated in FIG. 1, a tantalum oxide film 12 is formed on a semiconductor substrate 11, and then a tungsten nitride film 13 is deposited by physical vapor deposition (PVD). In order to be applied to a damascene metal gate, a tungsten nitride film by the physical vapor deposition method has a disadvantage in that the step coverage is poor because a metal film having excellent step coverage is required.
본 발명은 상기 종래기술의 문제점을 해결하기 위해 안출한 것으로서, 단차피복성이 우수한 텅스텐질화막을 형성하고 후속 열처리를 통해 저항을 낮추는데 적합한 게이트전극의 형성 방법을 제공함에 그 목적이 있다.The present invention has been made to solve the problems of the prior art, and an object of the present invention is to provide a method for forming a gate electrode suitable for forming a tungsten nitride film having excellent step coverage and lowering resistance through subsequent heat treatment.
도 1은 종래기술에 따른 게이트전극의 형성 방법을 도시한 도면,1 is a view showing a method of forming a gate electrode according to the prior art;
도 2a 내지 도 2b는 본 발명의 실시예에 따른 게이트전극의 형성 방법을 도시한 도면.2A and 2B illustrate a method of forming a gate electrode according to an exemplary embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
21 : 반도체 기판 22 : 탄탈륨산화막21 semiconductor substrate 22 tantalum oxide film
23 : 텅스텐질화막23: tungsten nitride film
상기의 목적을 달성하기 위한 본 발명의 게이트전극의 형성 방법은 반도체기판상에 고유전율을 갖는 게이트산화막을 형성하는 제 1 단계; 상기 게이트산화막상에 게이트전극으로서 화학적기상증착법을 이용하여 텅스텐질화막을 형성하는 제 2 단계; 및 상기 텅스텐질화막을 열처리하는 제 3 단계를 포함하여 이루어짐을 특징으로 한다.A method of forming a gate electrode of the present invention for achieving the above object comprises a first step of forming a gate oxide film having a high dielectric constant on a semiconductor substrate; Forming a tungsten nitride film on the gate oxide film using a chemical vapor deposition method as a gate electrode; And a third step of heat-treating the tungsten nitride film.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
도 2a 내지 도 2b는 본 발명의 실시예에 따른 게이트전극의 형성 방법을 도시한 도면이다.2A to 2B illustrate a method of forming a gate electrode according to an exemplary embodiment of the present invention.
도 2a에 도시된 바와 같이, 반도체기판(21)상에 탄탈륨산화막(22)을 형성한 다음, 상기 탄탈륨산화막(23)상에 화학적기상증착법(CVD)을 이용하여 텅스텐질화막 (23)을 형성한다.As shown in FIG. 2A, a tantalum oxide film 22 is formed on the semiconductor substrate 21, and then a tungsten nitride film 23 is formed on the tantalum oxide film 23 by chemical vapor deposition (CVD). .
이 때, 상기 텅스텐질화막(23)은 WF6와 NF의 혼합가스를 이용하여 플라즈마화학기상증착법(Plasma Enhanced Chemical Vapor Deposition; PECVD)으로 형성한다.At this time, the tungsten nitride film 23 is formed by plasma enhanced chemical vapor deposition (PECVD) using a mixed gas of WF 6 and NF.
또한, WF6와 NH3의 혼합가스를 이용하여 화학적기상증착법으로 형성할 수 있으며, 또는 WF6을 이용하여 화학적기상증착법으로 텅스텐막을 먼저 형성한 다음, 상기 텅스텐막상에 NH3가스를 흘리거나 또는 NF 플라즈마를 사용하여 텅스텐질화막을 형성한다.In addition, it may be formed by chemical vapor deposition using a mixed gas of WF 6 and NH 3 , or by first forming a tungsten film by chemical vapor deposition using WF 6 , and then flowing NH 3 gas on the tungsten film or Tungsten nitride film is formed using NF plasma.
도 2b에 도시된 바와 같이, 후속 게이트전극의 저항을 감소시키기 위해 상기 텅스텐질화막(23)에 질소(N2) 분위기에서 800℃∼1000℃의 온도에서 열처리한다. 상기와 같이 후열처리 공정을 실시하면 텅스텐질화막(23)이 텅스텐으로 변화되면서 저항이 낮은 게이트전극을 형성한다.As shown in FIG. 2B, the tungsten nitride film 23 is heat-treated at a temperature of 800 ° C. to 1000 ° C. in a nitrogen (N 2 ) atmosphere to reduce the resistance of subsequent gate electrodes. When the post-heat treatment process is performed as described above, the tungsten nitride film 23 is changed to tungsten to form a gate electrode having low resistance.
도면에 도시되지 않았지만, 상술한 실시예의 텅스텐질화막은 메탈산화막 캐패시터(Metal oxide capacitor)용 상부전극, 하부전극으로 적용할 수 있다.Although not shown in the drawings, the tungsten nitride film of the above-described embodiment may be applied as an upper electrode and a lower electrode for a metal oxide capacitor.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 바와 같은 본 발명의 게이트전극 형성 방법은 화학적기상증착법을 이용하여 텅스텐질화막을 형성하므로써, 다마신 금속게이트의 단차피복성을 향상시킬 수 있고, 후 열처리 공정을 실시하므로 게이트전극의 저항을 감소시킬 수 있는 효과가 있다.The gate electrode forming method of the present invention as described above can improve the step coverage of the damascene metal gate by forming a tungsten nitride film using chemical vapor deposition, and reduce the resistance of the gate electrode by performing a post-heat treatment process. It can be effected.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000044292A KR20020010808A (en) | 2000-07-31 | 2000-07-31 | Method for forming gate electrode in semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000044292A KR20020010808A (en) | 2000-07-31 | 2000-07-31 | Method for forming gate electrode in semiconductor device |
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| Publication Number | Publication Date |
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| KR20020010808A true KR20020010808A (en) | 2002-02-06 |
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| KR1020000044292A Withdrawn KR20020010808A (en) | 2000-07-31 | 2000-07-31 | Method for forming gate electrode in semiconductor device |
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- 2000-07-31 KR KR1020000044292A patent/KR20020010808A/en not_active Withdrawn
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