KR20020000460A - A test apparatus of seimconductor device - Google Patents

Abstract

PURPOSE: An apparatus for testing a semiconductor device is provided to detect a chip for anti-fuse programming after programming an anti-fuse in a wafer level test process and performing a test for package reliability. CONSTITUTION: The third multiplexer is formed by the first inverter(118) for inverting a special test signal(ST_anti_det) and the first and the second transmission gates(T7,T8) for outputting read data(anti_det_rd, anti_det_rdb) of an anti-detector portion to a mxout and a mxoutb according to the special test signal(ST_anti_det) and an output signal of the first inverter(118). A special test decoder outputs a low signal if not a special test mode. The low signal of the special test decoder is inverted to a high signal by the first inverter(118) and the first and the second transmission gates(T7,T8) are turned off. The special test decoder outputs the high signal if the special test mode. The high signal is inverted to the low signal by the second inverter and the first and the second transmission gates(T7,T8) are turned on. The read signal(anti_det_rd, anti_det_rdb) are transmitted to a register when the first and the second transmission gates(T7,T8) are turned on.

Description

A test apparatus of a semiconductor device

The present invention relates to a test device for a semiconductor device capable of detecting whether anti-fuse is programmed.

Typically, wafer-level tests detect error bits. When an error bit is detected, the error bit is repaired using laser repair and antifuse repair. After repairing the error bits, the package is packaged and burn-in stress is applied to test the reliability of the package. The error bit is detected after a reliability test of the package.

If an error bit occurs after the package phase, the error bit can only be repaired by antifuse. However, it was not possible to know which sample used the antifuse in the wafer level test among the error bit generated samples, and there was a problem in that the antifuse programming had to be performed for all the error samples.

Accordingly, an object of the present invention is to provide a test apparatus for a semiconductor device capable of detecting a chip in which an antifuse is programmed after a package reliability test after programming the antifuse in a wafer level test.

In order to achieve the above object, a test apparatus for a semiconductor device according to the present invention includes an anti-enable unit for generating an anti-enable signal when anti-fuse is programmed, and an anti-control unit for generating a control signal according to whether anti-fuse is programmed. According to the special test signal, the tester generates a special test signal according to an external signal, an anti-detector unit that stores data input to the pad from the external according to the special test signal and the anti-enable signal, and outputs read data. A readout multi-part that outputs read data of the anti-detector unit to a pad, and a control unit which not only generates data for a special test but also compares the generated data with the data output to the pad to determine whether anti-fuse is used. Characterized in that made.

1 is a control flowchart for explaining a test of a semiconductor device according to the present invention.

2 is a block diagram for explaining a test apparatus of a semiconductor device according to the present invention.

FIG. 3 is a circuit diagram illustrating the anti-detector unit of FIG. 2. FIG.

4 is a block diagram illustrating the read multiplexer of FIG. 2.

FIG. 5 is a circuit diagram illustrating the first multiplexer of FIG. 4.

FIG. 6 is a circuit diagram for describing a second multiplexer of FIG. 4. FIG.

FIG. 7 is a circuit diagram for describing a third multiplexer of FIG. 4. FIG.

Explanation of symbols on the main parts of the drawings

11: First anti-fuse 12: Anti-enable part

13: 2nd anti-fuse 20: anti-pump

31: The first predecoder 32: The first anthographic decoder

33: 2nd picture decoder 34: 2nd picture decoder

41: first comparison unit 42: second comparison unit

50: anti-control unit 60: special test decoder

70: main cell 80: sense amplifier

90: The reading middle part 100: Register

110: output driver 120: pad

130: input buffer 140: input driver

160: write driver 170: anti-cell

180: anti-detector unit 190: control unit

Hereinafter, with reference to the accompanying drawings to describe the present invention in detail.

1 is a flowchart illustrating a test of a semiconductor device according to the present invention.

The wafer level test S10 is performed to count the number of failed bits. Then, the number of counted bad bits is checked (S20). At this time, if there is no bad bit count FB, a post test S30 is performed.

If it is determined that the number of the bad bit counts FB is less than or equal to the preset number N of bits that can be repaired by the laser, the bad bits are repaired using the laser (S21). When the number of bad bit counts FB is N + 1, first, N bad bits are repaired using a laser (S22). The remaining bad bits are repaired using antifuse (S23). In this case, N is the number of bits that can be repaired by using a laser, and 1 is the number of bits that can be repaired by the antifuse, and is changed according to the number of antifuses. After the repair is performed, the repair is verified through a post test (S30). After the post test, the package (S40) and the package test (S50) are performed. Then, burn-in stress is applied to perform the reliability test (S60), and the number of bad bits is counted.

If the number of bad bits is zero, package sample S100 is performed. If the number of bad bits is greater than 1, the package is discarded because there are more bad bits than can be repaired with antifuse. However, if the number of bad bits is 1, it is determined whether antifuse has been used (S80). If antifuse is not used, antifuse repair is performed, and if antifuse is used, discard.

2 is a block diagram illustrating a programming antifuse detector in accordance with the present invention.

The programming antifuse detector includes a first antifuse 11 for programming X addresses, a second antifuse 13 for programming Y addresses, and an antifuse according to addresses <0:13> and ST <7: 8>. An anti-enable part 12 is provided to indicate whether or not it is used, and an anti-supply voltage of -4 volts for programming the first anti-fuse 11, the second anti-fuse 13 and the anti-enable part 12 is provided. A pump 20 is provided. A first predecoder 31 for predecoding the X address and a second predecoder 34 for predecoding the Y address are provided in accordance with the address <0:13>.

The first antifuse 11 is connected to a first antifreeze decoder 32 that predecodes its output, and the second antifuse 13 is a second antifreeze decoder 33 that predecodes its output. Connected. First comparison to generate an anti-X enable signal Anti_xen according to an output signal of the first predecoder 31 and the first anti-free decoder 32 and an output of the anti-enable unit 12 (Anti_en). The part 41 is provided. And a second comparator for generating an anti-Y enable signal Anti_yen in accordance with the output signals of the second predecoder 34 and the second anti-free decoder 33. In addition, the anti-control unit 50 generates a read signal Anti_rd and a write signal Anti_write according to the signals generated by the first comparator 41 and the second comparator 42.

The sense amplifier 80, the anticell 170, and the anti-detector unit 180 are generated according to the read signal Anti_rd generated by the anti-control unit 50 and the signal ST_anti_det generated by the special test decoder 60. A register 100 for storing output data is connected to the output terminal of the read multiplexer 90 which multiplexes the output signal. The register 100 is connected with an output driver 110 for outputting data to a pad 120 which will be described later. The output driver has a TTL (Transistor-Transistor Logic) level of the data at a complementary metal-oxide-semiconductor (CMOS) level Switch to the level. The pad 120 outputs the data converted to the TTL level through the output driver to the external controller 190 and receives the TTL level data from the controller 190. The input buffer 130 is connected to the pad so that the level of data input to the pad 120 can be switched from the TTL level to the CMOS level. An input driver 140 is connected to an output terminal of the input buffer 130 to drive data converted to the CMOS level. The output terminal of the input driver 140 is not only connected to the write driver 160 but also to the anticell 170 and the antidetector unit 180 through the switching unit 150. In this case, an anti-enable signal Anti_en output from the anti-enable unit 12, a signal ST_anti_det generated from the special decoder decoder 60, and a data input strobb are input to an input of the anti-detector unit 180. do.

The controller 190 generates data for the special test and outputs the data to the pad 120, and determines whether to use the anti-fuse according to the data output from the pad 120.

3 is a circuit diagram illustrating an anti-detector unit according to the present invention.

The anti-enable signal Anti_en output from the anti-enable unit 12, the detection signal ST_anti_det generated by the special test decoder 60, and the data input strobb are input to the input terminal of the NAND gate ND1. . The output terminal of the NAND ND1 is connected to the PMOS gate of the transmission gate T1 through the inverter I1 and the inverter I2. At this time, the NMOS gate of the transmission gate T1 is connected to the output terminal of the inverter I1.

The anti-enable signal Anti_en is also connected to the input terminal of the NAND gate ND2 through the inverter I5, and the strobe and the detection signal ST_anti_det are input to the input terminal of the NAND gate ND2. . The output terminal of the NAND gate ND2 is connected to the PMOS gate of the transmission gate T2 through the inverter I6 and the inverter I7, and the output terminal of the inverter I6 is connected to the NMOS gate of the transmission gate T2.

On the other hand, the output gwd of the input driver 140 is input to the inverter I3, and the output terminal of the inverter I3 is connected to the transmission gate T1 through the inverter I4. In addition, the output terminal of the inverter I3 is connected to the transmission gate T2. The output terminals of the transmission gates T1 and T2 are connected to the inverter I10 through a buffer including the inverter I8 and the inverter I9. At this time, the output of the inverter I10 is anti_det_rd, and the signal is inverted by the inverter I11 to become anti_det_rdb.

4 is a block diagram illustrating a read multiple part according to the present invention.

The read multiplexer 90 may include a first multiplexer 91 for multiplexing the read data of the main cell 70 by a sense amplifier 80 and a second multiplexer for multiplexing the read data of the anticell 170. 92 and a third multiplexer 93 for multiplexing the data of the anti-detector unit 180.

FIG. 5 is a circuit diagram for describing the first multiplexer 91 of FIG. 4.

The first multiplexer 91 includes a NOR gate NR1 that combines the anti-read signal Anti_rd and the special test signal ST_anti_det, and an inverter I12 and an inverter at an output terminal of the NOR gate NR1. I13) is connected in series. And transmission gates T3 and T4 for outputting the read data rd and rdb of the main cell 70 in accordance with the output signals of the inverters I12 and I13.

When the anti-fuse is used, the anti-control unit 50 outputs the anti-read signal Anti_rd which is a high signal, and the NOR gate NR1 outputs a low signal according to the signal. The inverter I12 inverts the high signal output from the NOR gate NR1 to a low signal, and the low signal is inverted by the inverter I13 to become a high signal. This causes the transmission gates T3 and T4 to be turned off. Even in the special test mode, the above operation is performed.

FIG. 6 is a circuit diagram for describing the second multiplexer 92 of FIG. 4.

The second multiplexer 92 multiplexes the data of the anti-cell 170, and the inverter I14 and the anti-read signal Anti_rd and the inverted special test signal ST_ant_det invert the special test signal ST_anti_det. NAND gates ND3 are combined, and inverters I15 to I17 are connected in series at the output terminal of the NAND gate ND3. The transmission gates T5 and T6 output the read data rd and rdb of the main cell 70 according to the output signals of the inverters I16 and I17.

When the anti-fuse is used and not in the special test mode, the anti-read signal Anti_rd output by the anti-control unit 50 is a high signal, and the special test decoder 60 receives the special test signal ST_anti_det, which is a low signal. Output Accordingly, the NAND gate ND3 outputs a low signal. The low signal output from the NAND gate ND3 is inverted by the inverter I15 to become a high signal, and the signal is maintained by the inverter I16 and becomes a high signal by the inverter I17. As a result, the transmission gates T5 and T6 are turned on to transmit the read signals a_rd and a_rdb of the anticell 170 to the register 100.

However, when the special test decoder 60 outputs the special test signal ST_anti_det which is a high signal in the special test mode, the signal is converted into a low signal by the inverter I14 and input to the NAND gate ND3. As a result, the NAND gate ND3 outputs a high signal, and the signal is held by the inverters I15 and I16 and is converted into a low signal by the inverter I17. Accordingly, the transmission gates T5 and T6 are turned off.

FIG. 7 is a circuit diagram for describing the third multiplexer 93 of FIG. 4.

The third multiplexer 103 is an inverter I18 for inverting the special test signal ST_anti_det, and anti_det_rd which is read data of the anti-detector unit 180 according to the output signals of the special test signal ST_anti_det and the inverter I18. And a transmission gate (T7) and a transmission gate (T8) for outputting anti_det_rdb to mxout and mxoutb. In the non-special test mode, the special test decoder 60 outputs a low signal, and the signal is converted into a high signal by the inverter I18. Thus, the transmission gates T7 and T8 are turned off. However, in the special test mode, the special test decoder 60 outputs a high signal, and the signal is converted into a low signal by the inverter I27. As a result, the transmission gates T7 and T8 are turned on so that the read signals anti_det_rd and anti_det_rdb of the anti-detect cell 180 are transmitted to the register 100.

Operation according to the present invention is as follows.

The special test decoder 60 determines the special test mode according to ST <7: 8>. If it is determined that the decoding result of ST <7: 8> is the special test mode, the special test decoder 60 outputs a special test signal ST_anti_det that is a high signal. At this time, data is input from the outside through the pad 120. Data input to the pad 120 is converted to the CMOS level in the input buffer 130 and then input to the anti-detector unit 180 via the input driver 140.

Accordingly, the operation of the anti-detector unit 180 is as follows.

The data input strobb is a signal for strobing write data during a write operation, and the anti-en signal (Anti_en) signal is a high level signal when the anti-enable fuse 12 is programmed. As described above, in the special test mode, the special test signal ST_anti_det is a high signal.

When the anti-fuse is used, both the data input strobb, the anti-enable signal Anti_en, and the special test signal ST_anti_det are high signals. At this time, the NAND gate ND1, which is a three-input NAND gate, outputs a low signal, and the inverter INV1 converts the low signal output from the NAND gate ND1 into a high signal. Therefore, when a high signal is output from the inverter INV1, a high signal is applied to the NMOS gate of the transmission gate T1, and a low signal converted through the inverter INV2 is applied to the PMOS gate of the transmission gate T1. Gate T1 is turned on.

On the other hand, the inverter INV5 converts the anti-enable signal Anti_en, which is a high signal, into a low signal. Accordingly, the three-input NAND gate ND2 outputs a high signal, and the inverter INV6 receives the NAND gate ND2. Convert the high signal output from to low signal. Accordingly, a low signal is applied to the NMOS gate of the transmission gate T2, and a high signal converted through the inverter INV7 is applied to the PMOS gate of the transmission gate T2, so that the transmission gate T2 is turned off. As the transmission gate T1 is turned on and the transmission gate T2 is turned off, the antiphase signals of the input data gwd output from the input driver 140 are converted to the inverter INV8 and the inverter INV9. Is latched in. The input signal gwd and the in-phase signal are finally output by the inverter INV10 as the read data anti_det_rd of the anti-detector unit 180.

At this time, the first and second multiplexers of the read multiplexer 90 are disabled and only the third multiplexer 93 is enabled by the special test signal ST_anti_det output from the special test decoder 60. Therefore, the read data anti_det_rd of the anti-detector unit 180 is stored in the register 100, and after being converted to the TTL level by the output driver 110, the output data is output to the external controller 190 through the pad 120. )do. At this time, the controller 190 compares the data output from the pad 120 with the data generated first to determine whether the anti-fuse is used.

On the other hand, when the anti-fuse is not used, both the input strobb / special test signal ST_anti_det are high signals, and the anti-enable signal Anti_en is a low signal. At this time, the NAND gate ND1, which is a three-input NAND gate, outputs a low signal, and the inverter INV1 converts the low signal output from the NAND gate ND1 into a high signal. Therefore, when a high signal is output from the inverter INV1, a high signal is applied to the NMOS gate of the transmission gate T1, and a low signal converted through the inverter INV2 is applied to the PMOS gate of the transmission gate T1. Gate T1 is turned on.

The inverter INV5 converts the anti-enable signal Anti_en, which is a high signal, into a low signal. The three-input NAND gate ND2 outputs a high signal, and the inverter INV6 outputs from the NAND gate ND2. The high signal is converted into a low signal. Accordingly, a low signal is applied to the NMOS gate of the transmission gate T2, and a high signal converted through the inverter INV7 is applied to the PMOS gate of the transmission gate T2, so that the transmission gate T2 is turned off. As the transmission gate T1 is turned on and the transmission gate T2 is turned off, an antiphase signal of the data gwd output from the input driver 140 is transmitted to the inverters INV8 and INV9. Latched. The input signal gwd and the in-phase signal are finally output by the inverter INV10 as the read data anti_det_rd of the anti-detector unit 180.

At this time, the first and second multiplexers of the read multiplexer 90 are disabled and only the third multiplexer is enabled by the special test signal ST_anti_det output from the special test decoder 60. Therefore, the read data anti_det_rd of the anti-detector unit is stored in the register 100, is converted to the TTL level by the output driver 110, and then output to the external controller 190 through the pad 120. The controller 190 compares the first generated data with the data output from the pad 120 and determines whether anti-fuse is used.

As described above, when antifuse is used, the data input to the pad 120 and the output data are in the same phase. On the contrary, when the antifuse is used, the data input to the pad 120 and the output data have opposite phases. That is, the external controller 190 may determine whether to use the anti-fuse by comparing the data input through the pad 120 and the output data.

According to the test apparatus of the semiconductor device according to the present invention, it is possible to easily detect whether or not the anti-fuse of the sample that generates a bad bit after the package has the effect of reducing the test time and increase the yield.

Claims (5)

When the anti-fuse is programmed, the anti-enable section for generating an anti-enable signal, Anti-control unit for generating a control signal according to whether or not anti-fuse programming, A steady test decoder for generating a special test signal according to an external signal; An anti-detector unit for storing data input to the pad from the outside and outputting read data according to the special test signal and the anti-enable signal; A read multiple part outputting the read data of the anti-detector part to the pad according to the special test signal; And a control unit which not only generates data for a special test but also compares the generated data with data output to the pad to determine whether anti-fuse is used. The method of claim 1, The anti-detector unit may include a first NAND gate that combines a data input strobe, the anti-enable signal, and a special test signal; A first transmission gate transferring data input through the pad from the outside according to the output signal of the first NAND gate; A second NAND gate that combines an inverted signal of the anti-enable signal, a special test signal, and a data input strobe; A second transmission gate which inverts and transfers data input through the pad from the outside according to the output signal of the second NAND gate; A latch for storing output data of the first and second transmission gates, And an inverter for inverting the output of the latch and outputting read data. The method of claim 1, The read multiplexer may include: a first multiplexer multiplexed with read data of a main cell and disabled by any one of a special test signal or a control signal of the anti-control unit; A second multiplexer multiplexed with the anti-cell read data according to a control signal of the anti-control unit and disabled by the special test signal; And a third multiplexer enabled by the special test signal to multiplex the read data of the anti-detector unit. The method of claim 3, wherein The third multiplexer includes an inverter for inverting the special test signal; And a first transmission gate and a second transmission gate configured to output read data of the anti-detector unit based on the special test signal and an output signal of the inverter. The method of claim 1, The controller compares the phase of the data output from the pad with the data generated for the special test, and determines that antifuse is used in in-phase, and determines that antifuse is not used in reverse phase. Device.