KR20010066284A - Method for preventing variation of wafer to wafer thickness in a chemical vaper deposition - Google Patents
Method for preventing variation of wafer to wafer thickness in a chemical vaper deposition Download PDFInfo
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- KR20010066284A KR20010066284A KR1019990067883A KR19990067883A KR20010066284A KR 20010066284 A KR20010066284 A KR 20010066284A KR 1019990067883 A KR1019990067883 A KR 1019990067883A KR 19990067883 A KR19990067883 A KR 19990067883A KR 20010066284 A KR20010066284 A KR 20010066284A
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/52—Controlling or regulating the coating process
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/02—Pretreatment of the material to be coated
- C23C16/0227—Pretreatment of the material to be coated by cleaning or etching
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/34—Nitrides
- C23C16/345—Silicon nitride
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Abstract
본 발명은 반도체 제조 공정중 박막 증착 공정(Deposition)에 관한 것으로, 특히 박막 증착 공정에 따른 챔버(chammer)내 세정 공정의 영향으로 인한 웨이퍼의 두께 변화를 방지하는 박막 증착 공정에 있어서 웨이퍼별 두께 변화 방지 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film deposition process in a semiconductor manufacturing process. In particular, a thickness variation of each wafer in a thin film deposition process for preventing a change in thickness of a wafer due to an influence of a cleaning process in a chamber according to a thin film deposition process. It is about a prevention method.
이를 위하여 본 발명에서는, 금속층사이의 절연막 형성시 보다좋은 막질을 얻기 위하여 실제 공정 진행하기 전에 수행되는 챔버내의 먼지를 제거하기 위한 산화막(SiO2) 증착 공정이전에 산화막과 에치 선택비가 상이한 막을 증착하므로써, 세정시 표면 지지대의 알루미늄 성분이 노출되지 않도록 하여 동일 조건 웨이퍼내에서 웨이퍼별 두께 변화를 방지하도록 한다.To this end, in the present invention, in order to obtain a better film quality when forming an insulating film between the metal layer, by depositing a film having a different etch selectivity from the oxide film (SiO 2 ) before the deposition process to remove the dust in the chamber performed before the actual process proceeds. In order to prevent the aluminum component of the surface support from being exposed, the thickness change of each wafer in the wafer under the same conditions is prevented.
따라서, 본 발명은 소자의 신뢰성 및 안정성을 확보할 수 있는 효과를 얻을 수 있다.Therefore, the present invention can obtain the effect of ensuring the reliability and stability of the device.
Description
본 발명은 반도체 제조 공정중 박막 증착 공정(Deposition)에 관한 것으로,특히 박막 증착 공정에 따른 챔버(chammer)내 세정 공정의 영향으로 인한 웨이퍼의 두께 변화를 방지하는 박막 증착 공정에 있어서 웨이퍼 두께 변화 방지 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film deposition process in a semiconductor manufacturing process, and particularly to prevent a wafer thickness change in a thin film deposition process that prevents a change in wafer thickness due to an influence of a cleaning process in a chamber according to a thin film deposition process. It is about a method.
반도체 웨이퍼 제조 공정은 로트(lot) 단위의 매 반도체 웨이퍼의 상부 표면에 여러 종류의 막을 형성시켜, 이미 만들어진 마스크를 이용하여 반도체 웨이퍼의 특정 부분을 선택적으로 깍아내는 작업을 되풀이함으로서 반도체 웨이퍼상의 각각의 칩상에 동일한 전자 회로를 구성해나가는 전 과정을 의미한다.The semiconductor wafer fabrication process involves forming various kinds of films on the upper surface of each semiconductor wafer in a lot unit, and repeatedly scraping a specific portion of the semiconductor wafer using a mask made in advance. It means the whole process of constructing the same electronic circuit on the chip.
이러한 반도체 웨이퍼 제조 공정중의 하나인 박막 증착 공정은 가스를 공급하여 기판 표면에서 화학반응을 통해 박막 즉, 금속층사이의 층간 절연막을 형성하는 공정으로서, APCVD, LPCVD, PECVD 방법 등을 통하여 박막을 형성한다.The thin film deposition process, which is one of the semiconductor wafer manufacturing processes, is a process of forming a thin film, that is, an interlayer insulating film between metal layers through chemical reaction on a substrate surface by supplying gas, and forming a thin film through APCVD, LPCVD, PECVD, etc. do.
이 때, PECVD(Plasma Enhancement Chemical Vaper Deposition) 방법을 이용하여 웨이퍼상에 박막 즉, 산화막(SiO2)을 증착하는 경우 웨이퍼 전면을 균일(Uniform)하게 하기 위하여 웨이퍼가 위치한 영역보다 더 넓은 영역에 산화막(SiO2)을 증착하는 바, 웨이퍼가 위치한 영역외의 다른 영역 뿐만 아니라 챔버내 측벽에도 산화막이 증착되는 경우가 발생한다.At this time, in the case of depositing a thin film, that is, oxide film (SiO 2 ) on the wafer by using a Plasma Enhancement Chemical Vaper Deposition (PECVD) method, the oxide film is formed in a wider area than the area where the wafer is placed to uniform the entire surface of the wafer. As a result of depositing (SiO 2 ), an oxide film is deposited not only on the region where the wafer is located but also on the sidewalls of the chamber.
도 1은 상기한 PECVD 공정에 따른 챔버내 세정 공정 수행에 대한 단면도이다.1 is a cross-sectional view of performing an in-chamber cleaning process according to the above-described PECVD process.
우선, PECVD 공정을 수행하기 전 보다 좋은 막질을 얻기 위하여, 도 1a에 도시된 바와 같이 표면 지지대(Heaterblock)(10)상에 챔버내의 먼지들을 제거하기 위하여 TEOS 산화막(20)으로 사전 증착 공정을 수행한 후, 그 다음에 웨이퍼를 안착시키고 PECVD 공정을 통하여 사전 증착된 TEOS 산화막(20)위에 원하는 웨이퍼의 두께가 형성될 때 까지 산화막(30)을 형성한다.First, in order to obtain a better film quality before performing the PECVD process, a pre-deposition process is performed with the TEOS oxide film 20 to remove dusts in the chamber on the surface of the heaterblock 10 as shown in FIG. 1A. Thereafter, the wafer is then seated and an oxide film 30 is formed on the predeposited TEOS oxide film 20 through a PECVD process until the desired wafer thickness is formed.
이 때, 산화막(30) 형성은 상기한 바에서 설명한 바와 같이, 웨이퍼 전면을 균일하게 하기 위하여 웨이퍼가 위치한 영역보다 더 넓은 영역에 산화막을 증착하기 때문에 웨이퍼가 위치한 영역(40)외의 영역과 도면에는 도시되지 않았지만 챔버내 측벽에도 산화막이 증착되기 때문에 다음에 형성되는 웨이퍼의 두께에 영향을 미친다. 따라서, 적정 두께 이상의 웨이퍼를 형성한 다음 웨이퍼가 위치하였던 영역(40)외에 형성된 산화막(20, 30)제거하는 세정 공정을 수행하여야 하는 바, 도 1a에 도시된 바에서 알 수 있듯이, 가스 공급기(50)의 가스 분출구(60)를 통하여 세정 가스인 C2F6및 기타의 “F”성분이 포함된 세정 가스를 분출하여 산화막(20, 30)을 제거(에치)한다.At this time, the oxide film 30 is formed as described above, in order to make the entire surface of the wafer uniform, the oxide film is deposited in a wider area than the area where the wafer is located. Although not shown, an oxide film is also deposited on the sidewalls of the chamber, which affects the thickness of the next wafer to be formed. Therefore, after forming a wafer having an appropriate thickness and then performing a cleaning process of removing the oxide films 20 and 30 formed outside the region 40 where the wafer is located, as shown in FIG. 1A, as shown in FIG. The cleaning gas containing the cleaning gas C 2 F 6 and other “F” components is blown out through the gas ejection opening 60 of 50 to remove (etch) the oxide films 20 and 30.
즉, 도 1b에서와 같이 가스 분출구(60)로부터 산화막(20, 30)과 웨이퍼(40)가 위치하였던 영역(40)의 표면 지지대(10)상으로 C2F6가스가 분출되어, 산화막(20, 30)이 제거한다.That is, as shown in FIG. 1B, C 2 F 6 gas is ejected from the gas ejection opening 60 onto the surface support 10 of the region 40 in which the oxide films 20 and 30 and the wafer 40 are located. 20, 30) to remove.
이 때, 웨이퍼가 위치하였던 영역(40)과 산화막(20, 30)이 증착되었던 영역에 C2F6가스를 분출하여 산화막(20, 30)을 제거하는 바, 웨이퍼가 위치하였던 영역(40)과 산화막(20, 30)이 증착되었던 영역간에는 산화막 두께 차이가 발생한다. 즉, C2F6가스에 의하여 웨이퍼가 위치하였던 영역(40)외의 산화막(20, 30)을 에치하는 동안 웨이퍼가 위치하였던 영역(40)은 오버 에치(over etch)되어 표면 지지대(10)의 알루미늄(Al) 성분이 노출되는 현상이 발생한다(도 1c 참조).At this time, the C 2 F 6 gas is ejected to the region 40 where the wafer is located and the region where the oxide films 20 and 30 are deposited to remove the oxide films 20 and 30, and thus the region 40 where the wafer is located. An oxide film thickness difference occurs between the regions where the oxide films 20 and 30 are deposited. That is, the area 40 where the wafer is positioned is overetched while the oxide films 20 and 30 other than the area 40 where the wafer is located are etched by the C 2 F 6 gas so that the surface support 10 may be overetched. The phenomenon in which the aluminum (Al) component of is exposed (refer FIG. 1C).
여기서, 노출된 알루미늄(Al) 성분은 세정 가스 분출구(60)에서 분출되는 C2F6가스와 반응하게 되어 리스터퍼링(Resputtering)이 발생하여 AlF 또는 AlOXFY의 화합물 형태로 도 1c에서와 같이 가스 분출구(60)에 부착된다.Here, the exposed aluminum (Al) component reacts with the C 2 F 6 gas emitted from the cleaning gas outlet 60 to cause resputtering, resulting in a compound of AlF or AlO X F Y in FIG. 1C. It is attached to the gas outlet 60 as well.
따라서, 산화막(20, 30) 에치 공정이 거의 끝나갈 시점에는 도 1d에 도시된 바와 같이 가스 분출구(60)에 부착된 화합물 면적만큼 가스 분출구(60)의 표면적이 증가하게된다.Therefore, when the etching process of the oxide films 20 and 30 is almost finished, the surface area of the gas outlet 60 is increased by the area of the compound attached to the gas outlet 60 as shown in FIG. 1D.
이와 같이, 가스 분출구(60)의 표면적인 증가하게 되는 경우, 다음 웨이퍼 두께 형성시 도 2에 도시된 바와 같이 웨이퍼 두께의 변화(h) 즉, 감소하는 결과를 초래하게 되어, 적정 두께의 웨이퍼가 형성되지 않게되어 소자의 누설 전류 등의 문제점이 발생하는 바, 소자의 신뢰성 및 안정성이 떨어지는 문제점이 있었다.As such, when the surface area of the gas ejection hole 60 is increased, a change in the wafer thickness h, that is, a decrease in the thickness of the wafer, as shown in FIG. Since it is not formed to cause problems such as leakage current of the device, there was a problem that the reliability and stability of the device is inferior.
본 발명은 상기한 문제점을 해결하기 위하여 안출된 것으로서, 본 발명의 목적은 PECVD 공정에 따른 세정 공정시 세정 가스 분출구의 표면적의 증가로 인하여 발생되는 웨이퍼 두께 변화를 방지하므로써, 소자의 신뢰성 및 안정성을 확보하기 위한 박막 증착 공정에 있어서 웨이퍼별 두께 변화 방지 방법을 제공하는 데 있다.The present invention has been made to solve the above problems, an object of the present invention is to prevent the wafer thickness change caused by the increase in the surface area of the cleaning gas outlet in the cleaning process according to the PECVD process, thereby improving the reliability and stability of the device In the thin film deposition process to secure the thickness to provide a method for preventing the change of thickness for each wafer.
전술한 목적을 달성하기 위한 본 발명은, 적정 두께를 형성하고자하는 웨이퍼상의 산화막 증착이전에 챔버내 먼지 제거를 위한 사전 산화막을 증착하는 박막증착 공정에 있어서, 상기 사전 산화막 증착이전에 상기 사전 산화막과 에치 선택비가 상이한 막을 증착하는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a thin film deposition process for depositing a pre-oxide film for removing dust in a chamber prior to depositing an oxide film on a wafer to form an appropriate thickness. It is characterized by depositing films having different etch selectivity.
도 1은 종래 기술에 따른 박막 증착 공정에 있어서 챔버 세정 공정을 나타낸 단면도이고,1 is a cross-sectional view showing a chamber cleaning process in a thin film deposition process according to the prior art,
도 2는 챔버 세정 공정을 수행한 후의 웨이퍼별 두께 변화 감소를 나타낸 그래프이고,2 is a graph showing a decrease in thickness change for each wafer after the chamber cleaning process is performed.
도 3은 본 발명에 따른 박막 증착 공정에 있어서 웨이퍼별 두께 변화 방지 공정 과정을 나타낸 단면도이다.3 is a cross-sectional view showing a thickness change prevention process for each wafer in the thin film deposition process according to the present invention.
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
10 : 표면 지지대 20, 30 : 산화막10: surface support 20, 30: oxide film
40 : 웨이퍼가 놓였던 자리 50 : 가스 공급기40: where the wafer was placed 50: gas supply
60 : 가스 분출구 100 : 질화막60 gas outlet 100 nitride film
이하, 첨부된 도면을 참조하여 본 발명에 따른 바람직한 실시예의 동작을 상세하게 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the operation of the preferred embodiment according to the present invention.
도 3은 본 발명에 따른 웨이퍼별 두께 변화 감소 방지를 위한 PECVD 공정을 나타낸 도면으로서, 금속층사이의 절연막 형성을 위하여 챔버내의 먼지를 제거하기 위한 사전 산화막을 증착하기전에 산화막과 에치 선택비가 상이한 막을 증착하여 표면 지지대(10)의 알루미늄 성분이 노출되지 않도록 하여 웨이퍼별 두께 변화의 원인인 가스 분출구의 표면적 변화를 방지하기 위한 공정을 나타낸 도면이다.FIG. 3 is a view showing a PECVD process for preventing a change in thickness of each wafer according to the present invention, and depositing a film having a different oxide and etch selectivity before depositing a pre-oxide for removing dust in a chamber to form an insulating film between metal layers. To prevent the aluminum component of the surface support 10 from being exposed, thereby showing a process for preventing the surface area change of the gas ejection opening, which is the cause of the thickness change for each wafer.
도 3a에 도시된 바와 같이, 도 1a에 도시된 바와 같이 챔버내 먼지를 제거하기 위한 산화막 즉, TEOS 산화막(20)을 사전에 증착하기 전에 산화막(20, 30)과 에치 선택비가 상이한 막(100)을 표면 지지대(10)상에 증착한다.As shown in FIG. 3A, as shown in FIG. 1A, an oxide film for removing dust in the chamber, that is, a film 100 having a different etch selectivity from the oxide films 20 and 30 before the TEOS oxide film 20 is deposited in advance. ) Is deposited on the surface support 10.
이 때, 본 발명의 바람직한 실시예에서는 산화막(20, 30)과 에치 선택비가 예를 들어 1대 4로 할 경우, 즉, 산화막(20, 30)의 에치속도가 4를 진행할 경우 1의 에치 속도를 진행하는 막(100)으로 질화막(Si3N4)을 이용하였다.At this time, in the preferred embodiment of the present invention, when the etch selectivity of the oxide films 20 and 30 is, for example, 1 to 4, that is, when the etch rate of the oxide films 20 and 30 is 4, the etch rate of 1 is increased. A nitride film (Si 3 N 4 ) was used as the film 100 to proceed.
이와 같이, 산화막과 에치 선택비가 상이한 막으로 질화막(100)을 표면 지지대(10)상에 증착한 다음, 챔버내 먼지를 제거하기 위한 TEOS 산화막(20)을 증착하고(도 3b 참조), 두께를 형성하고자 하는 웨이퍼를 안착시킨다음, PECVD 방법을 통하여 사전 증착된 TEOS 산화막(20)위에 원하는 웨이퍼의 두께가 형성될 때 까지 산화막(30)을 증착한다.As such, the nitride film 100 is deposited on the surface support 10 with a film having a different etch selectivity from the oxide film, and then a TEOS oxide film 20 is deposited to remove dust in the chamber (see FIG. 3B), and the thickness is reduced. After depositing the wafer to be formed, the oxide film 30 is deposited on the pre-deposited TEOS oxide film 20 through the PECVD method until the desired wafer thickness is formed.
이 때, PECVD 방법을 이용하여 산화막(30)을 증착하여 원하는 두께를 갖는 웨이퍼가 형성되면, 웨이퍼가 위치하였던 영역(40)외의 영역에 증착된 산화막(20, 30)과 챔버내 측벽에 증착된 산화막을 제거하기 위하여 가스 공급기(50)의 가스 분출구(60)를 통하여 C2F6가스를 분출시킨다(도 3c 및 3d 참조).At this time, when the oxide film 30 is deposited using a PECVD method to form a wafer having a desired thickness, the oxide films 20 and 30 deposited on the regions other than the region 40 where the wafer is located are deposited on the sidewalls of the chamber. In order to remove the oxide film, the C 2 F 6 gas is ejected through the gas ejection opening 60 of the gas supply 50 (see FIGS. 3C and 3D).
이 때, C2F6가스에 의하여 에치시, 표면 지지대(10)상의 웨이퍼가 위치하였던 영역(40)에는 3a에서와 같이 산화막(20, 30)과 에치 선택비가 상이한 막 즉, 질화막이 증착되어 있는 상태이므로 웨이퍼가 위치하지 않은 영역의 산화막(20, 30)의 에치 속도와 웨이퍼가 위치하였던 영역(40)의 에치 속도는 상이하게 된다.At this time, upon etching by the C 2 F 6 gas, a film having a different etching selectivity from the oxide films 20 and 30, that is, a nitride film, is deposited in the region 40 where the wafer on the surface support 10 is located, as in 3a. In this state, the etch rates of the oxide films 20 and 30 in the region where the wafer is not positioned are different from the etch rates of the region 40 in which the wafer is located.
즉, 웨이퍼가 위치하였던 영역(40)과 웨이퍼가 위치하지 않은 영역의 산화막(20, 30)의 에치 속도가 4로 진행될 경우, 웨이퍼가 위치하였던 영역(40)의 에치 속도는 1로 진행하므로써 웨이퍼가 위치하지 않았던 영역의 산화막(20, 30)이 전부 에치되는 동안 웨이퍼가 위치하였던 영역(40)의 질화막의 에치 속도는 1로 진행되어 웨이퍼가 위치하지 않은 영역의 산화막(20, 30)의 에치가 끝나도 웨이퍼가 위치하였던 영역(40)의 에치는 끝나지 않게된다.That is, when the etch rate of the oxide films 20 and 30 in the region 40 where the wafer is located and the region where the wafer is not positioned is 4, the etch rate of the region 40 where the wafer is located is 1 so that the wafer The etching rate of the nitride film of the region 40 where the wafer is located is advanced to 1 while the oxide films 20 and 30 of the region where the wafer is not positioned are all etched to the edges of the oxide films 20 and 30 of the region where the wafer is not located. Even if the end is etched, the etch in the region 40 where the wafer is located is not finished.
따라서, 도 3e에 도시된 바와같이 웨이퍼가 위치하지 않은 영역의 산화막(20, 30)이 에치되어도 웨이퍼가 위치하였던 영역(40)의 질화막은 에치가 끝나지 않은 상태이므로 표면 지지대(10)의 알루미늄 성분이 노출되지 않게되어, 종래에서와 같이 가스 분출구(60)의 표면적이 증가하지 않게된다.Therefore, as shown in FIG. 3E, even when the oxide films 20 and 30 of the region where the wafer is not etched are etched, the nitride film of the region 40 where the wafer is positioned is not etched, so that the aluminum component of the surface support 10 is not present. This is not exposed, so that the surface area of the gas jet port 60 does not increase as in the prior art.
이상에서 설명한 바와 같이, 본 발명에 따른 박막 증착 공정에 있어서 웨이퍼 두께 변화 방지 방법은, 금속층사이의 절연막 형성을 위하여 챔버내의 먼지를 제거하기 위한 사전 산화막을 증착하기전에 산화막과 에치 선택비가 상이한 막을 증착한 후 사전 산화막을 증착하므로써, 세정시 표면 지지대(10)의 알루미늄 성분이 노출되지 않도록 하여 웨이퍼별 두께 변화를 방지하도록 한다.As described above, in the thin film deposition process according to the present invention, the method for preventing wafer thickness variation deposits a film having a different etch selectivity from the oxide film before depositing a pre-oxide film for removing dust in the chamber to form an insulating film between the metal layers. After that, by depositing a pre-oxide film, the aluminum component of the surface support 10 is not exposed during cleaning to prevent a change in thickness for each wafer.
따라서, 본 발명은 소자의 신뢰성 및 안정성을 확보할 수 있는 효과를 얻을 수 있다.Therefore, the present invention can obtain the effect of ensuring the reliability and stability of the device.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57204134A (en) * | 1981-06-11 | 1982-12-14 | Yamagata Nippon Denki Kk | Etching method for silicon nitride film |
| JPH0262038A (en) * | 1988-08-27 | 1990-03-01 | Sony Corp | Dry etching |
| JPH06349818A (en) * | 1993-06-14 | 1994-12-22 | Kawasaki Steel Corp | Manufacture of semiconductor device |
| JPH1116845A (en) * | 1997-06-11 | 1999-01-22 | Applied Materials Inc | Reduction of mobile ion and metal contamination in HDP-CVD chambers using chamber seasoning film deposition |
| KR19990032347A (en) * | 1997-10-17 | 1999-05-15 | 윤종용 | Double oxide film formation method |
| JPH11162880A (en) * | 1997-12-02 | 1999-06-18 | Nec Corp | Equipment and method for manufacture of semiconductor device |
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1999
- 1999-12-31 KR KR1019990067883A patent/KR20010066284A/en not_active Ceased
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57204134A (en) * | 1981-06-11 | 1982-12-14 | Yamagata Nippon Denki Kk | Etching method for silicon nitride film |
| JPH0262038A (en) * | 1988-08-27 | 1990-03-01 | Sony Corp | Dry etching |
| JPH06349818A (en) * | 1993-06-14 | 1994-12-22 | Kawasaki Steel Corp | Manufacture of semiconductor device |
| JPH1116845A (en) * | 1997-06-11 | 1999-01-22 | Applied Materials Inc | Reduction of mobile ion and metal contamination in HDP-CVD chambers using chamber seasoning film deposition |
| KR19990032347A (en) * | 1997-10-17 | 1999-05-15 | 윤종용 | Double oxide film formation method |
| JPH11162880A (en) * | 1997-12-02 | 1999-06-18 | Nec Corp | Equipment and method for manufacture of semiconductor device |
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