KR20010063286A - Signature circuit which provides information concerning a semiconductor integrated circuit - Google Patents

Abstract

The semiconductor memory device disclosed herein includes a pad for data output and a pipeline connected to the pad and having a plurality of latch stages. Each latch stage of the pipeline is initialized to one of a logic low level and a logic high level at power up. The logic levels of the latch stages so initialized are used as information of the memory device. According to such a device, information related to the assembled semiconductor memory device can be stored without deteriorating the characteristics of the memory device.

Description

SIGNATURE CIRCUIT WHICH PROVIDES INFORMATION CONCERNING A SEMICONDUCTOR INTEGRATED CIRCUIT}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor integrated circuits, and more particularly, to a signature circuit for providing information related to semiconductor integrated circuit memory devices.

The characteristics of semiconductor integrated circuit memory dies (or chips) (eg, threshold voltage, saturation current, DC, AC, etc. of a transistor) are measured in several steps at the wafer level prior to packaging. Thereafter, the semiconductor integrated circuit memory dies integrated on the wafer are assembled into corresponding packages. After assembly, there is a need to verify the properties measured at the wafer level with respect to each die. That is, there is a need to identify the location in the wafer prior to assembly for each of the assembled dies.

Various methods for making this possible are described in US Patent No. 4,806,793 entitled “ SIGNATURE CIRCUIT RESPONSIVE TO AN INPUT SIGNAL ”, US Pat. 4,480,199 entitled " IDENTIFICATION OF REPAIRED INTERGRATED CIRCUIT ", and US Patent No. 5,818,285, entitled " FUSE SIGNATURE CIRCUITS FOR MICROELECTRONIC DEVICES, " respectively.

One such method is to use the presence or absence of current flow by fuse cutting. Referring to Figure 1, a circuit diagram showing a signature circuit according to the prior art is shown. The signature circuit of FIG. 1 is composed of a DQ pad for data input / output, a fuse F1 connected in series between the DQ pad and a power supply, and a plurality of NMOS transistors M1, M2, M3, and M4. The signature circuit of FIG. 2 may store information depending on whether the fuse F1 is cut off.

However, as the operation speed of semiconductor memory devices is gradually increased, the signature circuit connected to the data line serves as a cause of impairing the AC characteristics of the semiconductor integrated circuit memory device. That is, since the signature circuit connected to the data line affects the input resistance, input capacitance, and the like for the DQ pad, it acts as a cause of impairing the AC characteristics of the semiconductor integrated circuit memory device.

It is an object of the present invention to provide a signature circuit of a semiconductor integrated circuit memory device capable of storing information relating to an assembled die without degrading the characteristics of the memory device.

1 is a circuit diagram showing a signature circuit according to the prior art;

2 is a block diagram showing a pipeline used as a signature circuit according to the present invention;

3 is a circuit diagram showing the latch of FIG. 2 in accordance with a preferred embodiment of the present invention;

4 is an embodiment of a reset signal generator for generating reset signals for initializing the latch of FIG. And

FIG. 5 is a timing diagram illustrating a relationship between signals used in FIG. 3.

* Description of the symbols for the main parts of the drawings *

100, 110: register

According to a feature of the present invention for achieving the above object, a semiconductor memory device comprises a pad for outputting data; A pipeline coupled to the pad, the pipeline having a plurality of latch stages, each latch stage of the pipeline initialized to either a logic low level or a logic high level upon power up.

In this embodiment, the pipeline is used as a signature circuit for storing information of the memory device.

In this embodiment, each latch stage includes: an input terminal for receiving data; An output terminal for outputting the data; A latch coupled between the input terminal and the output terminal; An input terminal of the latch having a first fuse connected to a first power supply voltage through a corresponding transistor and a second fuse connected to a second power supply voltage through a corresponding transistor, and at power up according to a connection state of the first and second fuses Initialization means for initializing the.

With such an apparatus, location information at the wafer level for each die, i.e., die information, can be stored by selectively cutting fuses of registers having a pipelined structure connected to a particular DQ pad in relation to individual die at the wafer level.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments according to the present invention will now be described based on reference figures.

Rambus DRAM, well known in the art, is provided with two registers (constituting the pipeline) connected in parallel to each of the DQ pads for data output. Each of the registers corresponding to any DQ pad includes a plurality of latches. One of the registers accepts data when the clock signal is held at a first logic level (eg, logic high) and receives data input when the clock signal is held at a second logic level (eg, logic low). Output The other register outputs data when the clock signal is held at the first logic level and accepts data when the clock signal is held at the second logic level. The present invention implements the signature circuit using the registers of the Rambus DRAM described above so that the signature circuit does not affect the input resistance, input capacitance, etc. to the DQ pad.

Referring to FIG. 2, registers 100 and 110 are shown, corresponding to one DQ pad, provided to the Rambus DRAM. Each register 100 and 110 operates in synchronization with the clock signal CLK and includes four latch stages connected in series. In other words, each register functions as a shift register responsive to the clock signal CLK. Each latch stage of the register 100 accepts data bits when the clock signal CLK is at a logic high level, and each latch stage of register 100 is configured to receive input data bits when the clock signal CLK is at a logic low level. Output Similarly, each latch stage of register 110 accepts data bits when clock signal CLK is at a logic low level, and each latch stage of register 110 is input data when clock signal CLK is at a logic high level. Output a bit. According to the present invention, the latch stages provided to each register can be programmed to an initial value required by the initialization signals RESET and RESETB at power-on. In more detail, it is as follows.

As shown in FIG. 3, each latch stage of each register 100, 110 includes first and second switches S1 and S2, a latch L consisting of two inverters, and fuses F2 and F3. ), And PMOS and NMOS transistors (M5, M6). The switch S1 is composed of connected PMOS and NMOS transistors as shown, and when the clock signals CLK and CLKB are at the logic high level and the logic low level, the data Din is input to the input terminal ND of the latch L. ). The switch S2 is composed of connected PMOS and NMOS transistors as shown, and follows the data Din held in the latch L when the clock signals CLK and CLKB are at the logic low and logic high levels. Transfer to the latch stage located in the stage.

Between the input terminal ND of the latch L and the power supply, as illustrated in FIG. 3, the PNOS transistor M5 and the fuse F2 are connected in series. The gate of the PMOS transistor M5 is connected to the initialization signal RESETB. Similarly, the NMOS transistor M6 and the fuse F2 are connected in series between the input terminal ND of the latch L and the power supply, as shown in FIG. The gate of the NMOS transistor M6 is connected to the complementary signal RESET of the signal RESETB.

Here, the fuses F2 and F3 and the transistors M5 and M6 function as means for initializing the input terminal ND of the latch stage.

As shown in FIG. 4, the signals RESETB and RESET applied to the gates of the transistors M5 and M6 are connected using two inverters INV1 and INV2 connected in series and a signal VCCH. It was created. The signal RESET is a signal having a level complementary to the signal VCCH, and the signal RESETB is a signal having the same level as the signal VCCH (see Fig. 5).

According to this configuration, the node ND of the latch stage may be set to a logic low level or a logic high level depending on the connection state of the fuse at power up. For example, transistors M5 and M6 are turned on for a predetermined time by signals RESET and RESETB at power-on. If fuse F2 is cut and fuse F3 is not cut, node ND is precharged to a logic low level. In contrast, if fuse F3 is cut and fuse F2 is not cut, node ND is precharged to a logic high level. By programming each latch stage in this manner, 8-bit data used as die information can be stored in registers corresponding to any DQ pad.

As described above, location information at the wafer level for each die, i.e., die information, can be stored by selectively cutting fuses of registers having a pipelined structure connected to a particular DQ pad with respect to the individual die at the wafer level. As a result, it is possible to store information related to the assembled die without deteriorating the characteristics of the memory device.

Claims (3)

A pad for outputting data; A pipeline coupled to the pad, the pipeline having a plurality of latch stages, And each latch stage of the pipeline is initialized to one of a logic low level and a logic high level at power up. The method of claim 1, And the pipeline is used as a signature circuit to store information of the memory device. The method of claim 1, Each latch end is An input terminal for receiving data; An output terminal for outputting the data; A latch coupled between the input terminal and the output terminal; An input terminal of the latch having a first fuse connected to a first power supply voltage through a corresponding transistor and a second fuse connected to a second power supply voltage through a corresponding transistor, and at power up according to a connection state of the first and second fuses And initialization means for initializing the memory.