KR20010061122A - A method for forming a field oxide of semiconductor device - Google Patents
A method for forming a field oxide of semiconductor device Download PDFInfo
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- KR20010061122A KR20010061122A KR1019990063608A KR19990063608A KR20010061122A KR 20010061122 A KR20010061122 A KR 20010061122A KR 1019990063608 A KR1019990063608 A KR 1019990063608A KR 19990063608 A KR19990063608 A KR 19990063608A KR 20010061122 A KR20010061122 A KR 20010061122A
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- 238000000034 method Methods 0.000 title claims abstract description 50
- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 238000002955 isolation Methods 0.000 claims abstract description 31
- 150000004767 nitrides Chemical class 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 11
- 229920005591 polysilicon Polymers 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 2
- 238000010030 laminating Methods 0.000 claims description 2
- 239000002002 slurry Substances 0.000 claims description 2
- 230000010354 integration Effects 0.000 abstract description 5
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000005498 polishing Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000009545 invasion Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000009271 trench method Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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Abstract
본 발명은 반도체소자의 소자분리막 형성방법에 관한 것으로,The present invention relates to a method of forming a device isolation film of a semiconductor device,
반도체기판 상부에 패드산화막, 패드질화막 및 식각정지막을 적층하고 상기 식각정지막, 패드질화막, 패드산화막 및 일정두께의 반도체기판을 식각하여 트렌치를 형성한 다음, 상기 트렌치를 매립하는 트렌치 매립용 절연막을 증착하고 상기 트렌치 매립용 절연막을 CMP 하되, 상기 식각정지막이 같이 식각된 다음, 상기 패드질화막을 제거하는 공정으로 활성영역의 공정마진을 확보할 수 있어 반도체소자의 고집적화를 가능하게 하는 기술이다.A pad oxide layer, a pad nitride layer, and an etch stop layer are stacked on the semiconductor substrate, the etch stop layer, the pad nitride layer, the pad oxide layer, and the semiconductor substrate having a predetermined thickness are etched to form a trench, and then a trench filling insulating layer filling the trench is formed. CMP is deposited and the trench filling insulating film is etched, the etch stop film is etched together, and the pad nitride film is removed to secure a process margin of an active region, thereby enabling high integration of semiconductor devices.
Description
본 발명은 반도체소자의 소자분리막 형성방법에 관한 것으로, 특히 트렌치형 소자분리막 형성공정중 하나인 CMP 공정시 패드질화막의 상측 끝부분이 라운딩 되는 현상으로 인한 소자의 특성 열화를 방지하는 기술에 관한 것이다.The present invention relates to a method of forming a device isolation film of a semiconductor device, and more particularly, to a technology for preventing deterioration of device characteristics due to the rounding of the upper end of the pad nitride film during the CMP process, which is one of the trench type device isolation film formation processes. .
고집적화라는 관점에서 소자의 집적도를 높이기 위해서는 각각의 소자 디맨젼 ( dimension ) 을 축소하는 것과, 소자간에 존재하는 분리영역 ( isolation region ) 의 폭과 면적을 축소하는 것이 필요하며, 이 축소정도가 셀의 크기를 좌우한다는 점에서 소자분리기술이 메모리 셀 사이즈 ( memory cell size ) 를 결정하는 기술이라고 할 수 있다.In order to increase the integration of devices from the viewpoint of high integration, it is necessary to reduce each device dimension and to reduce the width and area of isolation regions existing between devices. Device isolation technology determines the memory cell size in terms of size.
소자분리절연막을 제조하는 종래기술로는 절연물 분리방식의 로코스 ( LOCOS : LOCal Oxidation of Silicon, 이하에서 LOCOS 라 함 ) 방법, 실리콘기판상부에 산화막, 다결정실리콘층, 질화막순으로 적층한 구조의 피.비.엘. ( Poly - Buffed LOCOS, 이하에서 PBL 이라 함 ) 방법, 기판에 홈을 형성한 후에 절연물질로 매립하는 트렌치 ( trench ) 방법 등이 있다.Conventional techniques for manufacturing device isolation insulating films include LOCOS (LOCOS: LOCOS) method, an oxide film, a polysilicon layer, and a nitride film on a silicon substrate. B.L. (Poly-Buffed LOCOS, hereinafter referred to as PBL) method, a trench method of embedding an insulating material after forming a groove in the substrate, and the like.
그러나, 상기 LOCOS 방법으로 소자분리산화막을 미세화할 때 공정상 또는 전기적인 문제가 발생한다. 그중의 하나는, 소자분리절연막만으로는 전기적으로 소자를 완전히 분리할 수 없다는 것이다.However, a process or electrical problem occurs when the device isolation oxide film is miniaturized by the LOCOS method. One of them is that the device isolation insulating film alone cannot completely separate the device.
그리고, 상기 PBL 을 사용하는 경우, 필드산화시에 산소의 측면확산에 의하여 버즈빅이 발생한다. 즉, 활성영역이 작아져 활성영역을 효과적으로 활용하지 못하며, 필드산화막의 두께가 두껍기 때문에 단차가 형성되어 후속공정에 어려움을 준다. 그리고, 기판상부의 다결정실리콘층으로 인하여 필드산화시 기판내부로 형성되는 소자분리절연막이 타기법에 비하여 상대적으로 작기 때문에 타기법에 비해 신뢰성을 약화시킬 수 있다.In the case of using the above-mentioned PBL, buzz big is generated by side diffusion of oxygen during field oxidation. In other words, the active area is small, so that the active area is not effectively utilized, and because the thickness of the field oxide film is thick, a step is formed, which causes difficulty in subsequent processes. Further, due to the polysilicon layer on the substrate, the device isolation insulating film formed inside the substrate during field oxidation is relatively smaller than that of the hitting method, thereby reducing the reliability of the hitting method.
이상에서 설명한 LOCOS 방법과 PBL 방법은 반도체기판 상부로 볼록한 소자분리절연막을 형성하여 단차를 갖게 됨으로써 후속공정을 어렵게 하는 단점이 있다.The LOCOS method and the PBL method described above have a disadvantage in that a subsequent step is made difficult by forming a convex element isolation insulating film on the semiconductor substrate and having a step.
이러한 단점을 해결하기 위하여, 반도체기판을 식각하여 트렌치를 형성하고 상기 트렌치를 매립한 다음, CMP 방법을 이용하여 상부면을 평탄화시키고 후속공정을 평탄화시킴으로써 후속공정을 용이하게 실시할 수 있도록 하였다.In order to solve this disadvantage, the semiconductor substrate is etched to form a trench, and the trench is buried, and then the CMP method is used to planarize the top surface and to planarize the subsequent process so that the subsequent process can be easily performed.
도 1a 내지 도 1e 는 종래기술에 따른 반도체소자의 소자분리막 형성방법을 설명하면 다음과 같다.1A to 1E illustrate a device isolation film forming method of a semiconductor device according to the prior art as follows.
먼저, 반도체기판(11) 상부에 패드산화막(13)을 형성하고, 상기 패드산화막(13) 상부에 패드질화막(15)을 형성한다. (도 1a)First, a pad oxide film 13 is formed on the semiconductor substrate 11, and a pad nitride film 15 is formed on the pad oxide film 13. (FIG. 1A)
그리고, 소자분리마스크를 이용한 식각공정으로 상기 패드질화막(15)과 패드산화막(13) 및 일정두께의 반도체기판(11)을 식각하여 상기 반도체기판(11)에 트렌치(17)를 형성한다. (도 1b)The pad nitride layer 15, the pad oxide layer 13, and the semiconductor substrate 11 having a predetermined thickness are etched by an etching process using an element isolation mask to form a trench 17 in the semiconductor substrate 11. (FIG. 1B)
그 다음에, 라운딩 산화 공정을 실시하고 상기 트렌치(17)를 매립하는 트렌치 매립용 산화막(19)을 형성한 다음, 상기 산화막(19)을 화학기계연마 ( chemical mechenical polishing, 이하에서 CMP 라 함 ) 하여 상부면을 평탄화한다.Next, a round oxidation process is performed to form a trench filling oxide film 19 filling the trench 17, and then the oxide film 19 is referred to as chemical mechanical polishing (hereinafter referred to as CMP). To flatten the top surface.
이때, 상기 패드질화막(15)의 모서리 부분이 라운딩된다. (도 1c, 도 1d)At this time, the corner portion of the pad nitride film 15 is rounded. (FIG. 1C, FIG. 1D)
그 다음, 상기 패드질화막(15)을 제거하여 소자분리막(21)을 형성한다. 이때, 상기 CMP 공정시 라운딩된 패드질화막(15)으로 인하여 ⓐ 와 같이 활성영역 측으로 라운딩되어 소자분리막(21)이 구비된다. (도 1e)Next, the pad nitride layer 15 is removed to form the device isolation layer 21. In this case, the device isolation film 21 is provided by rounding to the active region as shown by ⓐ due to the pad nitride film 15 that is rounded during the CMP process. (FIG. 1E)
상기한 바와같이 종래기술에 따른 반도체소자의 소자분리막 형성방법은, 트렌치 매립용 산화막의 CMP 공정시 식각정지막으로 사용되는 패드질화막의 모서리 부분이 라운딩되어 상기 CMP 된 트렌치 매립용 산화막이 활성영역 측으로 라운딩되어 침범함으로써 활성영역의 공정마진을 감소시키고 그에 따른 반도체소자의 고집적화를 어렵게 하는 문제점이 있다.As described above, in the method of forming a device isolation film of a semiconductor device according to the prior art, the corner portion of the pad nitride film used as an etch stop layer in the CMP process of the trench filling oxide film is rounded so that the CMP trench filling oxide film is turned to the active region side. As a result of rounding and invasion, the process margin of the active region is reduced, thereby making it difficult to integrate the semiconductor device.
본 발명은 상기한 종래기술의 문제점을 해결하기위하여, 패드질화막 상부에 식각정지막을 형성하고 소자분리막으로 사용될 트렌치 매립용 산화막의 CMP 공정을 실시하여 패드질화막의 라운딩 현상을 방지하여 활성영역의 공정마진을 확보할 수 있도록 함으로써 반도체소자의 고집적화를 가능하게 하는 반도체소자의 소자분리막 형성방법을 제공하는데 그 목적이 있다.In order to solve the above problems of the prior art, an etching stop layer is formed on the pad nitride layer, and a CMP process of the trench buried oxide layer to be used as the device isolation layer is performed to prevent rounding of the pad nitride layer, thereby preventing a process margin of the active region. It is an object of the present invention to provide a method for forming a device isolation film of a semiconductor device that enables the high integration of the semiconductor device by ensuring the stability.
도 1a 내지 도 1e 는 종래기술에 따른 반도체소자의 소자분리막 형성방법을 도시한 단면도.1A to 1E are cross-sectional views illustrating a method of forming a device isolation film of a semiconductor device according to the prior art.
도 2a 내지 도 2f 는 본 발명의 실시예에 따른 반도체소자의 소자분리막 형성방법을 도시한 단면도.2A to 2F are cross-sectional views illustrating a method of forming an isolation layer in a semiconductor device according to an embodiment of the present invention.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
11,31 : 반도체기판 13,33 : 패드산화막11,31: semiconductor substrate 13,33: pad oxide film
15,35 : 패드질화막 17,39 : 트렌치15,35: pad nitride film 17,39: trench
19,41 : 트렌치 매립용 산화막 21,43 : 소자분리막19,41 oxide film for trench filling 21,43 device isolation film
37 : 폴리실리콘막 ⓐ : 라운딩된 소자분리막37 polysilicon film ⓐ rounded device isolation film
ⓑ : 수직한 구조의 소자분리막Ⓑ: device isolation film with vertical structure
이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 소자분리막 형성방법은,In order to achieve the above object, a device isolation film forming method of a semiconductor device according to the present invention,
반도체기판 상부에 패드산화막, 패드질화막 및 식각정지막을 적층하는 공정과,Laminating a pad oxide film, a pad nitride film, and an etch stop film on the semiconductor substrate;
상기 식각정지막, 패드질화막, 패드산화막 및 일정두께의 반도체기판을 식각하여 트렌치를 형성하는 공정과,Forming a trench by etching the etch stop film, the pad nitride film, the pad oxide film, and the semiconductor substrate having a predetermined thickness;
상기 트렌치를 매립하는 트렌치 매립용 절연막을 증착하는 공정과,Depositing a trench filling insulating film to fill the trench;
상기 트렌치 매립용 절연막을 CMP 하되, 상기 식각정지막이 같이 식각되는 공정과,CMP the insulating layer for filling the trench, wherein the etching stop layer is etched together;
상기 패드질화막을 제거하는 공정을 포함하는 것을 특징으로한다.And removing the pad nitride film.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2f 는 본 발명의 실시예에 따른 반도체소자의 소자분리막 형성방법을 도시한 단면도이다.2A through 2F are cross-sectional views illustrating a method of forming an isolation layer in a semiconductor device according to an embodiment of the present invention.
먼저, 반도체기판(31) 상부에 패드산화막(33)을 50 ∼ 100 Å 두께 형성하고, 상기 패드산화막(33) 상부에 패드질화막(35)을 1000 ∼ 1200 Å 두께 형성한다. (도 2a)First, a pad oxide film 33 is formed on the semiconductor substrate 31 by 50 to 100 mm thick, and a pad nitride film 35 is formed on the pad oxide film 33 to 1000 to 1200 mm thick. (FIG. 2A)
그리고, 상기 패드질화막(35) 상부에 식각정지막인 폴리실리콘막(37)을 50 ∼ 100 Å 두께 형성한다. (도 2b)Then, a polysilicon film 37, which is an etch stop film, is formed on the pad nitride film 35 at a thickness of 50 to 100 mm. (FIG. 2B)
그 다음, 소자분리마스크를 이용한 식각공정으로 상기 상기 폴리실리콘막(37), 패드질화막(35), 패드산화막(33) 및 일정두께의 반도체기판(31)을 식각하여 상기 반도체기판(31)에 트렌치(39)를 형성한다. (도 2c)Next, the polysilicon layer 37, the pad nitride layer 35, the pad oxide layer 33, and the semiconductor substrate 31 having a predetermined thickness are etched by an etching process using an element isolation mask. The trench 39 is formed. (FIG. 2C)
그 다음에, 상기 트렌치(39)를 매립하는 트렌치 매립용 산화막(41)을 형성하고, 상기 산화막(41)을 화학기계연마 ( chemical mechenical polishing, 이하에서 CMP 라 함 ) 하여 상부면을 평탄화한다.Next, an oxide filling film 41 for filling the trench 39 is formed, and the oxide film 41 is subjected to chemical mechanical polishing (hereinafter referred to as CMP) to planarize the upper surface thereof.
이때, 상기 패드질화막(35)의 모서리 부분이 라운딩되지않는 대신 상기 폴리실리콘막(37)이 식각된다.At this time, the edge portion of the pad nitride layer 35 is not rounded, but the polysilicon layer 37 is etched.
그리고, 상기 CMP 공정은 폴리실리콘과의 식각선택비가 8∼13 : 1 인 산화막용 슬러리를 사용한다.The CMP process uses an oxide film slurry having an etching selectivity of 8-13: 1 with polysilicon.
그리고, 상기 CMP 공정은 상기 식각정지막이 식각될때까지만 실시한다. (도2d, 도 2e)The CMP process is performed only until the etch stop layer is etched. (FIG. 2D, FIG. 2E)
그 다음, 상기 패드질화막(35)을 제거하여 소자분리막(41)을 형성한다. 이때, 상기 CMP 공정시 라운딩된 패드질화막(35)으로 인하여 ⓐ 와 같이 활성영역 측으로 라운딩되어 소자분리막(41)이 구비된다. (도 2f)Next, the pad nitride layer 35 is removed to form the device isolation layer 41. In this case, the device isolation film 41 is provided by the pad nitride film 35 that is rounded toward the active region as shown by ⓐ during the CMP process. (FIG. 2F)
이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 소자분리막 형성방법은, 패드질화막 상부에 식각정지막으로 폴리실리콘을 형성하여 CMP 공정시 패드질화막의 라운딩 현상을 방지하여 활성영역의 공정 마진을 확보함으로써 반도체소자의 고집적화를 가능하게 하는 효과를 제공한다.As described above, in the method of forming a device isolation film of a semiconductor device according to the present invention, polysilicon is formed on the pad nitride film as an etch stop film to prevent rounding of the pad nitride film during the CMP process, thereby securing a process margin of the active region. It provides an effect that enables high integration of semiconductor devices.
Claims (7)
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| KR1019990063608A KR20010061122A (en) | 1999-12-28 | 1999-12-28 | A method for forming a field oxide of semiconductor device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100771892B1 (en) * | 2007-02-06 | 2007-11-01 | 삼성전자주식회사 | Manufacturing method of semiconductor device having planarized film without dishing phenomenon |
| KR100798802B1 (en) * | 2001-12-31 | 2008-01-29 | 주식회사 하이닉스반도체 | Method of forming device isolation film of semiconductor device |
| KR100849064B1 (en) * | 2002-07-10 | 2008-07-30 | 주식회사 하이닉스반도체 | Method for forming an element isolation film of a semiconductor element |
-
1999
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100798802B1 (en) * | 2001-12-31 | 2008-01-29 | 주식회사 하이닉스반도체 | Method of forming device isolation film of semiconductor device |
| KR100849064B1 (en) * | 2002-07-10 | 2008-07-30 | 주식회사 하이닉스반도체 | Method for forming an element isolation film of a semiconductor element |
| KR100771892B1 (en) * | 2007-02-06 | 2007-11-01 | 삼성전자주식회사 | Manufacturing method of semiconductor device having planarized film without dishing phenomenon |
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