KR20010005007A - Memory device and method for improving word line access time - Google Patents

Abstract

SUMMARY OF THE INVENTION The present invention provides a high speed semiconductor memory device that quickly activates a word line. The present invention provides an address indicating a start of a las, cas, write enable, and chip select signal and address transfer in a semiconductor memory device. A command decoder configured to generate a word line access signal and an address access signal that is activated before the word line access signal in response to a flag signal; Means for generating an address signal as a pulse signal in response to the address access signal, predecoding it, and then latching it; Word line access control means for transferring an output signal from the means to a decoder in response to the word line access signal; And an address decoder that receives and decodes a predecoded signal through the word line access control means, decodes an address before a read or write operation is activated in response to the word line access signal, and decodes the address access signal. In response, a read or write operation is activated to activate address decoding.

Description

Memory device and method for improving word line access time

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device in which an operation speed is increased by modifying a method of activating a word line to an address applied from the outside.

As the cell density of memory devices increases rapidly with generations, the cell area increases, and as the functions for controlling cell blocks become more complicated, the size of control blocks increases rapidly, resulting in a significant increase in chip size. Doing. Because of this, the length of bus lines that carry external input signals to internal cell blocks has also increased dramatically, and delays in metal bus lines are no longer negligible. In addition, the clock speed is getting faster, and a small amount of delay and skew are also limiting the clock speed.

1 shows a block diagram of address signal transfer according to the prior art, wherein an externally applied address Ai connects an external pin and a circuit of a core block to an address pad 110; When the unstable voltage is input through the address pad 110, an electrostatic discharge protection unit 120 for preventing the unstable voltage from being transferred to the internal circuit, and the address as an internal address. An address pulse generator (address pulse generator) for transmitting an address buffer 130 for converting a signal into a decoder and an internal address (gax_ABi, gax_CDi, gax_EFi) to a decoder under the control of a wordline active signal (WAC). 140, a driving buffer 150 for amplifying an address signal, and addresses (baxAi, baxBi, baxCi, baxDi, baxEi, baxFi) via bus lines An address predecoder 160 for predecoding, a local signal driver 170 for driving the predecoded signals bax_ABi, bax_CDi, bax_EFi as an address decoder, and the transmitted signal lax_ABi Address Decoder 180 for decoding lax_CDi and lax_EFi, a Wordline Driver 190 for driving a wordline by the decoded address, and the wordline active signal WAC. Command Decoder 100 is generated.

FIG. 2 is a circuit diagram of a conventional word line active signal generator, and is connected in series between a supply power supply VCC and a ground power supply GND, and gates a RAS, a cas, and a write enable signal WE. NMOS21 (NM21, NM22, NM23) to be input as input signal and PMOS transistor (PM21) using the write enable signal as a gate, and inverter (INV21) which inverts the signal by the lath, cas, and write enable signal. It is composed of

FIG. 3 is a timing diagram of an address signal transfer process according to the prior art. Referring to FIG. 3 together with FIG. 1, after the word line active signal WAC is activated in the state where the address Ai is externally applied, FIG. When the clock is active "high", the pre-decoded address lax_EFi is transferred from the address pulse generator 140 toward the decoder to decode and activate the word line WL.

Specifically, the address signal transfer process according to the prior art will be described.

Externally applied address Ai connects the pins on the outside of the chip to the core blocks inside, and static electricity or a sudden high voltage generated in the human body is directly applied to the core block circuit through the pins on the outside. It is transmitted to the address buffer 130 via the antistatic circuit 120 to prevent destruction.

The transferred address Ai is an internal address (gax_ABi, gax_CDi, gax_EFi) by an address buffer 130 that converts an external TTL (Transistor Transistor Logic) signal into a Complementary Metal Oxide Semiconductor (CMOS) signal used in an internal circuit of a memory. ) Is applied to the address pulse generator 140. The internal addresses gax_ABi, gax_CDi, and gax_EFi applied to the address pulse generator 140 are activated by the word line active signal WAC generated by the command decoder 100 to drive a long signal bus line made of metal. The address bax_ABi, bax_CDi, bax_EFi is transferred to the bus line through the driving buffer 150 and delayed by the resistance and capacitance present in the bus line, and then predecoded by the address predecoder 160. ) Is input to the address decoder 180 as the address lax_ABi, lax_CDi, lax_EFi buffered through the local signal driver 170 in front of the address decoder 180 of the unit cell block. The signal decoded by the decoder activates the word line WL via the word line driver 190 for driving the word line to perform a read, write, or refresh operation.

The word line active signal WAC is generated at the command decoder 100 and combines the las, the cas, and the write enable as shown in FIG. 2, so that the word line when the write enable is logic " low " The active signal WAC goes logic "low" and disables the wordline pulse generator 140. When the write enable WE is logic " high " and when the RAS and CAS are logic " high ", the word line active signal WAC is " high " to activate the address pulse generator 140. Enable).

The address signal transfer process according to the related art has a limitation in starting a column access operation due to a delay time caused by a bus line and a driving buffer to access a word line. Due to the propagation delay, it has become a big factor in limiting the speed of memory devices.

SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art as described above, and an object of the present invention is to provide a semiconductor memory device capable of quickly activating a word line to implement high-speed operation.

1 is a block diagram showing an address signal transfer process of a conventional memory device.

2 is a circuit diagram of a conventional word line active signal generation unit.

3 is a timing diagram of a conventional address signal transfer operation.

4 is a block diagram showing an address signal transmission process of a memory device according to an embodiment of the present invention.

5A is a circuit diagram of an address access signal generation unit according to an embodiment of the present invention.

5B is a circuit diagram of a word line access control unit according to an embodiment of the present invention.

5C is a circuit diagram of an address decoder according to an embodiment of the present invention.

Figure 6 is a timing diagram of an address signal transfer operation in accordance with the present invention.

* Explanation of symbols for the main parts of the drawings

200: command decoder 230: address buffer

240: address pulse generator 260: address predecoder

270: pulse latch unit 280: word line access control unit

290: address decoder

WAC: Wordline Active Signal WAP: Wordline Access Signal

AAP: address access signal Af: address flag signal

In accordance with another aspect of the present invention, a semiconductor memory device includes a word line access signal and a word line access signal in response to a lath, a cas, a write enable, and an address flag signal indicating an address transfer start. A command decoder for generating an address access signal that is first activated; Means for generating an address signal as a pulse signal in response to the address access signal, predecoding it, and then latching it; Word line access control means for transferring an output signal from the means to a decoder in response to the word line access signal; And an address decoder that receives and decodes a predecoded signal through the word line access control means, decodes an address before a read or write operation is activated in response to the word line access signal, and decodes the address access signal. In response, a read or write operation is activated to activate address decoding.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

4 is an address signaling block diagram according to an embodiment of the present invention.

As shown in the drawing, an embodiment according to the present invention includes an address pad 210 for receiving an external address Ai as an input, an electrostatic discharge protection unit for connecting the pad and the address buffer ( In response to an address buffer 230 and an address access signal AAP, the internal address is converted into an internal address gax_ABi, gax_CDi, and gax_EFi. An address pulse generator 240 to be transmitted to the decoder, a driving buffer unit 250 to amplify the address signal, and an address (baxAi, baxBi, baxCi, baxDi, baxEi, baxFi) passing through the bus line Address predecoder 260 to predecode the signal, a pulse latch unit 270 to latch the predecoded signal, and a wordline access signal (WAP). A wordline access control logic 280 for controlling the latched addresses bax_ABi, bax_CDi, and bax_EFi to be input to the decoder, and an address decoder for decoding the transmitted address signals lax_ABi, lax_CDi, and lax_EFi_wap. Address Decoder 290, Wordline Driver 300 for driving the wordline, and control signal lath, cas, write enable, chip select and address flag signals (Af) in combination The command decoder 200 generates an address access signal AAP and a word line access signal WAP.

Referring to Figure 4, the address signal transfer process proposed in the present invention will be described below.

The externally applied address Ai is applied to the address pulse generator 240 via the address pad 210, the antistatic circuit 220 and the address buffer 230 through the same path and method as the conventional method described above. When another operation is performed before activating the word line, the address pulse generator 240 is activated by an address access signal (AAP) together with an external address in advance during the operation of the other operation so that the address is pre-set. It is passed to the decoder. Addresses amplified through the driving buffer 250 (baxAi, baxBi, baxCi, baxDi, baxEi, baxFi) are transferred to the long bus line to drive the circuit of the next stage, and the resistance and capacitance present in the bus line. The delay is caused by the capacitance, and is predecoded by the address predecoder 260 to be transmitted to the pulse latch unit 270.

The pulse latch unit 270 inputs a pulse to the driver in the form of a general cross coupled latch and outputs a desired value, and immediately becomes a floating state that is neither a "high" nor a "low" level, but is output. Latch the desired data value. That is, it prevents the continuous pull-on of driver pull-up and pull-down morse generated when the level signal is input, and the latch circuit of relatively smaller size than the driver stage operates. As a result, it consumes less power and does not require a separate precharge process.

Among the addresses (lax_ABi, lax_CDi, lax_EFi) buffered by the word line access control unit 280, the latches (bax_ABi, bax_CDi, bax_EFi) latched by the pulse latch unit 270 are activated by the word line access signal WAP. When the active address is input to the address decoder 290, the decoded signal is decoded to activate the word line WL through the word line driver 300.

The word line access signal WAP is made in the same manner as the word line active signal WAC described in the prior art of FIG.

The address access signal AAP is made of a combination of control signals RAS_aap, CAS_aap, WE_aap and an address flag signal (Address Flag Af) for controlling the address access signal as shown in FIG. 5A. When the address flag signal Af is logic "low", the address access signal is "low" to disable the address pulse generator, and the address flag signal Af becomes the "high" level and the control signals RAS_aap and CAS_aap When WE_aap becomes logic "high", the address access signal AAP is activated "high".

FIG. 5B is a circuit diagram of the word line access control unit 280 according to the present invention. The address line lax_EFi generated by the predecoded and latched address bax_EFi through the buffer is combined with the word line access signal WAP. The address lax_EFi_wap to be decoded is generated. When the word bax_EFi is applied at the "high" level, the word line access signal WAP becomes "high" and is activated at a logic "high" level.

FIG. 5C is an exemplary circuit diagram of an address decoder 290 according to the present invention. In the related art, only a low decoder precharge signal (Rdp) is used as a gate terminal of a PMOS transistor for precharging a word line. In the present invention, the word line is precharged to the ground voltage (GND) level when the word line access signal becomes “high” using the low decoder precharge signal and the inverted word line access signal (/ WAP). When the access signal is enabled and the precharge ends and the addresses lax_ABi, lax_CDi, and lax_EFi_wap are input at a logic "high" level, they are activated to perform decoding.

For reference, the circuit configuration shown in FIGS. 5A, 5B, and 5C is an exemplary design designed to satisfy the logic of the signal as described above, and those skilled in the art will fully understand them under the logic.

6 is a timing diagram of an address signal transfer process according to the present invention of FIG. Referring to FIG. 6, the entire operation is briefly summarized. When the clock is "high" after the address access signal AAP is activated while the address Ai is applied from the outside, the address pre-decoded from the address pulse generator toward the decoder When the latch is latched by the pulse latch unit and the word line access signal WAP is activated "high", the address lax_EFi_wap is input to the decoder and decoded to activate the word line WL.

In the case of address forwarding, it does not work in other operations. Therefore, this address is used to latch a pre-decoded address, and when the actual wordline access signal is input, the decoding starts at the address decoder. Will be compensated.

Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the present invention transfers the address to the address decoder input terminal before the start of another operation, and is activated by the word line access signal (WAP) at the start of the operation, and immediately transfers the address to the decoder to address the decoder in the address pulse generator. Reduce the delay time to Therefore, the word line can be quickly activated to obtain a high speed operation of the semiconductor memory device.

Claims (3)

In a semiconductor memory device, A command decoder for generating a word line access signal and an address access signal that is activated before the word line access signal in response to a lath, a cas, a write enable, and an address flag signal indicating an address transfer start; Means for generating an address signal as a pulse signal in response to the address access signal, predecoding it, and then latching it; Word line access control means for transferring an output signal from the means to a decoder in response to the word line access signal; And An address decoder which receives and decodes the predecoded signal through the word line access control means, And decoding an address before a read or write operation is activated in response to the word line access signal, and activated when a read or write operation is activated in response to the address access signal to activate address decoding. . The method of claim 1, The means, An address pulse generator for generating an input address as a pulse signal in response to the address access signal; An address predecoder to predecode the address signal output from the address pulse generator; And a latch unit for latching the predecoded address signal. The method of claim 2, And the decoder precharges an unselected word line in response to the word line access signal.