KR20010002286A - method for manufacturing semiconductor devices - Google Patents

Abstract

The present invention discloses a method for manufacturing a semiconductor device that improves both the short channel effect and the reverse short channel effect. According to this, an ion implantation layer for the pocket region is formed in the channel control region, and in addition, an ion implantation layer for the impurity diffusion suppression region is formed in the channel control region equal to or shallower than the ion implantation layer for the pocket region.

Accordingly, the present invention improves the short channel effect by suppressing the punch-through phenomenon of source / drain regions in a MOS transistor having a gate length of sub-quater micron size, and also improves the diffusion of impurities in the pocket region under the extended source / drain regions. By suppressing impurity accumulation on the surface of the channel, the reverse shot channel effect can be improved.

Description

Method for manufacturing semiconductor devices

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to suppress short channel effects and reverse short channel effects of a semiconductor device having a submicron gate length. A method for manufacturing a semiconductor device.

In general, as the degree of integration of semiconductor devices such as memory devices increases, the size of devices constituting the semiconductor device has been continuously reduced. At present, the gate length of the MOS transistor constituting the memory device has been reduced to the submicron size, and the junction of the source / drain regions has become shallow. However, as the gate length of the MOS transistor is reduced to the submicron size, the problem of the short channel effect, in which the threshold voltage is sharply lowered, has become increasingly serious.

In order to solve this problem, various methods have been introduced. Among them, a widely used method is to form and utilize a pocket ion implantation layer under an extended source / drain.

A method of fabricating a semiconductor device using the conventional method will be briefly described with reference to FIGS. 1 to 5. First, as shown in FIG. 1, for example, an active region of a p-type silicon substrate 10 having a first conductivity type, for example. In order to define the isolation layer, an isolation layer 11 is formed in the field region of the silicon substrate 10.

Thereafter, a sacrificial oxide film (not shown) is formed on the surface of the active region of the silicon substrate 10, and then a portion of the active region, for example, a pattern of the photoresist layer which exposes a region for the n MOS transistor and covers the other region (Not shown) is formed on the sacrificial oxide film.

A channel control region 13 for adjusting the threshold voltage of the n MOS transistor on the silicon substrate 10 in the region for the n MOS transistor by ion implantation of the second conductivity type n-type impurity using the pattern of the photoresist layer as a mask layer. ).

Then, the pattern of the photoresist film is removed and the sacrificial oxide film is removed to expose the entire surface of the active region, and then the gate oxide film 15 is grown on the surface of the active region, and a first conductive layer, for example, For example, a polysilicon layer is laminated. Thereafter, the first conductive layer is formed in a pattern of the gate electrode 17 by using a photolithography process.

Next, a gate polycrystalline silicon oxide film, which is the first insulating film 19, is formed on the surfaces of the gate electrode 17 and the gate oxide film 15 using an oxidation process, and then the first insulating film 19 is formed using a chemical vapor deposition process. ), An oxide film that is the second insulating film 21 is laminated.

As shown in FIG. 2, after the photoresist pattern 23 is formed on the resultant structure to define the pocket region of the n MOS transistor, the photoresist pattern 23 and the gate electrode 17 are formed. P-type impurities are ion-implanted using the mask layer to form a first ion implantation layer 25 in the channel control region 13 for forming pocket regions. The first ion implanted layer 25 suppresses the occurrence of punching through between the source / drain regions to be formed in a subsequent process to improve the short channel effect.

In addition, by using the pattern 23 of the photoresist film and the gate electrode 17 as a mask layer, a low concentration of ion implanted n-type impurities is used to form a second ion implanted layer 27 for an n-type extended source / drain region. .

Here, the order of the ion implantation process for forming the 1st ion implantation layer 25 and the 2nd ion implantation layer 27 may be mutually changed. Of course, the ion implantation energy, the dose, and the ion implantation inclination angle of the first ion implantation layer 25 and the second ion implantation layer 27 are different from each other.

As shown in FIG. 3, the pattern 23 of the photoresist film is then removed, and then a third insulating film is deposited on the resulting structure, and the surface of the second insulating film 21 on the gate electrode 17 is exposed. The spacers 29 are formed on both sidewalls of the gate electrode 17 by being etched back until they reach the end.

As shown in FIG. 4, a pattern 31 of a photoresist film for n + source / drain regions is then formed on the resulting structure, and the pattern 31 of the photoresist film, the gate electrode 17 and the spacer 29 are masked. A high concentration of ion implanted n-type impurities is used as a layer to form a third ion implanted layer 33 for the n + type deep source / drain region.

As shown in FIG. 5, the source / drain regions 35 of the LDD structure are formed by activating impurities in the second and third ion implantation layers 27 and 33 using a heat treatment process. Therefore, in the MOS transistor having a gate length of submicron size, the punch-through phenomenon of the source / drain regions is suppressed by the first ion implantation layer for forming the pocket region, so that the short channel effect is significantly improved.

However, in the case of the MOS transistor whose gate length is reduced to submicron, the first ion implantation for forming the pocket region causes an inverse short channel effect in which the threshold voltage is increased. In view of the cause of the reverse shot channel effect, the damage of the silicon substrate generated during the second and third ion implantation for the formation of the extended source / drain region and the deep source / drain region may be caused by subsequent heat treatment for diffusion of the source / drain region. It causes a large amount of silicon self interstitial defects in the source / drain regions. The silicon magnetic interstitial defects diffuse with a diffusion flux (shown by arrow) of the silicon magnetic interstitial defects, as shown in FIG. As a result, impurities under the extended source / drain, which are ion-implanted at the time of first ion implantation, are continuously diffused, and impurities in the pocket region under the extended source / drain are depleted. Thus, as shown in Fig. 5, an impurity accumulation region 37 in which p-type impurities are accumulated is formed on the channel surface of the transistor. That is, the impurity concentration according to the depth from the surface of the silicon substrate under the gate electrode is highest at the depth D1 near the channel surface of the transistor as shown in FIG. This phenomenon is called transient enhanced diffusion (TED).

Currently, the inverse short channel effect caused by the TED phenomenon is gradually worsened as the gate length is reduced to the sub-quarter micron, and various methods for solving this problem are urgently needed.

Accordingly, it is an object of the present invention to provide a method for manufacturing a semiconductor device which suppresses the short channel effect while also suppressing the reverse short channel effect.

1 is a cross-sectional structural view showing a semiconductor device according to the prior art.

2 to 5 are cross-sectional process diagrams showing a method of manufacturing a semiconductor device according to the prior art.

FIG. 6 is a view showing silicon self interstitial flux generated in a method of manufacturing a semiconductor device according to the prior art. FIG.

7 is an impurity concentration graph showing impurity accumulation generated in the method of manufacturing a semiconductor device according to the prior art.

8 is a cross-sectional structural view showing a semiconductor device according to the present invention.

9 to 11 are cross-sectional process diagrams illustrating a method for manufacturing a semiconductor device according to the present invention.

12 is a view showing a silicon magnetic interstitial defect flux generated in the method of manufacturing a semiconductor device according to the present invention.

13 is an impurity concentration graph showing a state in which impurities are not accumulated on the substrate surface of the semiconductor device according to the present invention.

The semiconductor device manufacturing method for achieving the above object is

Selectively forming a gate electrode on the gate oxide film of the active region of the first conductivity type silicon substrate;

Forming a first ion implantation layer for channel control, a second ion implantation layer and a third ion implantation layer for the extended source / drain regions, respectively, in the active region defined by the gate electrode;

Forming a fourth ion implantation layer for a high concentration source / drain region in an active region defined by a spacer on the sidewall of the gate electrode; And

A diffusion inhibiting region for activating the second and fourth ion implantation layers to form a source / drain region of a second conductivity type LDD structure and to activate the third ion implantation layer to suppress impurity accumulation on the surface of the channel region. It characterized in that it comprises a step of forming.

Preferably, the third ion implantation layer is formed to be shallower than the first ion implantation layer.

In addition, any one of silicon (Si), argon (Ar), nitrogen (N), germanium (Ge), and indium (In) is implanted as impurities of the third ion implantation layer.

Hereinafter, a semiconductor device and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings. The same code | symbol is attached | subjected to the part same as a conventional part.

8 is a cross-sectional structural view showing a semiconductor device according to the present invention.

As shown in FIG. 8, in the semiconductor device of the present invention, an isolation layer 11 is formed in a field region to define an active region of the silicon substrate 10, and a gate oxide film 15 is formed on the active region. The gate electrode 17 is formed on a portion of the gate oxide film 15, the source / drain region 35 of the LDD structure is formed in the active region and is spaced apart from each other with the gate electrode 17 interposed therebetween. Spacers 29 are formed on the sidewalls of 17. Further, a diffusion suppression layer 47 is formed in the channel control region 13 between the source / drain regions 35 so as to suppress the diffusion of impurities in the pocket region under the n-source / drain region.

Therefore, in the semiconductor device of the present invention, the diffusion suppression layer 47 is formed during the heat treatment for the diffusion of the source / drain regions 35, which suppresses the diffusion of impurities on the surface of the channel region and suppresses the formation of the impurity accumulation region. The reverse channel effect can be improved. In addition, impurities in the pocket region under the n-source / drain region improve the short channel effect.

A method of manufacturing a semiconductor device configured as described above will be described with reference to FIGS.

As shown in FIG. 9, first, the processes of FIGS. 1 and 2 are performed in the same manner. That is, for example, the isolation layer 11 is formed in the field region of the silicon substrate 10 to define the active region of the p-type silicon substrate 10 of the first conductivity type.

Thereafter, a sacrificial oxide film (not shown) is formed on the surface of the active region of the silicon substrate 10, and then a portion of the active region, for example, a pattern of the photoresist layer which exposes a region for the n MOS transistor and covers the other region (Not shown) is formed on the sacrificial oxide film.

A channel control region for controlling the threshold voltage of the n MOS transistor on the silicon substrate 10 in the region for the n MOS transistor by ion implantation of the second conductivity type n-type impurity using the pattern of the photoresist layer as a mask layer. (13) is formed.

Then, the pattern of the photoresist film is removed and the sacrificial oxide film is removed to expose the entire surface of the active region, and then the gate oxide film 15 is grown on the surface of the active region, and a first conductive layer, for example, For example, a polysilicon layer is laminated. Thereafter, the first conductive layer is formed in a pattern of the gate electrode 17 by using a photolithography process.

Next, a gate polycrystalline silicon oxide film, which is the first insulating film 19, is formed on the surfaces of the gate electrode 17 and the gate oxide film 15 using an oxidation process, and then the first insulating film 19 is formed using a chemical vapor deposition process. ), An oxide film that is the second insulating film 21 is laminated.

Subsequently, a photoresist pattern 23 is formed on the resultant structure to define the pocket region of the n MOS transistor using a photographic process, and then the photoresist pattern 23 and the gate electrode 17 are used as a mask layer. P-type impurities are implanted to form a first ion implantation layer 25 in the channel control region 13 for forming pocket regions. The first ion implantation layer 25 can improve the short channel effect by suppressing the occurrence of punch-through through the source / drain regions to be formed in a subsequent process.

In addition, by using the pattern 23 of the photoresist film and the gate electrode 17 as a mask layer, a low concentration of ion implanted n-type impurities is used to form a second ion implanted layer 27 for an n-type extended source / drain region. .

Here, the order of the ion implantation process for forming the 1st ion implantation layer 25 and the 2nd ion implantation layer 27 may be mutually changed. Of course, the ion implantation energy, the dose, and the ion implantation inclination angles of the first ion implantation layer 25 and the second ion implantation layer 27 are different from each other.

As shown in FIG. 10, the pattern 23 of the photoresist film is then removed, and then the pattern 41 of the photoresist film for defining the impurity diffusion suppressing region is formed on the resulting structure, and the gate electrode 17 and the photoresist film are formed. Using the pattern 41 as a mask layer, any of impurities such as silicon (Si), argon (Ar), nitrogen (N), germanium (Ge), or indium (In) for ion channeling The fourth ion implantation layer 43 is formed in the channel control region 13 by implantation. The fourth ion implantation layer 43 forms the diffusion suppression layer 47 of FIG. 8 due to the unchanneling effect, thereby suppressing the occurrence of the TED phenomenon by the ion implantation and heat treatment processes of the subsequent n + type source / drain regions. The effect can be improved.

Here, the fourth ion implantation layer 43 is equal to the projection range Rp of the first ion implantation layer 25, or 100-200 Å shallower than the projection range Rp of the first ion implantation layer 25. It is preferably formed in the region 13.

As shown in FIG. 11, the pattern 41 of the photoresist film is then removed, and a third insulating film is stacked on the resulting structure, and the surface of the second insulating film 21 over the gate electrode 17 is exposed. It is etched back until a spacer 29 is formed on both sidewalls of the gate electrode 17.

Thereafter, a pattern 45 of a photoresist film for n + source / drain regions is formed on the resultant structure, and an n-type impurity is formed using the gate electrode 17, the spacer 29, and the pattern 45 of the photoresist film as a mask layer. Ion implantation at a high concentration forms an ion implantation layer 33 for the n + type source / drain region.

Thereafter, as shown in FIG. 8, the source / drain region 35 of the LDD structure is diffused by activating impurities in the ion implanted layers 27 and 33 implanted using the heat treatment process and n− A diffusion suppression region 47 is also formed between the n + type source / drain regions located below the type source / drain regions.

At this time, as already mentioned, a large amount of silicon magnetic interstitial defects are generated in the ion implantation layers 27 and 33, and as shown in FIG. 12, it diffuses with a diffusion flux (shown by an arrow). Since the diffusion inhibiting region 47 is present, impurities in the pocket region under the ion implantation layer 27 do not increase and diffuse, and impurities in the pocket region under the n-type source / drain region are not exhausted. As a result, unlike in the prior art, a considerable amount of impurities in the pocket region do not accumulate on the channel surface. That is, the impurity concentration according to the depth from the surface of the silicon substrate under the gate electrode does not appear the highest at the depth near the channel surface of the transistor as shown in FIG.

As described above, the present invention forms an ion implantation layer for the pocket region in the channel control region, and in addition, the ion implantation layer for the impurity diffusion suppression region is equal to or shallower than the ion implantation layer for the pocket region. To form.

Accordingly, the present invention improves the short channel effect by suppressing the punch-through phenomenon of source / drain regions in a MOS transistor having a gate length of sub-quater micron size, and also improves the diffusion of impurities in the pocket region under the extended source / drain regions. By suppressing impurity accumulation on the surface of the channel, the reverse shot channel effect can be improved.

On the other hand, the present invention is described based on the preferred example shown in the drawings, but not limited to this and various modifications and improvements are possible by those skilled in the art to which the present invention belongs without departing from the spirit of the invention. Of course.

Claims (3)

Selectively forming a gate electrode on the gate oxide film of the active region of the first conductivity type silicon substrate; Forming a first ion implantation layer for channel control, a second ion implantation layer and a third ion implantation layer for the extended source / drain regions, respectively, in the active region defined by the gate electrode; Forming a fourth ion implantation layer for a high concentration source / drain region in an active region defined by a spacer on the sidewall of the gate electrode; And A diffusion inhibiting region for activating the second and fourth ion implantation layers to form a source / drain region of a second conductivity type LDD structure and to activate the third ion implantation layer to suppress impurity accumulation on the surface of the channel region. Method of manufacturing a semiconductor device comprising the step of forming a. 5. The method of claim 4, wherein the third ion implantation layer is formed to be shallower than the first ion implantation layer. The method of claim 4, wherein any one of silicon (Si), argon (Ar), nitrogen (N), germanium (Ge), and indium (In) is ion-implanted as impurities of the third ion implantation layer. Method of manufacturing a semiconductor device.