KR20000075305A - method for forming trench type isolation layer using polishing sacrificial layer - Google Patents
method for forming trench type isolation layer using polishing sacrificial layer Download PDFInfo
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- KR20000075305A KR20000075305A KR1019990019826A KR19990019826A KR20000075305A KR 20000075305 A KR20000075305 A KR 20000075305A KR 1019990019826 A KR1019990019826 A KR 1019990019826A KR 19990019826 A KR19990019826 A KR 19990019826A KR 20000075305 A KR20000075305 A KR 20000075305A
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- 238000005498 polishing Methods 0.000 title claims abstract description 93
- 238000000034 method Methods 0.000 title claims abstract description 51
- 238000002955 isolation Methods 0.000 title claims abstract description 18
- 239000002002 slurry Substances 0.000 claims abstract description 24
- 239000004065 semiconductor Substances 0.000 claims abstract description 14
- CETPSERCERDGAM-UHFFFAOYSA-N ceric oxide Chemical compound O=[Ce]=O CETPSERCERDGAM-UHFFFAOYSA-N 0.000 claims abstract description 7
- 229910000422 cerium(IV) oxide Inorganic materials 0.000 claims abstract description 7
- 238000004519 manufacturing process Methods 0.000 claims abstract description 6
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 230000003064 anti-oxidating effect Effects 0.000 claims description 2
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 239000011521 glass Substances 0.000 claims 1
- 230000008021 deposition Effects 0.000 abstract description 3
- 238000005516 engineering process Methods 0.000 abstract description 3
- 238000000926 separation method Methods 0.000 abstract description 2
- 150000004767 nitrides Chemical class 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 241000293849 Cordylanthus Species 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000010790 dilution Methods 0.000 description 1
- 239000012895 dilution Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
본 발명은 반도체 제조 기술에 관한 것으로, 특히 소자간의 전기적 분리를 위한 소자분리 공정에 관한 것이며, 더 자세히는 트렌치형 소자분리막 형성방법에 관한 것이다. 본 발명은 STI 공정 중 산화막의 CMP에서 고연마선택비 슬러리 사용시 산화막 증착 후 형성된 단차에 의해 발생하는 연마속도가 현저히 떨어지거나, 연마선택비가 저하되는 현상을 완화시킬 수 있는 반도체 소자의 트렌치 소자분리막 형성방법을 제공하는데 그 목적이 있다. 본 발명은 STI 공정시 산화막의 평탄화를 위해 실시되는 CMP 공정에서 사용되는 고연마선택비 슬러리(예컨대, 세리아) 자체에 기인하는 연마 거동 특성상 한번에 연마가 이루어지지 않는 점을 개선하기 위해서 산화막으로 트렌치를 매립한 후 초기에 형성된 단차를 최소로 하기 위해 연마 희생막을 산화막 상부에 증착하고 하나의 레시피(recipe)에 2가지 연마 조건을 세팅(setting)하여 원스텝(one-step) 연마를 실시한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a device isolation process for electrical separation between devices, and more particularly, to a method of forming a trench type device isolation film. The present invention provides a trench isolation layer for a semiconductor device that can alleviate the phenomenon that the polishing rate caused by the step formed after the deposition of the oxide film is significantly reduced or the polishing selectivity is reduced when the high polishing selectivity slurry is used in the CMP of the oxide film during the STI process. The purpose is to provide a method. The present invention provides a trench with an oxide film to improve the fact that polishing is not performed at one time due to the polishing behavior due to the high polishing selectivity slurry (eg, ceria) itself used in the CMP process to planarize the oxide film during the STI process. In order to minimize the initial step formed after the filling, the polishing sacrificial film is deposited on the oxide film, and one polishing is performed by setting two polishing conditions in one recipe.
Description
본 발명은 반도체 제조 기술에 관한 것으로, 특히 소자간의 전기적 분리를 위한 소자분리 공정에 관한 것이며, 더 자세히는 트렌치형 소자분리막 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a device isolation process for electrical separation between devices, and more particularly, to a method of forming a trench type device isolation film.
트렌치 소자분리(shallow trench isolation, STI) 공정은 반도체 소자의 디자인 룰(design rule)의 감소에 따른 필드 산화막의 열화와 같은 공정의 불안정 요인과, 버즈비크(bird's beak)에 따른 활성 영역의 감소와 같은 문제점을 근본적으로 해결할 수 있는 소자분리 공정으로 부각되고 있으며, 1G DRAM급 이상의 초고집적 반도체 소자 제조 공정에의 적용이 유망한 기술이다.The trench trench isolation (STI) process is a process instability factor such as deterioration of the field oxide film due to the reduction of design rules of the semiconductor device, and the reduction of the active area due to the bird's beak. It is emerging as a device isolation process that can fundamentally solve the same problem, and it is a promising technology to be applied to an ultra-high density semiconductor device manufacturing process of 1G DRAM or higher.
STI 공정은 통상적으로 패드 산화막 및 질화막(silicon nitride)을 사용한 소자분리 마스크 패턴을 사용하여 식각하여 실리콘 기판에 트렌치를 형성하고, 산화막으로 트렌치를 매립한 다음 화학·기계적 평탄화(Chemical Mechanical Planarization, CMP) 공정을 이용하여 초과 증착된 산화막을 일정 부분 연마하는 공정을 실시하게 된다.The STI process is typically etched using a device isolation mask pattern using a pad oxide and a silicon nitride to form trenches in the silicon substrate, fill the trench with oxide and then chemical mechanical planarization (CMP). By using the process, a process of partially polishing the deposited oxide film is performed.
산화막의 CMP 공정시 통상적으로 세리아계 슬러리(CeO2based slurry)를 사용하고 있다. 세리아계 슬러리는 질화막에 대한 산화막의 연마비가 높아서 공정 마진이 크다는 장점이 있는 반면, 산화막 증착 후 형성된 단차에 의해서 연마 속도가 현저히 떨어지는 문제점이 있으며, 연마 속도를 증가시키기 위하여 연마 압력을 높여 연마할 경우에도 초기에는 연마속도가 느리다가 갑자기 빨라지는 현상과 함께 연마선택비가 급격히 떨어져 고연마선택비의 장점이 감소되는 문제점이 있었다.When the CMP process of the oxide film is typically used for ceria-based slurry (CeO 2 based slurry). Ceria-based slurry has the advantage that the process margin is high due to the high polishing ratio of the oxide film to the nitride film, while the polishing rate is significantly reduced by the step formed after the oxide film deposition, when polishing to increase the polishing pressure to increase the polishing rate Even in the early stages, the polishing rate was slow and suddenly accelerated, and the polishing selection ratio was sharply dropped, thereby reducing the advantages of the high polishing selection ratio.
즉, 세리아계 슬러리의 경우 슬러리 특성상 패턴이 형성되고 단차가 존재할 경우, 일정 시간 동안 연마가 이루어지지 않다가 임계점을 지나게 되면 갑자기 연마속도가 증가하는 특성을 가지고 있다. 또한, 연마 조건에 따라 질화막에 대한 산화막의 연마선택비의 변화가 큰 특성을 가지고 있다.That is, in the case of the ceria-based slurry, when the pattern is formed due to the characteristics of the slurry and there is a step, the polishing rate is suddenly increased after passing through the critical point without polishing for a predetermined time. In addition, the polishing selectivity of the oxide film with respect to the nitride film is large depending on the polishing conditions.
STI 공정시 트렌치를 산화막으로 매립하는 과정에서 트렌치 깊이만큼의 단차가 발생하게 되고, 이를 연마 압력이 높은 조건으로 연마하게 되면 초기에 연마가 안되다가 단차가 일정한 값 이하로 감소되면서 갑자기 빨라지게 되는 현상이 발생하게 되는데, 특히 초기 단차가 낮고 연마속도가 빠른 지역의 경우는 연마속도가 느린 지역 상부의 산화막이 완전히 연마되는 동안 연마 정지막으로 사용된 질화막이 기계적인 힘에 의해서 연마가 되어 연마 도중 활성영역이 손상(damage)을 입게 되고, 슬러리에 노출되어 웰(well) 형성이 불완전하거나 누설전류(leakage current) 발생의 원인이 된다. 또한, 연마압력이 낮을 경우 임계점에 도달하는 시간이 길어지게 되어 생산성(throughput) 측면에서 불리한 결과를 얻게 된다.In the process of filling the trench with the oxide film during the STI process, a step as much as the trench depth is generated, and when the polishing is performed under a high polishing pressure, the step is not polished at the beginning but suddenly accelerated as the step is reduced below a certain value. Especially, in the case where the initial step is low and the polishing speed is high, the nitride film used as the polishing stop film is polished by mechanical force while the oxide film on the upper polishing area is completely polished. Areas are damaged and exposed to the slurry, resulting in incomplete well formation or leakage currents. In addition, when the polishing pressure is low, the time to reach the critical point is long, which results in disadvantageous results in terms of productivity.
이러한 문제점을 개선하기 위해 다단계 연마 공정이 사용되고 있는데, 다단계 연마 공정은 산화막 연마용 슬러리를 사용하여 1차 연마를 실시함으로써 초기에 형성된 단차를 제거하고, 1차 연마후 활성영역 상부의 남아 있는 산화막의 두께를 측정한 다음 2차 연마시에는 선택비가 높은 슬러리를 사용하여 연마하는 번거로운 공정을 거쳐야 한다. 또한, 산화막 연마용 슬러리와 선택비가 높은 슬러리를 같은 연마 패드 내에서 교차 사용하게 되고, 고 연마선택비 사용시 선택비를 떨어뜨리는 인자들이 첨가되기도 하기 때문에 항상 2차 연마시 연마 패드에 특별한 처리를 해야 하는 번거로움이 발생하게 된다. 이에 따라 공정 진행시 안정성의 문제가 발생하게 되고, 수율을 떨어뜨리게 되는 문제가 발생하게 된다. 물론 1차 연마용, 2차 연마용으로 구분하여 장비를 운용하게 되면 이러한 문제점을 극복할 수 있으나, 이는 생산 단가 측면에서 매우 불리한 단점이 있다.In order to solve this problem, a multi-step polishing process is used. The multi-step polishing process removes the step formed initially by performing primary polishing using an oxide film polishing slurry, and removes the remaining oxide film on the active region after the primary polishing. After measuring the thickness, secondary polishing requires a cumbersome process of polishing with a high selectivity slurry. In addition, an oxide polishing slurry and a high selectivity slurry are used in the same polishing pad, and when using a high polishing selectivity, special factors are applied to the polishing pad at the time of secondary polishing. The hassle will occur. As a result, a problem of stability occurs during the process, and a problem of lowering the yield occurs. Of course, if you operate the equipment divided into primary polishing, secondary polishing for this problem can be overcome, but this has a very disadvantageous disadvantage in terms of production cost.
본 발명은 STI 공정 중 산화막의 CMP에서 고연마선택비 슬러리 사용시 산화막 증착 후 형성된 단차에 의해 발생하는 연마속도가 현저히 떨어지거나, 연마선택비가 저하되는 현상을 완화시킬 수 있는 반도체 소자의 트렌치 소자분리막 형성방법을 제공하는데 그 목적이 있다.The present invention provides a trench isolation layer for a semiconductor device that can alleviate the phenomenon that the polishing rate caused by the step formed after the deposition of the oxide film is significantly reduced or the polishing selectivity is reduced when the high polishing selectivity slurry is used in the CMP of the oxide film during the STI process. The purpose is to provide a method.
도 1은 본 발명의 일 실시예에 따른 STI 공정 중 CMP 공정 전의 단면도.1 is a cross-sectional view before the CMP process of the STI process according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
10 : 실리콘 기판 11 : 패드 산화막10 silicon substrate 11 pad oxide film
12 : 질화막 13 : 산화막12 nitride film 13 oxide film
14 : BPSG막14: BPSG film
본 발명은 STI 공정시 산화막의 평탄화를 위해 실시되는 CMP 공정에서 사용되는 고연마선택비 슬러리(예컨대, 세리아) 자체에 기인하는 연마 거동 특성상 한번에 연마가 이루어지지 않는 점을 개선하기 위해서 산화막으로 트렌치를 매립한 후 초기에 형성된 단차를 최소로 하기 위해 연마 희생막을 산화막 상부에 증착하고 하나의 레시피(recipe)에 2가지 연마 조건을 세팅(setting)하여 원스텝(one-step) 연마를 실시한다.The present invention provides a trench with an oxide film to improve the fact that polishing is not performed at one time due to the polishing behavior due to the high polishing selectivity slurry (eg, ceria) itself used in the CMP process to planarize the oxide film during the STI process. In order to minimize the initial step formed after the filling, the polishing sacrificial film is deposited on the oxide film, and one polishing is performed by setting two polishing conditions in one recipe.
상기의 기술적 과제를 해결하기 위한 본 발명의 특징적인 반도체 소자의 트렌치형 소자분리막 형성방법은, 반도체 기판 상의 활성영역에 오버랩되는 산화방지 및 연마정지 패턴을 형성하는 제1 단계; 상기 제1 단계 수행 후, 노출된 상기 실리콘 기판을 식각하여 트렌치를 형성하는 제2 단계; 상기 제2 단계 수행 후, 전체구조 상부에 트렌치 매립용 산화막을 형성하는 제3 단계; 상기 트렌치 매립용 산화막 상에 상기 제3 단계에서 발생한 단차를 감소시키기 위한 연마희생산화막을 형성하는 제4 단계; 및 고연마선택비 슬러리를 사용하여 상기 연마희생산화막 및 상기 트렌치 매립용 산화막을 화학·기계적으로 연마하여 평탄화를 이루는 제5 단계를 포함하여 이루어진다.In order to solve the above technical problem, a method of forming a trench type isolation layer for a semiconductor device according to the present invention includes: a first step of forming an anti-oxidation and polishing stop pattern overlapping an active region on a semiconductor substrate; A second step of forming a trench by etching the exposed silicon substrate after performing the first step; A third step of forming an oxide film for trench filling in an upper portion of the entire structure after performing the second step; Forming a polishing sacrificial film for reducing the step difference generated in the third step on the trench buried oxide film; And a fifth step of chemically and mechanically polishing the polishing dilution film and the trench filling oxide film using a high polishing selectivity slurry to planarize.
이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.
첨부된 도면 도 1은 본 발명의 일 실시예에 따른 STI 공정 중 CMP 공정 전의 단면을 도시한 것으로, 이하 이를 참조하여 설명한다.1 is a cross-sectional view of the SMP process before the CMP process according to an embodiment of the present invention, will be described below with reference to this.
본 실시예에 따른 STI 공정은, 먼저 실리콘 기판(10) 상에 패드 산화막(11)을 10∼100Å 두께로 성장시키고, 그 상부에 확산방지 및 연마정지막으로 사용될 질화막(12)을 100∼3000Å 두께로 증착한다.In the STI process according to the present embodiment, the pad oxide film 11 is first grown to a thickness of 10 to 100 GPa on the silicon substrate 10, and the nitride film 12 to be used as a diffusion preventing and polishing stop film is formed on the silicon substrate 10 to be 100 to 3000 GPa. Deposit to thickness.
이어서, 사진 및 식각 공정을 통해 패드 산화막(11) 및 질화막(12)으로 구성된 소자분리 마스크 패턴을 형성하고, 노출된 실리콘 기판(10)을 식각하여 2000∼5000Å 깊이의 트렌치를 형성한다.Subsequently, a device isolation mask pattern including the pad oxide layer 11 and the nitride layer 12 is formed through a photolithography and an etching process, and the exposed silicon substrate 10 is etched to form trenches having a depth of 2000 to 5000 占 퐉.
계속하여, 갭필링(gap-filling) 특성이 뛰어난 고밀도플라즈마 화학기상증착(HDP CVD) 방식의 산화막(13)을 전체구조 상부에 4000∼10000Å 두께로 증착하여 트렌치를 매립한다.Subsequently, an oxide film 13 having a high density plasma chemical vapor deposition (HDP CVD) method having excellent gap-filling characteristics is deposited at a thickness of 4000 to 10000 GPa over the entire structure to fill the trench.
다음으로, 산화막(13) 증착 후 발생하는 단차를 최소화하기 위해서 산화막(13)과 비슷한 연마속도를 갖는 BPSG(borophosphosilicate glass)막(14)을 전체구조 상부에 1000∼5000Å 두께로 증착하고, 300∼1200℃ 온도로 10분∼2시간 정도 플로우(flow) 시킨다. 이때, BPSG막(14)은 연마 희생막으로 증착된 것으로, 막 내의 보론(boron) 및 포스포러스(phosphorus)의 농도를 20wt% 이하로 도핑(doping)하는 것이 바람직하다.Next, a BPSG (borophosphosilicate glass) film 14 having a polishing rate similar to that of the oxide film 13 is deposited to a thickness of 1000 to 5000 kPa over the entire structure in order to minimize the step that occurs after the oxide film 13 is deposited. It is made to flow at 1200 degreeC temperature for about 10 minutes-about 2 hours. In this case, the BPSG film 14 is deposited as a polishing sacrificial film, and it is preferable to dope a concentration of boron and phosphorus in the film to 20 wt% or less.
이후, 실리카(SiO2), 세리아(CeO2), 알루미나(Al2O3) 등의 연마제를 포함하는 CeO2계 슬러리를 사용하여 CMP를 실시하고, 후속 공정을 통상적인 방법으로 진행하여 필드 산화막 형성을 완료한다. 이때, 슬러리의 연마제 농도를 1∼30wt%의 범위로 하며, 슬러리의 연마제 용액의 pH가 2∼13의 범위로 하는 것이 바람직하다.Thereafter, CMP is performed using a CeO 2 -based slurry containing an abrasive such as silica (SiO 2), ceria (CeO 2), alumina (Al 2 O 3), and the subsequent process is performed in a conventional manner to complete the field oxide film formation. At this time, it is preferable that the slurry concentration of the slurry is in the range of 1 to 30 wt%, and the pH of the slurry solution of the slurry is in the range of 2 to 13.
특히, CMP 공정시 연마 레시피(recipe) 내에 두 가지 공정 조건을 세팅하여 연마하게 되는데, 먼저 초기에는 연마압력이 높고 균일도가 좋은 조건으로 연마 희생막으로 사용된 BPSG막(14)과 그 하부의 산화막(13)의 일부를 연마하고, 연마 압력과 연마 패드의 속도가 완전히 램프다운(ramp down)시킨 다음, 연마선택비가 높은 낮은 연마 압력 조건으로 나머지 산화막(13)을 연마한다. 만일 연마 테이블이 2개 이상인 장비인 경우에는 상기의 초기 연마 및 최종 연마를 각각 다른 테이블에서 진행한다. 즉, 첫 번째 연마 테이블에서는 연마속도가 큰 높은 연마 압력 조건을 사용하고, 2번째 연마테이블에서는 연마선택비가 높도록 연마 압력이 낮고 테이블 속도가 적당히 빠른 조건으로 연마를 진행한다.In particular, in the CMP process, polishing is performed by setting two process conditions in the polishing recipe. First, the BPSG film 14 used as the polishing sacrificial film under high polishing pressure and good uniformity, and an oxide film under the same are prepared. A part of (13) is polished, the polishing pressure and the speed of the polishing pad are fully ramped down, and then the remaining oxide film 13 is polished under low polishing pressure conditions with a high polishing selectivity. If there are two or more polishing tables, the initial polishing and the final polishing are performed in different tables. That is, the first polishing table uses a high polishing pressure condition with a high polishing rate, and the second polishing table performs polishing under a low polishing pressure and a moderately high table speed so that the polishing selectivity is high.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
예컨대, 전술한 실시예에서는 연마희생막으로 BPSG막을 사용하는 경우를 일례로 들어 설명하였으나, 본 발명은 SOG막과 같이 단차피복성이 우수한 산화막으로 연마희생막을 형성하는 경우에도 적용할 수 있다. 이때, SOG막은 코팅 후, 80∼500℃의 온도에서 1분∼10분 동안 베이킹(baking)하고, 200∼600℃의 온도에서 30분∼2시간 동안 큐어링(curing)하는 공정을 거치는 것이 바람직하다.For example, in the above-described embodiment, the case where the BPSG film is used as the polishing sacrificial film has been described as an example. However, the present invention can be applied to the case where the polishing sacrificial film is formed of an oxide film having excellent step coverage like the SOG film. At this time, it is preferable that the SOG film is subjected to a process of baking at a temperature of 80 to 500 ° C. for 1 minute to 10 minutes and curing at a temperature of 200 to 600 ° C. for 30 minutes to 2 hours. Do.
전술한 본 발명은 STI 공정 중 행해지는 CMP 공정시 소자 분리막 형성시 연마속도가 현저히 떨어지거나, 연마선택비가 저하되는 현상을 완화시키면서 원스텝 연마를 통해 평탄화를 이룰 수 있어 생산성을 향상시키는 효과가 있다. 또한, 본 발명은 고선택비 슬러리에 의한 장점을 최대로 끌어올림으로써 연마 특성상 발생하는 연마 불균일도, 평탄도를 개선하고, 안정적인 공정을 진행할 수 있어 수율 향상을 기대할 수 있다.The present invention described above has the effect of improving the productivity by one-step polishing while alleviating the phenomenon that the polishing rate is significantly reduced or the polishing selectivity is reduced when forming the device isolation layer during the CMP process performed during the STI process. In addition, the present invention can be expected to improve the yield by increasing the advantages of the high selectivity slurry to the maximum to improve the polishing non-uniformity, flatness and stable process that occurs due to the polishing characteristics.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100576424B1 (en) * | 2004-06-22 | 2006-05-08 | 동부일렉트로닉스 주식회사 | Trench Formation Method for Semiconductor Devices |
| US10622364B2 (en) | 2015-05-13 | 2020-04-14 | Samsung Electronics Co., Ltd. | Method of fabricating semiconductor device |
| US10748906B2 (en) | 2015-05-13 | 2020-08-18 | Samsung Electronics Co., Ltd. | Semiconductor device and method of fabricating the same |
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1999
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100576424B1 (en) * | 2004-06-22 | 2006-05-08 | 동부일렉트로닉스 주식회사 | Trench Formation Method for Semiconductor Devices |
| US10622364B2 (en) | 2015-05-13 | 2020-04-14 | Samsung Electronics Co., Ltd. | Method of fabricating semiconductor device |
| US10748906B2 (en) | 2015-05-13 | 2020-08-18 | Samsung Electronics Co., Ltd. | Semiconductor device and method of fabricating the same |
| US10756092B2 (en) | 2015-05-13 | 2020-08-25 | Samsung Electronics Co., Ltd. | Method of fabricating semiconductor device |
| US10777560B2 (en) | 2015-05-13 | 2020-09-15 | Samsung Electronics Co., Ltd. | Semiconductor device and method of fabricating the same |
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