KR20000063735A - Highly concentrated pad - Google Patents
Highly concentrated pad Download PDFInfo
- Publication number
- KR20000063735A KR20000063735A KR1020000044682A KR20000044682A KR20000063735A KR 20000063735 A KR20000063735 A KR 20000063735A KR 1020000044682 A KR1020000044682 A KR 1020000044682A KR 20000044682 A KR20000044682 A KR 20000044682A KR 20000063735 A KR20000063735 A KR 20000063735A
- Authority
- KR
- South Korea
- Prior art keywords
- pad
- pads
- wire
- heights
- integration degree
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000010292 electrical insulation Methods 0.000 claims abstract description 4
- 239000004065 semiconductor Substances 0.000 claims abstract description 3
- 238000000034 method Methods 0.000 claims 2
- 230000010354 integration Effects 0.000 abstract 3
- 230000001105 regulatory effect Effects 0.000 abstract 1
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0613—Square or rectangular array
- H01L2224/06131—Square or rectangular array being uniform, i.e. having a uniform pitch across the array
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
- H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
- H01L2224/10125—Reinforcing structures
- H01L2224/10126—Bump collar
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
첨부도면 도 1a 내지 도 1b를 참조하여 종래 기술에 의한 패드구성 및 상기 패드에 와이어를 본딩한 상태를 설명한다.1A to 1B, a pad structure according to the related art and a state in which wires are bonded to the pad will be described.
패드(11)란 주 기판(12) 위에 내부 회로(13)의 말단 등을 넓게 형성시켜 와이어(14) 등이 부착되기 용이하게 한 부분을 지칭하는 것으로서, 반도체 집적회로 장치 또는 여러 가지 회로기판 등에 다양한 용도로 사용된다. 상기 패드(11)에 미세 와이어(14)의 일단(15)을 녹여 부착시키고, 상기 와이어의 또 다른 일단(도시 않음)은 상기 패드와 전기적으로 도통되어야 할 외부의 기판 등의 회로 내지는 패드(도시 않음)에 본딩시키므로써 내부 회로와 외부 회로간에 전기적 도통이 이루어 지게된다.The pad 11 refers to a portion where a terminal or the like of the internal circuit 13 is widely formed on the main substrate 12 so that the wire 14 or the like is easily attached thereto. The pad 11 is a semiconductor integrated circuit device or various circuit boards. Used for various purposes. One end 15 of the fine wire 14 is melted and attached to the pad 11, and another end of the wire (not shown) may be a circuit or pad (such as an external substrate) to be electrically connected to the pad. By bonding to each other, electrical connection is established between the internal and external circuits.
종래 방법의 패드(11)들은 일렬로 배치되어 있으며, 상기한 방법으로 와이어 본딩(15)이 이루어 질 때 와이어의 본딩 사이즈의 제약으로 인해서 패드 부의 크기는 일정한 크기 이상이 요구되며, 이 때문에 밀집 도를 충분히 높일 수가 없게되는 문제점이 있다.The pads 11 of the conventional method are arranged in a line, and when the wire bonding 15 is made in the above-described manner, the size of the pad portion is required to be a certain size or more due to the limitation of the bonding size of the wire, and thus the density There is a problem that can not be raised sufficiently.
본 발명은 상기한 문제점을 해소하기 위해 안출된 것으로서, 와이어 본딩 사이즈를 더 이상 줄이지 않고도 패드의 밀집 도를 높이고자 함을 목적으로 하고 있다.The present invention has been made to solve the above problems, and aims to increase the density of the pads without further reducing the wire bonding size.
도 1a는 종래 방법의 패드 배치 및 와이어가 본딩된 상태를 도시한 상태도이다.1A is a state diagram illustrating a pad arrangement and a state in which wires are bonded in the conventional method.
도 1b는 도 1a에서 패드의 단면을 도시한 단면도이다.FIG. 1B is a cross-sectional view illustrating a cross section of the pad in FIG. 1A.
도 2a는 본 발명에 의한 패드, 패드 배치 및 와이어 본딩상태를 도시한 상태도이다.2A is a state diagram illustrating a pad, a pad arrangement, and a wire bonding state according to the present invention.
도 2b는 도 2a에서 'a' 부분 패드열의 패드 단면을 도시한 단면도이다.FIG. 2B is a cross-sectional view illustrating a pad cross section of the 'a' partial pad row in FIG. 2A.
도 2c는 도 2a에서 'b' 부분 패드열의 패드 단면을 도시한 단면도이다.FIG. 2C is a cross-sectional view illustrating a pad cross section of the 'b' partial pad row in FIG. 2A.
<도면의 주요 부분에 대한 부호 설명><Description of the symbols for the main parts of the drawings>
11 : 패드11: pad
12 : 기판12: substrate
13 : 내부 회로13: internal circuit
14 : 와이어14: wire
15 : 와이어의 본딩 부15: bonding part of wire
21 : 내부 회로21: internal circuit
22 : 패드22: pad
23 : 기판23: substrate
24 : 와이어24: wire
25 : 와이어의 본딩 부25: Bonding part of the wire
상기한 기술적 과제를 달성하기 위하여, 본 발명에 의한 패드 및 패드배치의 바람직한 일 실시 예를 첨부도면 도 2a 내지 도 2c를 참조하여 설명한다.In order to achieve the above technical problem, a preferred embodiment of the pad and the pad arrangement according to the present invention will be described with reference to the accompanying drawings, Figures 2a to 2c.
내부회로(21)의 선 폭은 패드(22)에 비해서 상대적으로 매우 가늘기 때문에 상기 패드와 패드 사이로 다수개의 내부회로들이 지나갈 수 있다. 상기한 방법, 즉 패드 사이로 회로들이 지나가게 하는 방법으로 내부회로와 연결된 패드 들을 이 열로 배치하고 이들 각 패드열의 높이가 서로 다르게, 보다 정확하게는 바깥쪽의 패드 열(a)이 안쪽의 패드 열(b)보다 더 낮게 형성되도록 미리 주 기판(23)의 높이를 형성시킨 후 상기한 패드 들을 정의하고 이들 각각의 패드에 와이어(24)의 일단을 본딩(25)하고, 상기 와이어의 또 다른 일단(도시 않음)을 외부기판의 패드(도시 않음)에 본딩 또는 적절한 방법으로 연결시키면, 인접한 와이어들 간에는 높이 차이가 유지되므로, 절연피복 등으로 보호되지 않은 와이어의 경우에도 안정적인 전기적 절연상태를 유지할 수 있게되고, 결국 와이어가 본딩된 패드의 밀집 도를 높일 수 있게 된다. 이때, 외부회로의 패드부도 상기한 방법으로 단차를 주어 형성시키면 외부회로 패드의 밀집도 역시 높일 수 있게 된다.Since the line width of the internal circuit 21 is relatively thinner than the pad 22, a plurality of internal circuits may pass between the pad and the pad. In this way, the pads connected to the internal circuit are arranged in this row in such a way that the circuits pass between the pads, and the height of each pad row is different from each other. The height of the main substrate 23 is formed in advance so as to be lower than b), and then the pads are defined and the one end of the wire 24 is bonded 25 to each of these pads, and the other end of the wire ( Bonding to the pads (not shown) of the external substrate in a suitable manner, the height difference is maintained between adjacent wires, so that even in the case of wires not protected by insulation coating, a stable electrical insulation state can be maintained. As a result, it is possible to increase the density of the pad to which the wire is bonded. At this time, if the pad portion of the external circuit is formed by giving a step in the above-described manner, the density of the external circuit pad can also be increased.
상기한 2열의 패드 배치는 일 실시 예에 불과하며, 3열 이상 다수 열의 패드 배치도 상기한 방법과 동일한 방법으로 얼마든지 가능함은 자명한 사실이다.The pad arrangement of the two rows is only an embodiment, and it is apparent that pad arrangements of three or more rows and multiple rows can be performed in the same manner as described above.
본 발명에 의하면, 패드에 연결되는 와이어의 본딩 사이즈를 더 이상 줄이지 않고도 패드의 밀집 도를 높일 수 있으며, 절연 피복 등과 같은 적절한 절연 막이 형성되지 않은 와이어를 사용하는 경우에도 인접한 와이어들이 서로 전기적으로 도통되는 문제를 방지할 수 있게된다.According to the present invention, the pad density can be increased without further reducing the bonding size of the wires connected to the pads, and adjacent wires are electrically connected to each other even when a wire without proper insulating film such as an insulating coating is used. This can prevent problems.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000044682A KR20000063735A (en) | 2000-08-01 | 2000-08-01 | Highly concentrated pad |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000044682A KR20000063735A (en) | 2000-08-01 | 2000-08-01 | Highly concentrated pad |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20000063735A true KR20000063735A (en) | 2000-11-06 |
Family
ID=19681325
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020000044682A Ceased KR20000063735A (en) | 2000-08-01 | 2000-08-01 | Highly concentrated pad |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20000063735A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9468102B2 (en) | 2013-06-18 | 2016-10-11 | Samsung Electronics Co., Ltd. | Display device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0274046A (en) * | 1988-09-09 | 1990-03-14 | Nec Ic Microcomput Syst Ltd | Semiconductor integrated circuit device |
| KR19980057437U (en) * | 1997-02-04 | 1998-10-15 | 문정환 | Chip Structure of Semiconductor Device |
| KR19990061323A (en) * | 1997-12-31 | 1999-07-26 | 윤종용 | Semiconductor package |
-
2000
- 2000-08-01 KR KR1020000044682A patent/KR20000063735A/en not_active Ceased
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0274046A (en) * | 1988-09-09 | 1990-03-14 | Nec Ic Microcomput Syst Ltd | Semiconductor integrated circuit device |
| KR19980057437U (en) * | 1997-02-04 | 1998-10-15 | 문정환 | Chip Structure of Semiconductor Device |
| KR19990061323A (en) * | 1997-12-31 | 1999-07-26 | 윤종용 | Semiconductor package |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9468102B2 (en) | 2013-06-18 | 2016-10-11 | Samsung Electronics Co., Ltd. | Display device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100426825B1 (en) | Semiconductor device | |
| US20030062620A1 (en) | Semiconductor device | |
| EP1895586A3 (en) | Semiconductor package substrate | |
| JP2568748B2 (en) | Semiconductor device | |
| US20070130554A1 (en) | Integrated Circuit With Dual Electrical Attachment Pad Configuration | |
| JPH11261010A5 (en) | ||
| KR20000063735A (en) | Highly concentrated pad | |
| JPS5954247A (en) | Electronic component parts | |
| KR100331073B1 (en) | Semiconductor Package Structure | |
| CN100401510C (en) | Semiconductor device, semiconductor body and method for manufacturing the same | |
| KR960019683A (en) | Semiconductor devices | |
| JP2935356B2 (en) | Semiconductor device and substrate, and mounting structure of semiconductor device | |
| JP2993480B2 (en) | Semiconductor device | |
| KR20040081173A (en) | Device for connecting an ic terminal to a reference potential | |
| JPH0410429A (en) | Semiconductor device | |
| JP2004022907A (en) | Semiconductor device and manufacturing method thereof | |
| KR100206975B1 (en) | Semiconductor package | |
| JP2895327B2 (en) | Transistor | |
| KR100290790B1 (en) | Antistatic Structure of Semiconductor Device and Manufacturing Method Thereof | |
| JPS6143437A (en) | Semiconductor device | |
| KR101269329B1 (en) | Semiconductor chip | |
| JPS59182548A (en) | semiconductor equipment | |
| JP2000286359A (en) | Semiconductor chip | |
| JPH03255655A (en) | Semiconductor device | |
| KR19980030136A (en) | Printed Circuit Boards Can Increase Time-Wired Wiring Rates |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| PA0109 | Patent application |
Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 20000801 |
|
| PA0201 | Request for examination | ||
| PG1501 | Laying open of application | ||
| E902 | Notification of reason for refusal | ||
| PE0902 | Notice of grounds for rejection |
Comment text: Notification of reason for refusal Patent event date: 20020516 Patent event code: PE09021S01D |
|
| E601 | Decision to refuse application | ||
| PE0601 | Decision on rejection of patent |
Patent event date: 20020724 Comment text: Decision to Refuse Application Patent event code: PE06012S01D Patent event date: 20020516 Comment text: Notification of reason for refusal Patent event code: PE06011S01I |