KR20000043571A - Fabrication method of chip sized package - Google Patents

Abstract

PURPOSE: A method for fabricating a chip sized package is provided to realize a simpler structure and a shorter electrical path than ever and to enhance a solder joint reliability. CONSTITUTION: A semiconductor chip(20) is coated with an insulating layer(60). The insulating layer(60) is then partly etched to expose chip pads(21) formed on the chip(20). Next, metal lines(40) are deposited while extending over the insulating layer(60) from the respective chip pads(21). A circuit tape may be alternatively used instead of the metal lines(40) and the insulating layer(60). On the other hand, a frame coated with a first photoresist layer except ball lands is provided. A copper layer(100) is deposited on overall surfaces of the frame, and a second photoresist layer is then coated on the copper layer(100) except the ball lands. After metal bumps are formed on the ball lands, the second photoresist layer is removed. Next, the chip(20) and the frame are conjoined together face to face. A mold body(120) is then formed, and the frame and the first photoresist layer are all removed. Therefore, the metal bumps coated with the remaining copper layer(100) are protruded from the mold body(120). Finally, a solder paste is applied to each metal bump and then reflowed, so that solder balls(141) each having the inner metal bump are obtained.

Description

Chip size package manufacturing method

The present invention relates to a method for manufacturing a chip size package.

Chip size packages have the advantage that the size of the package can be set to the size of the chip, research is being continued in accordance with the trend of light and short package. Such a chip size package uses a rigid substrate, or a pattern tape.

Among the above methods, a method using a tab tape is mainly proposed recently because a method using a substrate is very difficult to manufacture. A structure of a conventional chip size package using a tab tape will be described below with reference to FIG. 1.

As shown in the drawing, the tab tape 1 has a structure in which a solder resist 1a, a metal wiring 1b, an adhesive 1c, and an elastomer 1d: elastomer are sequentially stacked from the bottom. The semiconductor chip 2 is attached on the elastomer 1d. The pad 2a of the semiconductor chip 2 is electrically connected to the metal wiring 1b of the tab tape 1 with a copper ribbon 3: Cu ribbon. On the other hand, a ball land is formed in the soldering resist 1a, and the whole is molded with the sealing agent 4 so that this ball land may be exposed and the surface of the semiconductor chip 2 may be exposed. Solder balls 5 mounted on the substrate are attached to the exposed ball lands.

However, the chip size package using the tab tape as described above has a complicated structure of the tab tape, and thus, the package shown in FIG.

As illustrated, the intermediate layer 11 is attached to the bottom surface of the semiconductor chip 10, and the solder ball 12 is directly attached to the bottom surface of the intermediate layer 11.

However, the chip size package shown in FIG. 1 has the following disadvantages.

First, as described above, since the structure of the tab tape consists of four layers, the structure is complicated and the manufacturing process is complicated. In particular, the price of the tab tape is expensive, and also has the disadvantage that the strength is weak due to the material properties.

In addition, although the pads of the pattern tape and the semiconductor chip are bonded with a copper ribbon, the copper ribbon is often broken under high temperature processes. In addition, when epoxy series is used as an encapsulant to secure water resistance, a disconnection accident of the copper ribbon becomes a more serious problem.

On the other hand, since the package shown in Figure 2 does not use a tab tape has the advantage of a simple structure and short electrical connection, but also has the following disadvantages.

First, since both sides of the semiconductor chip are exposed, they are very vulnerable to infiltration of foreign matters or mechanical external shocks.

In addition, since the solder bonding force depends solely on the solder ball since the solder ball is directly attached to the intermediate layer, there is a disadvantage in that the size of the solder ball is increased to increase the bonding force, that is, the thickness of the package is increased. In addition, there is a high possibility that the solder ball supported by the jig in the package electrical test may be damaged, and in order to prevent the solder ball, the material of the solder ball must be expensive copper.

Accordingly, the present invention has been made to solve all the disadvantages of the conventional chip size packages, and provides a method of manufacturing a chip sage package that is not complicated in structure and can enhance foreign matter penetration or mechanical strength. The purpose is to.

Another object is to improve the electrical properties by making the electrical signal transmission path very short.

Another object is to prevent the solder balls from being damaged in various tests, by increasing the strength of the solder balls themselves.

1 and 2 are cross-sectional views showing a conventional chip size package.

Figure 3 is a bottom partially cut perspective view showing a chip size package according to the present invention

4 to 10 are views sequentially showing a chip size package manufacturing process according to Embodiment 1 of the present invention

11 is a view showing a manufacturing process according to Embodiment 2 of the present invention.

12 is a view showing a manufacturing process according to Embodiment 3 of the present invention.

13 is a view showing a manufacturing process according to Example 4 of the present invention.

14 and 15 illustrate a manufacturing process according to Embodiment 5 of the present invention.

16 is a view showing a manufacturing process according to Example 6 of the present invention;

17 is a view showing the manufacturing process according to the seventh embodiment of the present invention;

-Explanation of symbols for the main parts of the drawing-

20; Semiconductor chip 21; pad

40; Metal line 50; Bump

51; Solder paste 60; Insulating film

70; Auxiliary metal line 80; frame

90; Photoresist 100; Metal film

120; Encapsulant 141; Solder ball

In order to achieve the above object, a method for manufacturing a chip size package according to the present invention consists of the following steps.

An insulating film is applied on the surface of the semiconductor chip to a thickness of about 5 탆. A predetermined portion of the insulating film is etched to expose the pad of the semiconductor chip. A metal line is deposited on the exposed pad and the portion of the insulating layer. As described above, the metal line is deposited in a single layer or multilayer structure, and in the case of the single layer structure, an auxiliary metal line is deposited on the metal line deposited on the insulating film. Here, a tab tape may be used instead of the insulating film and the metal line. That is, when a tab tape having a structure in which an adhesive, a polyimide film, and a metal wiring layer are sequentially laminated from the bottom is applied to the surface of the semiconductor chip, and a metal bump is attached on the exposed pad, the bump presses the metal wiring layer to the pad. You are connected.

Subsequently, a photoresist is applied on the frame, and a position corresponding to the position where the auxiliary metal film is deposited is etched to form a ball land. A thin metal film such as copper is deposited on the entire surface, and photoresist is applied again on the remaining metal film except for the ball land. After the bumps of a metallic material such as copper are plated on the exposed ball lands, the upper photoresist is removed by stripping and etching to form upper ends of the bumps in a curvature shape. Then apply solder paste on top of the bumps. Here, in order to prevent a metal reaction between the bump and the material of the metal film from occurring and diffusion phenomenon, it is preferable to replace the material of the metal film with nickel instead of copper.

The semiconductor chip on which the metal line is deposited is turned over, the auxiliary metal line is mounted on the solder paste, and then the metal line and the bump are electrically connected through a reflow process. The whole is placed in a mold and the encapsulant is flowed into the mold and molded. Then, the frame is removed and the lower photoresist is dissolved and removed to expose the bumps downward in the encapsulant. The bump is then flipped over so that the bumps face upwards, and then the solder bumps are applied to the exposed bumps and reflowed to form solder balls.

On the other hand, instead of the molding process, it is also preferable to replace with a step of filling the encapsulant so that the surface of the semiconductor chip is exposed to the heat radiation action. In addition, instead of the reflow process, only solder paste may be locally heated with a laser to form solder balls. Alternatively, the solder paste may be applied to the substrate without forming the solder balls as described above, and the bumps may be directly attached to the solder paste and then reflowed.

According to the above-described configuration of the present invention, since the pad of the semiconductor chip is connected to the solder balls through a metal line which can be formed into a very short length, the electric signal transmission path is very short, and thus the structure of the package is very simple. do. In addition, since the metal bumps are embedded in the solder balls, the solder balls are prevented from being damaged in various package tests.

Best Mode for Carrying Out the Invention Preferred embodiments of the present invention will now be described based on the accompanying drawings.

Example 1

3 is a partially cut-away perspective view of a bottom surface of a chip size package according to the present invention, and FIGS. 4 to 10 are views sequentially showing a chip size package manufacturing process according to the present invention.

First, the chip size package shown in FIG. 3 shows the bottom view of the state before the solder ball for mounting the substrate is attached. As shown, a plurality of pads 21 are disposed in the semiconductor chip 20 along the periphery. An insulating film 60 is applied to the surface of the semiconductor chip 20, and in particular, each pad 21 is applied so as to be exposed. A plurality of bumps 50 made of metal such as copper are disposed on the surface of the insulating layer 60 at equal intervals in length and width, and each bump 50 is electrically connected to each pad 21 by a metal line 40. The entire package of this structure is molded with the encapsulant 120, where each bump 50 is molded to be exposed.

The solder ball is attached to the structure as described above. First, a package manufacturing process having the above configuration will be described in detail with reference to the accompanying drawings.

As shown in FIG. 4A, when the wafer to be divided into a plurality of semiconductor chips 20 is placed on the rotating plate P, the insulating film 60 is placed on the surface of the semiconductor chip 20 as shown in FIG. 4B. When spin coating while rotating, the insulating film 60 is applied to the surface of the semiconductor chip 20 to a thickness of about 5㎛ as shown in Figure 4c.

Subsequently, as illustrated in FIG. 5A, the via region 22 is formed by etching the corresponding region of the insulating layer 60 so that each pad 21 of the semiconductor chip 20 is exposed. Next, as shown in FIG. 5B, a metal tracer 40 is deposited on the exposed pad 21 and a portion of the insulating layer 60. The metal line 40 includes aluminum (Al), copper (Cu), nickel (Ni), chromium (Cr), titanium (Ti), gold (Au), platinum (Pt), palladium (Pd), and lead (pb). Or single layer structure of tin (Sn) or a multi-layered multilayer structure, preferably about 0.5 to 4 mils thick.

If the metal line 40 has a single layer structure, as shown in FIG. 5C, the auxiliary metal line 70 is deposited on the metal line 40 deposited on the insulating film 60. The auxiliary metal line 70 is a metal film for assisting the wetting action of the solder ball in a subsequent solder reflow process, and has a single layer structure such as the material of the metal line 40, or copper, nickel, gold, Copper and nickel and gold and chromium, copper and nickel and gold and cobalt, copper and nickel and gold and tin, copper and nickel and gold and chromium and tin, copper and nickel and gold and cobalt and tin, or copper and nickel and lead It is a multilayer structure made of any one. On the other hand, if the metal line 40 is a multilayer structure, since the metal line 40 itself can assist the wet action, it is not necessary to separately provide the auxiliary metal line 70.

Subsequently, as shown in FIG. 6, several semiconductor chips 20 are separated from the wafer by the cutter S. FIG. That is, FIG. 3 shows a bottom view of any one of the semiconductor chips 20 separated by the process of FIG. 6.

Hereinafter, the process of attaching the solder ball to the semiconductor chip manufactured by the above process will be described in detail.

First, as shown in FIG. 7A, a photoresist 90 is coated on a surface of a metal or plastic frame 80. A portion of the photoresist 90, which is a position corresponding to the auxiliary metal line position of the semiconductor chip, is etched to form the ball land 81. Then, a thin metal film 100 of a metal material such as copper is deposited on the entire surface.

Then, as shown in FIG. 7B, another photoresist 91 is applied to the remaining surface of the metal film 100 except for the ball lands 81, and then the metal bumps 50 are applied to the exposed ball lands 81. Plating as shown in Figure 7c. The bump 50 is one of copper, nickel, tin, lead, silver, gold, chromium, titanium, or tungsten, and is preferably formed to a thickness of about 0.2 to 0.5 mm. In addition, the thickness of the metal line is preferably about 0.5 to 4 Mil.

Subsequently, when the upper photoresist 91 is etched and removed, the bumps 50 protrude from the metal film 100 by a predetermined height as shown in FIG. 7D, and the outer surface of the bumps 50 protruding at the same time is shown in FIG. 7E. Curvature shape is achieved. On the other hand, the metal film 100 made of copper deposited in the process of FIG. 7A remains on the outer surface of the bump 50.

Then, as shown in FIG. 8A, after applying the solder paste 51 on each bump 50, the semiconductor chips 20 separated individually are disposed on the frame 80. At this time, the auxiliary metal line 70 is positioned on the vertical upper portion of each bump 51.

In this state, when the semiconductor chip 20 is pressed from above and mounted on the frame 80, the auxiliary metal line 70 and the solder paste 51 are adhered as shown in FIG. 8B, and then electrically connected through the reflow process. Connect it perfectly.

Then, as shown in FIG. 9A, the whole is placed inside the cavity of the mold 110. In particular, the lower end of the mold 110 is brought into contact with the photoresist 90 applied on the frame 80. That is, the bottom surface of the frame 80 is in the state exposed to the outside from the mold (110). In this state, the encapsulant 120 is flowed into the cavity of the mold 110, and the whole is molded into the encapsulant 120.

Subsequently, after the whole is removed from the mold 110, the frame 80 is removed, the photoresist 90 is dissolved and removed, and the bump 50 remains exposed as shown in FIG. 9B.

Finally, as shown in FIG. 10A, the solder paste 140 is applied onto each bump 50 using the stencil mask 130 in the upside-down state, and then the solder paste 140 at a maximum temperature of 235 ° C. ), The chip size package according to the present invention shown in FIG. 10B is completed.

Example 2

11 shows one of the chip size package manufacturing processes according to the second embodiment of the present invention, and the heating process is applied instead of the reflow process, which is the last process of the first embodiment.

As shown, instead of reflowing the solder paste 140, instead of locally heating only the solder paste 140 using the laser 160, it is desirable to form the solder balls 141 shown in FIG. 10B. It is possible.

Example 3

12A and 12B show one of the package manufacturing processes according to the third embodiment of the present invention, and unlike the first and second embodiments, a method of mounting on a substrate without using solder balls is shown.

First, as shown in FIG. 12A, the solder paste 140 is not applied to the bump 50, but is applied to the substrate B, and then the bump 50 is positioned above the vertical portion of the solder paste 140. The package is disposed on the substrate B.

Next, as shown in FIG. 12B, the bump 50 is directly adhered to the solder paste 140, and the package is mounted on the substrate B.

Example 4

13 is a modified example of the bump structure according to the third embodiment of the present invention. As shown in FIG. 1, in the first embodiment, a copper metal film 100 is deposited on the outer surface of the bump 50. According to the fourth embodiment, a nickel metal film 101 is deposited instead of copper.

This is because when solder balls are formed, tin or lead, which is a material of the solder ball, may react with copper, which is a material of the bump 50, to form an intermetallic compound that lowers electrical reliability. In order to prevent this, the nickel metal film 101 is used as a kind of diffusion prevention layer. The nickel metal film 101 only needs to deposit the nickel metal film 101 instead of the copper metal film 100 in the process shown in FIG. 7A.

Example 5

14 and 15 are modifications applied to tab tapes instead of metal lines and insulating films according to Embodiment 5 of the present invention.

As shown in FIG. 14, the tab tape 150 having the via holes 22 formed on the surface of the semiconductor chip 20 at positions corresponding to the positions of the pads 21 of the semiconductor chip 20. The tab tape 150 is a structure in which an adhesive layer 151, a polyimide film 152, and a patterned metal wiring layer 153 are sequentially stacked from the bottom, as is well known, and as illustrated in FIG. 15A, a semiconductor chip. Once attached to the surface of 20, the pad 21 is exposed through the via hole 22. That is, the adhesive layer 151 and the polyimide film 152 are removed from the pad 21 and only the metal wiring layer 153 is present.

In this state, when the metal wiring layer 153 is pressed onto the pad 21 by pressing the bump 52, for example, the gold bump 52, the metal wiring layer 153 is bent downward to contact the pad 21. . In the fifth embodiment, the pad 21 and the metal wiring layer 153 are bonded by bumping, but thermocompression bonding or ultrasonic waves may be used.

When comparing the structure of Example 5 and Example 1 using such a tab tape, the insulating film of Example 1 is a polyimide film of Example 5, the metal line of Example 1 is a metal wiring layer of Example 5, However, in Example 1, the insulating film can be directly fixed to the semiconductor chip, but since the polyimide film cannot be directly fixed, the adhesive layer is used, and in Example 5, a separate bump is used to contact the metal wiring layer to the pad. It's just different.

Example 6

16 shows a modification of the molding process according to Embodiment 6 of the present invention. Instead of the molding process using the mold shown in FIG. 9A of Example 1, the entire body is filled with an encapsulant 121 and molded to expose the surface of the semiconductor chip 20, as shown in FIG. 16A. The exposed surface of the semiconductor chip 20 is to enable a heat radiation action.

Example 7

FIG. 17 illustrates the configuration of a multi-chip module by arranging several pieces in the ceramic capsule 122 without molding the package according to the seventh embodiment of the present invention. A plurality of solder balls 142 are attached to the bottom surface of the ceramic capsule 122.

As described above, according to the present invention, since the electric signal transmission path from the pad to the solder ball is made by a metal line which can be formed in a very short length without using the metal wire, it is very important to construct the electric signal transmission path very short. By doing so, the electrical characteristics are improved.

In particular, since bumps of metal are built in the solder balls, the solder balls are prevented from being damaged in various package tests. In addition, since the bumps are protected by photoresist, various processes are performed, and contamination of the bumps is prevented.

In the above, a preferred embodiment for carrying out the method for manufacturing a chip size package according to the present invention has been illustrated and described, but the present invention is not limited to the above-described embodiment, but deviates from the gist of the present invention claimed in the following claims. Without this, any person skilled in the art to which the present invention pertains may make various changes.

Claims (6)

Applying an insulating film to the semiconductor chip, and forming a via hole by etching the insulating film to expose the pad of the semiconductor chip; Depositing a metal line on the via hole and a portion of the insulating film; Applying a photoresist to a frame, etching the photoresist at positions corresponding to the via holes, forming a ball land, and then depositing a metal film on the entire surface; Forming bumps on the ball lands and applying solder paste to the bumps; Mounting a metal line deposited on the solder paste and the insulating film of the semiconductor chip; Molding the whole with an encapsulant so that the frame and the photoresist are exposed, and then removing the frame and the photoresist to expose the bumps; And Forming solder balls on the exposed bumps. The method of claim 1, wherein the metal film is deposited by copper or nickel. 2. The method of claim 1, wherein the metal line is deposited in a single layer, and an auxiliary metal line is deposited on the metal line to which the solder paste is applied to assist the wetting action of the solder ball when the solder ball is formed. Chip size package manufacturing method. The method of claim 1, wherein the metal line is deposited in a multilayer structure. The method of claim 1, wherein the solder ball is formed by applying a solder paste to the bumps and reflowing the solder paste. The method for manufacturing a chip size package according to claim 1, wherein the solder balls are formed by applying a solder paste to the bumps and heating the solder paste with a laser.