KR20000017503A - A semiconductor memory apparatus - Google Patents

Abstract

A semiconductor integrated circuit device capable of achieving high data transfer efficiency in any of a continuous read operation, a continuous write operation, and a continuous read / write operation is provided.

When preparing the read delay RL from the setting of the read command RCMD # 1 until the read data # 1 is confirmed and the valid write data # 1 from the setting of the write command WCMD # 1. When the write delay up to WL is set to the same clock cycle value (= 3), the timing of the start of the access operation to the memory cell is different (3 CLOCK CYCLES) during the read operation and the write operation. Doing.

Description

Semiconductor memory device {A SEMICONDUCTOR MEMORY APPARATUS}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device in which dynamic RAM (DRAM) cells are integrated and arranged, and more particularly, to a DRAM capable of improving data transfer efficiency in a read / write mixed cycle in a high-speed random access cycle. .

Among the MOS semiconductor memory devices, DRAM has the highest integration since the memory cells constituting it are relatively simple, and are currently used as main memory in all computer devices. On the other hand, DRAMs with several high-speed data cycle functions that must improve memory performance in response to the current rapid performance improvement of microprocessors (MPUs) have been proposed or have started mass production. As a representative example, the so-called Synchronous DRAM (hereinafter referred to as SDRAM), which exchanges all input and output information in synchronization with the system clock, can be accessed by triggering both edges of the clock up and down while operating in the same manner. Double Data Rate SDRAM (hereinafter referred to as DDR-SDRAM).

In addition, Rambus DRAMs (hereinafter referred to as RDRAMs), etc., in which data transfer is performed at a higher speed by protocol-based commands, have been developed. Among the conventional asynchronous DRAMs, the transition to these synchronous DRAMs has been developed. The flow can be said to be inevitable in the future.

This synchronous DRAM is characterized by a very high maximum bandwidth (data transfer rate). For example, 100 Mbps is achieved as the maximum bandwidth in the latest SDRAM.

It is also expected to reach 200 Mbps in future DDR-SDRAM and 800 Mbps in RDRAM.

However, such a high bandwidth can be realized only in burst access in a limited specific row direction of the memory space.

In other words, the speed at the time of random access, in which the row address changes, is only about the same speed as the conventional asynchronous DRAM. As a countermeasure, in a computer system employing DRAM as a main memory, hierarchical memory is adopted as a general method.

Specifically, a cache memory composed of SRAMs having faster access than DRAMs is disposed between the MPU and the DRAMs, and information of a part of the DRAMs is cached in the SRAMs. In this case, the system accesses from the DRAM only when the memory access from the MPU is made from the high speed cache memory, and an access instruction is obtained in an address space not cached in the cache memory. By this method, even when there is a difference in speed performance between the MPU and the DRAM, computer system performance is greatly improved.

In the case of a cache miss, however, reading from the DRAM is required, and in particular, when another row address in the same block of the DRAM memory space is accessed, the maximum waiting time occurs in the MPU. This problem will be described below with reference to FIG. 14 taking SDRAM as an example.

Fig. 14 shows an example of the read operation timing of the SDRAM. If a cache miss occurs in a computer system employing the above-described layering of memory, and a need for access from the SDRAM occurs as a main memory, a precharge of the currently active address from the system side should be performed at time t1, and precharged. The command PRECHARGE is issued. Subsequently, after a predetermined time elapses, an activation command ACTIVE is issued from the MPU, and a bank corresponding to the required memory space is activated. After a specific time elapses, a read command READ is issued. From time t2 after a specified time from this read command, data of a particular burst length is read out from the SDRAM in synchronization with a clock.

As shown in Fig. 14, the maximum bandwidth in the case of continuously reading in synchronization with the clock is very high, but the practical bandwidth for random access in the case of cache miss is significantly reduced. In other words, it is understood that the time for which data is not read from time t1 to t2, in other words, the waiting time when viewed from the MPU side is large.

Specifically, in the SDRAM specification shown in Fig. 14, the maximum bandwidth at random cycles is only about 36% of that at burst cycles. This is likely to be the bottleneck for future computer system performance improvements.

In view of these problems, there is a growing demand for high performance DRAMs that realize faster access times and cycle times. In particular, in the multi-MPU system centered on the current high-performance server machine, not only high-speed burst transmission but also high-speed random access is important, and the same high-speed random is also used in a commercial multimedia system whose main purpose is to reproduce real-time video in the future. It is believed that an accessible DRAM is required.

As a DRAM based on such a request, Enhanced SDRAM (hereinafter referred to as ESDRAM) announced by Enhanced Memory Systems Inc. as shown in FIG. 15 and Virtual Channel Memory (hereinafter referred to as NEC) as shown in FIG. , VCM).

However, in the ESDRAM, as shown in FIG. 15, a cache (SRAM CACHE) 101 composed of SRAMs is built into each bank. In the VCM, as shown in FIG. 16, a cache (1K CACHE) composed of register circuits is shown. In addition to the conventional DRAM memory cell array, for example, the 102 is loaded with 16K bits, a large-capacity cache memory unit is newly installed. In this way, the high-speed access and the high-speed cycle are realized, and there is a problem that the overhead for the chip size is high and the cost reduction is difficult to be achieved.

As a method of achieving both high speed random access performance and low cost, there is a method of abolishing the concept of page cycle, which is an operation mode of a conventional DRAM.

More specifically, as shown in FIG. 17, when the read command RCMD # 1 is issued at time t1, activation of the word line WL is started to read the cell data into the bit line group bBL / BL. After that, the sense amplifier is activated at time t2. When the cell data is detected by the sense amplifier, the column select line CSL is activated at time t3, and the bit line data is transferred to a data line (not shown) inside the chip, which is read out of the chip. The data is propagated to the desired voltage by the sense amplifier by using the time that data propagates through the wiring from the data line inside the chip to the reading unit. When amplification is completed at time t4, a series of precharge operations called inactivation of the word line WL and precharge of the bit line are automatically started. Thereby, without the page access function, it becomes possible to complete a series of access sequences in the shortest time, and as a result, a high speed random cycle can be realized.

On the other hand, as a method of improving the data transfer capability from the synchronous memory to the maximum, so-called read delay (RL), which is a delay time from the setting of the read command to the confirmation of the read data, and the write command, A memory in which a so-called write delay (WL) is set to the same clock cycle value has been devised, which is a delay time from setting to preparing valid write data. For example, a No Bus Latency SRAM (NoBL SRAM) proposed by Cypress Semiconductor Corporation is one example.

In a conventional pipeline SRAM, as shown in FIG. 18, four clock cycles were required to realize a read / write mixing cycle. In the NoBL SRAM, as shown in FIG.

In this way, the NoBL SRAM sets R.L. and W.L. to the same clock cycle value (both two clock cycles in Fig. 19), thereby enabling data reading and writing to be performed without unnecessary idle cycles, and improving the data transfer capability.

The problem when the method of setting such R.L. and W.L. to the same clock cycle value is incorporated into the DRAM will be described below.

Unlike the SRAM, the DRAM needs to read the data read into the sense amplifier after the operation in the memory is a low system round which is representative of the word line WL driving and the sense amplifier driving. An example of this is as shown in FIG. In other words, reading from the memory cell of the DRAM requires a valid time after completion of the row-based operation, that is, after cell data is detected and amplified by the sense amplifier. A specific example is shown in FIG. 20 shows the internal operation state at the time of reading in correspondence with time.

As shown in Fig. 20, 10 ns of cell data is activated by a sense amplifier until the word line is activated from the setting of the read command and the cell data is read from the memory cell to the bit line (WL Activation: W.ACT.). 5 ns until detection (Sensing: SENSE.), 10 ns until cell data amplified by sense amplifier (Restore: RSTRE), and 5 ns for precharge (Equalize: EQL). have. The cycle time of the DRAM in this case is 30 ns.

As shown in Fig. 20, when the concept of page cycles is abolished, the data read of the DRAM can be performed in parallel with the amplification of the cell data at the stage where the cell data is detected by the sense amplifier. This is because the precharge (EQL.) Is automatically started when the sensing (SENSE.) And amplification (RSTRE.) Of the cell data by the sense amplifier is completed.

Here, when it is assumed that about 8 ns is required until the cell data is read out of the chip via the data line inside the chip (Data Transfer: D.TRS.), The column select line CSL is determined by the sense amplifier. If the cell data is detected at the time when the detection is completed, the time from the setting of the read command to the actual reading of the data out of the chip (ACCESS TIME) requires about 25 ns.

If this is transferred to the data bus in synchronization with the rise of the external clock CLK, as shown in Fig. 20, R.L. becomes three clock cycles (this state is defined as R.L. = 3).

On the other hand, consider writing the data into the DRAM. When WL is set to three clocks with the same clock cycle value as RL, the write data determined at the timing of the third clock from the setting of the write command is taken into the chip, and the data is sent to the sense amplifier via the data line inside the chip. Will be sent. However, as can be seen from Fig. 20, at the timing of the third clock from the setting of the write command, the DRAM is already in the precharge (EQL.) State. For this reason, writing data into the memory cell becomes impossible.

In order to eliminate this, the time until the transition to the precharge operation at the time of recording may be set longer than the time until the transition to the precharge operation at the time of reading. That is, the cycle time at the time of writing may be longer than the cycle time at the time of reading. However, since the cycle time at the time of writing is lengthened, in the case of a read / write mixed cycle, there is a problem that the data transfer efficiency is remarkably lowered and the advantages of the high speed random cycle DRAM are remarkably impaired.

As described above, in a DRAM which realizes a high-speed cycle by eliminating the concept of page cycles, since the clock cycle value of the read delay RL and the clock cycle value of the write delay WL are different from each other, different column addresses within the same page are used. It is difficult to improve the data transfer efficiency in the continuous read / write operation with the bits corresponding to the following.

On the other hand, when the clock cycle value of the read delay R.L. and the clock cycle value of the write delay W.L. are set equal, the cycle time at the time of writing cannot be longer than the cycle time at the time of reading. This is to prevent the DRAM from entering the precharge state when the write data is input. For this reason, data transfer efficiency does not improve.

SUMMARY OF THE INVENTION The present invention has been made in view of the above, and an object thereof is a semiconductor memory device comprising a memory unit capable of reading information from a memory cell in accordance with a read command and writing information into the memory cell in accordance with a write command. A semiconductor memory device capable of obtaining high data transfer efficiency in any of a continuous read operation, a continuous write operation, and a continuous read / write operation.

In order to achieve the above object, a first aspect of the present invention includes a memory cell including a plurality of memory cells integrated and arranged in a matrix shape, and includes a read command among a plurality of commands set in synchronization with an external clock. And a memory unit capable of respectively reading information from the memory cell and writing operation to write information to the memory cell in accordance with a write command. The first delay time from setting of the read command to confirming valid read data and the second delay time from setting of the write command to preparing valid write data are set to the same clock cycle value. When present, the start timing of the access operation to the memory section is different from the read operation and the write operation.

In the semiconductor integrated circuit device having the above-described configuration, the first and second delay times are set to the same clock cycle value, respectively, and the start timing of the access operation to the memory section is different between the read operation and the write operation.

In particular, the timing of the start of the access operation to the memory unit differs between the read operation and the write operation, so that the second delay time is equal to the first delay time even when the cycle time at the time of writing and the cycle time at the time of reading are the same. The clock cycle value can be set. That is, when valid write data is prepared, it is possible to avoid the problem that the memory section is already in the precharge state.

Thus, high data transfer efficiency can be obtained both in the continuous read operation and in the continuous write operation.

In addition, since the first delay time and the second delay time can be set to the same clock cycle value without making the cycle time in the write operation longer than the cycle time in the read operation, high data transfer even during continuous read / write operations. Efficiency can be obtained.

Therefore, it is possible to obtain a semiconductor integrated circuit device in which high data transfer efficiency can be obtained in any of a continuous read operation, a continuous write operation, and a continuous read / write operation.

In addition, in the second aspect of the present invention, the first delay time from the setting of the read command until the read data is confirmed, and the second delay time from the setting of the write command to preparing valid write data When set to the same clock cycle value, a first write operation mode in which information writing to a memory cell is completed within a write operation command cycle in which the write command is set, and a write operation command to the memory cell in a write operation command cycle in which the write command is set; One or both of the second recording operation modes in which the information recording is not completed are set.

In the semiconductor integrated circuit device having the above-described configuration, similarly to the semiconductor integrated circuit device of the first aspect, a semiconductor memory device capable of improving data transfer efficiency during continuous read / write operations can be obtained.

In addition, when the second write operation mode is set, generation of unnecessary idle cycles can be suppressed during continuous read / write operations. Therefore, the data transfer efficiency in the continuous read / write operation can be further improved.

1A is an operation waveform diagram during continuous read of a DRAM according to a first embodiment of the present invention, and (b) is an operational waveform diagram during continuous write of a DRAM according to a first embodiment of the present invention.

2 is an operation waveform diagram during a read / write mixing cycle of a DRAM according to the first embodiment of the present invention;

3 is an operation waveform diagram during a read / write mixing cycle of a DRAM according to a second embodiment of the present invention;

4 is another operation waveform diagram during a read / write mixing cycle of a DRAM according to the second embodiment of the present invention;

5 is a block diagram of a DRAM according to the second embodiment of the present invention.

Fig. 6A is a block diagram of an example of a command decoder & controller, and Fig. 6B is a block diagram of another example of a command decoder & controller.

Fig. 7 is still another operational waveform diagram at the time of a read / write mixing cycle in the second embodiment of the present invention.

8 is a block diagram of a DRAM according to the third embodiment of the present invention.

Fig. 9A is a block diagram of an example of the consistency determiner, and Fig. 9B is a block diagram of another example of the consistency determiner.

10 is a block diagram of a DRAM according to the fourth embodiment of the present invention.

11A is a circuit diagram showing one circuit example of a control signal generator, (b) is a circuit diagram showing one circuit example of a shift register, and (c) is a timing chart showing clocks CLK and / CLK.

12 is a circuit diagram showing an example of a circuit of a consistency determiner.

Fig. 13 is a circuit diagram showing an example of a circuit of a refresh controller.

14 is an operational waveform diagram of a conventional SDRAM.

15 is a block diagram of a conventional ESDRAM.

16 is a block diagram of a conventional VCM.

Fig. 17 is an operation waveform diagram of a DRAM abolishing the conventional concept of page access.

18 is an operational waveform diagram of a conventional pipeline SRAM.

19 is an operational waveform diagram of a conventional NoBL SRAM.

20 is a diagram for explaining a problem of DRAM abolishing the conventional concept of page access.

<Explanation of symbols for main parts of drawing>

1: clock buffer

2: Command Decoder & Controller

3: address register

4: input data register

5: address buffer

6: data input buffer

7: control signal generator

8: row decoder

9: thermal decoder

10: I / O control circuit

11: Sense amplifier I / O gate

12: memory cell array

13: data output buffer

14: consistency checker

15: refresh controller

21: delay recording detector

22, 22 ': command decoder

23: switch

23 ': switch circuit

24: normal recording controller

25: delay recording controller

31: first determination circuit

32: second determination circuit

33: resistor circuit

41: control signal generation circuit for write operation

42: control signal generation circuit for read operation

43: input circuit

44: shift register circuit

45: control circuit for the delay write operation

46: output circuit

47: output control circuit

48: input circuit

49: output circuit

51: NAND gate circuit

52: shift register

61: clock type inverter

62: inverter

63: clock type inverter

71: ADN gate circuit

72: NOR gate circuit

81, 82: clock type inverter

91, 92: AND gate circuit

93: NOR gate circuit

101: resistor circuit

102: address comparison circuit

103: output circuit

112: buffer (inverter)

121: EX-NOR gate circuit

122: NOR gate circuit

132: Inverter

141: register circuit

142: output circuit

152: buffer (inverter)

161: NOR gate circuit

162: clock type inverter

EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention is described with reference to drawings.

In addition, although the embodiment described below illustrates the SDRAM which can perform the high speed random cycle which canceled the page cycle function, this invention is applicable also to the SDRAM which has a page cycle function.

[First Embodiment]

1A and 1B are operation waveform diagrams of the SDRAM according to the first embodiment of the present invention, respectively, and assume a case of operating in synchronization with an external clock CLK having an operating frequency of 100 MHz. . The delay time from the setting of the read command to the data output, that is, the read delay RL is " 3 ", and the delay time from the setting of the write command to the preparation of valid write data, i.e., the write delay WL is " 3 " The clocks are set to the same clock cycle value.

In addition, in the operation waveform diagrams of Figs. 1A and 1B, an operation state inside the SDRAM is added. As an operation state,

(1) An operation state in which a word line is activated from the setting of a read command and electrically connects a memory cell and a bit line (WL Activation: W.ACT .: word line activation).

(2) The operating state of detecting the bit line data by the sense amplifier (Sensing: SENSE: data detection).

(3) Operation state of amplifying bit line data by sense amplifier (Restore: RSTRE: Data amplification)

(4) An operation state in which the word line WL is inactivated and the bit line is precharged (Equalize: EQL .: precharge).

(5) Operation state for reading data of the bit line to the outside of the chip (Data Transfer: D.TRS .: Data Transfer)

Assume the above five.

The operating speeds in each operation state are assumed to be about 10 ns for word line activity, about 5 ns for data detection, about 10 ns for data amplification, about 5 ns for precharge, and about 8 ns for data transfer.

Based on these assumptions, the basic specification of the SDRAM according to the first embodiment is the time from word line activity to precharge, that is, cycle time is about 30 ns, from the setting of the read command until the data is read out of the chip. The time, ie the access time, is about 25 ns. The cycle time (READ CYCLE TIME) at the time of reading and the cycle time (WRITE CYCLE TIME) at the time of writing are equally about 30 ns (= 3 clock cycles).

Hereinafter, the SDRAM according to the first embodiment of the present invention will be described taking this SDRAM as an example.

Fig. 1A is an operating waveform in a continuous read cycle.

As shown in Fig. 1A, when the read command RCMD # 1 is input to the chip in synchronization with the rise of the external clock CLK at time t1, data is read about 25 ns after this, and at time t2, The read data # 1 is determined at the timing RL = 3. Further, at time t2 30 ns after time t1, when the read command RCMD # 2 is input to the chip again, maximum data efficiency can be obtained.

1B is an operating waveform in a continuous write cycle.

As shown in Fig. 1B, even in a continuous write cycle, the write command WCMD # 1 is input to the chip at time t1, and the write data # 1 is written to the chip at time t2 (WL = 3). Enter it.

At this time, the operation inside the DRAM has the following characteristics, which is a key point of the present invention. That is, the start time of operation in the DRAM at the time of writing is delayed compared to the start time of operation in the DRAM at the time of reading so that the write data # 1 can be completely written into the memory cell.

For example, as shown in Fig. 1B, the start of the word line WL starts at time t2 three clock cycles after the input time t1 of the write command WCMD # 1 (access to the memory section). Start of operation). As a result, the timing of transferring the write data to the sense amplifier via the data bus inside the chip can be made to substantially match the timing at which the activation of the word line WL of the memory cell corresponding to the address to be written is completed. Therefore, the memory cell corresponding to the address to be written is written in parallel with the time when the rewrite (detection and amplification) of the memory cell data corresponding to an address other than the memory cell as the write object connected to the word line WL is performed. You can record on

As described above, in the recording, as in the reading, at the time t2 30 ns after the time t1, the rewrite command WCMD # 2 can be input to the chip, and the maximum data transfer capability is obtained in the continuous reading and the continuous writing. The same can be set.

As described above, the operation start time in the DRAM at the time of writing is delayed by at least one clock cycle or more (three clock cycles delay in FIG. 1B) compared to the operation start time in the DRAM at the time of reading, so that the continuous read cycle or Even during continuous write cycles, the data transfer capacity can be set to the maximum.

Accordingly, in an SDRAM capable of reading information from a memory cell in response to a read command and writing information into the memory cell in response to a write command, even when RL and WL are set to the same clock cycle value, the operation in the DRAM is inconsistent. In other words, the DRAM does not become precharged when the write data is input, and the data transfer capability can be improved.

In the present embodiment, an example in which the operation start time in the DRAM at the time of writing is delayed by 3 clock cycles (30 ns) compared with the operation start time in the DRAM at the time of reading is shown. Of course, the frequency and operating speed performance of the DRAM can be appropriately changed.

Second Embodiment

As described in the first embodiment, the W.L and R.L can be set to the same clock cycle value by delaying the operation start time in the DRAM at the time of writing compared with the operation start time in the DRAM at the time of reading.

However, in the case of a write / read mixed cycle, a phenomenon occurs that an unnecessary idle cycle occurs between certain commands. This phenomenon is explained with reference to FIG.

2 shows continuous reading, writing, reading, recording, ...; This subsequent access sequence is assumed.

In this case, it is possible to input a command at an interval (3 clock cycles) determined by the cycle time of the DRAM from read to write, but in the case of a transition from write to read, 6 clock cycles are required. As a result, there are three idle cycles (IDLE CYCLE). The reason for this is that the operation start time in the DRAM at the time of writing is delayed by three clock cycles compared with the operation start time in the DRAM at the time of reading, so the completion of the write operation is inevitably delayed, and as a result, the transition to the read operation is impossible. Because. This form is shown in FIG. 2 as operation timing inside the DRAM.

As described above, in the case of DRAM incorporating a method of setting R.L. and W.L. to the same clock cycle value for the purpose of increasing the efficiency of the data bus, an idle cycle exists in a read operation cycle immediately after a write operation cycle. If the improvement in the idle cycle, that is, the interval from the write command to the subsequent read command can be shortened, the data transfer capability of the DRAM according to the present invention can be further improved.

The second embodiment aims to shorten the interval from the write command to the subsequent read command to further improve the data transfer capability of the DRAM.

3 is an operation waveform diagram of a high speed random cycle DRAM corresponding to the second embodiment.

As shown in Fig. 3, even in a continuous cycle of read / write, there is no idle cycle in particular between the write operation cycle and the read operation cycle. This is because, as shown in FIG. 3 as the operation timing in the DRAM, in the second embodiment, the timing at which the write operation is actually performed in the memory cell in the DRAM starts from the time when the next write command is set. That is, for example, the write operation of data into the DRAM defined by the first write command WCMD # 1 is controlled to start from the timing at which the second write command WCMD # 2 is set.

Hereinafter, when the write operation to the DRAM in real time is set to start from the time when the next write command is set, the reading, writing, reading, writing, ... Even in the case of this continuous access sequence, there is no unnecessary idle cycle. Accordingly, even in the case of introducing a method of improving data transfer efficiency by setting RL and WL to the same clock cycle value (in this case, 3) in a DRAM having a high speed random cycle in which the concept of page cycles has been abolished, Since there is no contradiction in the internal operation, the idle cycle can be eliminated.

In addition, as described above, it is also possible to set two types of recording modes by distinguishing the method of starting the write operation inside the DRAM from the time when the next write command is set from the "normal write operation". In this case, the recording operation according to the second embodiment is referred to as "delay recording operation" in the sense of distinguishing it from the "normal recording operation". These two write operations can also be freely set on the system side by using the control pins of the DRAM.

4 shows an example of the operation timing when the read / write mixing cycle is realized by using two kinds of write operations.

In the example shown in Fig. 4, an example is provided in which a dedicated access control pin is provided and a control signal DW (Delayed Write: DW) is input to the control pin in order to distinguish between the "normal write operation" and the "delayed write operation". have.

In addition, the example shown in FIG. 4 assumes a case where a delayed write operation is performed when the control signal DW is set to "HIGH level" in a cycle in which a write command is set.

As shown in the operation timing inside the DRAM of Fig. 4, the first write command WCMD # 1 is set to " delay write operation ", and immediately after that, the read command RCMD # 1 is continued and Even when the second write command WCMD # 2 is later set to " normal write operation ", the operation inside the DRAM is not inconsistent, and two write operations and one read operation are possible. This is evident from the operation timing of the DRAM inside the DRAM appended to Fig. 4, in which the operation of the DRAM is necessarily determined, that is, the operation of the DRAM does not overlap at any timing.

In addition, the problem that the DRAM does not become a precharge state when the write data is input does not cause a problem that the operation start time at the time of reading the operation start time of the "normal write operation" as described in the first embodiment. This is delayed by 3 clock cycles. During these three clock cycles, when the write operation preceding this is a "delayed write operation", it becomes possible to complete the write operation. In other words, in order to enable the "delay write operation", it is necessary to delay the operation starting point in the DRAM during the "normal write operation" beyond the cycle time of the DRAM operation.

In this embodiment, in order to distinguish between a "normal write operation" and a "delay write operation", although the example which provided the dedicated access control pin and inputs the control signal DW was shown, it is not limited to this. For example, the state of a particular pin is useful, and moreover, it is possible to combine multiple pins, or to define the operation of either "normal write operation" or "delay write operation" in a mode register setting cycle used in a typical SDRAM. Of course, it can be realized by various methods.

5 is a block diagram schematically showing an example of the configuration of a DRAM according to the second embodiment.

As shown in Fig. 5, the external input clock CLK, which is a reference for all operation timings, is input to the clock buffer 1, and then appropriately inputted to the main block to define the operation timing of the main block in the DRAM. . In the present embodiment, the external input clock CLK is input to the clock buffer 1, and then the address buffer ADDRESS BUFFERS 5, the data input buffer DIN BUFFER 6, and the CONTROL SIGNAL GENERATOR 7 ) And an example of input to the data output buffer (Dout BUFFER) 13 are shown.

The command defining clock group (/ CS, etc.) composed of the chip select signal / CS and the like is input to the command decoder & controller 2. The command decoder & controller 2 decrypts various commands and controls operations in the DRAM in accordance with the decrypted result. In addition, as in the present embodiment, when the control signal DW is input, the control signal DW is input to the command decoder & controller 2. Thereby, in the command decoder & controller 2, it is determined whether two types of write operations, i.e., "normal write operation" or "delay write operation", and any one of these write operations is defined inside the DRAM.

When the "delay write operation" is specified, the command decoder & controller 2 activates the address register ADDRESS REGISTER 3 and the input data register 4 respectively. In addition, the address register 3 is connected to the output of the address buffer ADDRESS BUFFERS 5 to which the external address ADDRESS is input, and the input data register 4 receives the write data from the data pins DQ0-DQn. Is connected to the output of the data input buffer (Din BUFFER) 6. By activating the address register 3, the address register 3 holds and stores the address information of the cell to be delayed write. Also, the input data register 4 is activated, whereby the input data register 4 is delayed. The recording data information to be recorded is held and recorded respectively.

The command decoder & controller 2 controls the CONTROL SIGNAL GENERATOR 7, and the timing of the external input clock CLK is different from the operation starting timing in the normal write operation, delayed write operation, and read operation. Determined in synchronization with Then, the control signal generator 7 is a row decoder (ROW DECODER) 8, a column decoder (COLUMN DECODER) 9, and an I / O CONTROL CIRCUITS (10), which is a core circuit part of the DRAM. Determine the operation timing.

In the "normal write operation", write data input from the data pins DQ0-DQn to the data input buffer 6 is stored in the I / O control circuit 10 and the I / O gate & sense amplifier SENSE AMP. It is written to a memory cell (not shown) formed in the memory cell array 12 via the & I / O GATE 11.

In the "delayed write operation", the write data stored and held in the input data register 6 is similar to the "normal write operation" in the I / O control circuit 10 and the I / O gate & sense amplifier 11. By way of example, the memory cells are written to memory cells (not shown) formed in the memory cell array 12.

On the other hand, in the " read operation ", information held and stored in a memory cell (not shown) is transferred from the I / O gate & sense amplifier 11 to the data output buffer Dout via the I / O control circuit 10. From the BUFFER 13 is read to the data pins DQ0-DQn.

Next, a configuration example of the command decoder & controller 2 for realizing the second embodiment will be described.

FIG. 6A is a block diagram schematically showing a first configuration example of the command decoder & controller 2. As shown in FIG. 6A shows only the connection portion of the command decoder & controller 2 and the control signal generator 7 among the command decoder & controller 2.

As shown in Fig. 6A, the first configuration example includes a delayed write detector 21, a command decoder 22, a switch 23, and a normal write controller NORMAL. WRITE CONTROLLER 24 and DELAYED WRITE CONTROLLER 25.

The delay recording detector 21 receives the control signal DW and detects whether it is a "delay recording operation" or a "normal recording operation" depending on whether the signal is "HIGH level" or "LOW level". This detection result is transmitted to the command decoder 22.

The command decoder 22 receives the command specification clock group (/ CS ETC.), decodes the input command, and determines, for example, whether it is "write" or "read". When the command decoder 22 of the first configuration example determines that " write ", the command decoder 22 again refers to the detection result from the delay write detector 21 to determine again whether it is a "delay write operation" or a "normal write operation". do. Based on this determination result, the switch 23 is controlled to be switched.

In the case of "normal recording operation", the switch 23 normally connects the recording controller 24 to the control signal generator 7. As a result, the control signal generator 7 is normally controlled by the output from the recording controller 24.

On the other hand, in the case of the "delay write operation", the switch 23 connects the delay write controller 25 to the control signal generator 7 instead of the normal write controller 24. Thereby, the control signal generator 7 is connected to the delay write controller 25, and the control signal generator 7 is to be controlled by the output from the delay write controller 25.

FIG. 6B is a block diagram schematically showing a second configuration example of the command decoder & controller 2. As shown in FIG. 6B shows only the connection portion of the command decoder & controller 2 and the control signal generator 7 among the command decoder & controller 2 similarly to FIG. 6A.

As shown in Fig. 6B, the second configuration example includes a command decoder 22 ', a switch circuit 23', a normal write controller 24 and a delay write. DELAYED WRITE CONTROLLER 25.

The second configuration example is particularly different from the first configuration example in that a control signal DW is input to the command decoder 22 '. Thereby, the command by the combination of the control signal DW and the command specification clock group / CS ETC. is input to the command decoder 22 '. Then, the input command is decrypted.

In addition, the second structural example includes one structural example of the switch 23.

One structural example of the switch 23 is a switch circuit 23 'constituted by a plurality of logic circuits. 6B shows an example of a circuit of the switch circuit 23 '.

As shown in Fig. 6B, one circuit example of the switch circuit 23 'is an AND circuit 26-1 for controlling whether or not to activate an output of the recording controller 24, and delayed recording. AND circuit 26-2 for controlling whether to activate the output of the controller 25, and NOR circuit 27 for outputting the logical sum of the outputs of these two AND circuits 26-1 and 26-2. It is composed.

In the "normal write operation", the command decoder 22 'of the second configuration example sets the output to "HIGH level". The output of this "HIGH level" is input to the AND circuit 26-1. As a result, the AND circuit 26-1 is activated to change its output level in accordance with the output level of the normal write controller 24. FIG. As a result, the output of the normal recording controller 24 is activated.

The output of the "LOW level" inverted by the inverter 28 is input to the AND circuit 26-2. For this reason, the AND circuit 26-2 is activated as opposed to the AND circuit 26-1. Therefore, the output level of the AND circuit 26-2 is fixed to the "LOW level", regardless of the output level of the delay write controller 25. FIG.

The NOR circuit 27 receives an "LOW level" output from the AND circuit 26-2 and is activated, and changes its output level in accordance with the output level of the AND circuit 26-1. As a result, the output from the normal recording controller 24 is input to the control signal generator 7, so that the control signal generator 7 can be controlled by the output from the normal recording controller 24.

On the other hand, in the "delay write operation", the command decoder 22 'of the second configuration example sets the output to "LOW level". For this reason, as opposed to the "normal write operation", the AND circuit 26-1 becomes inactive, and its output level is fixed to the "LOW level" irrespective of the output level of the normal write controller 24. FIG. . In addition, the AND circuit 26-2 becomes active, and its output level changes in accordance with the output level of the delay write controller 25. In other words, the output of the delay recording controller 25 becomes active.

The NOR circuit 27 receives the output of the "LOW level" from the AND circuit 26-1, becomes active, and changes the output level according to the output level of the AND circuit 26-2. As a result, the output from the delay write controller 25 is input to the control signal generator 7 so that the control signal generator 7 can be controlled by the output from the delay write controller 25.

By the configuration as shown in Figs. 6A and 6B, the command decoder & controller 2 can determine whether it is a "normal write operation" or a "delay write operation". And, in the "normal recording operation", the output from the normal recording controller 24 can be input to the control signal generator 7, and in the "delay recording operation", the output from the delay recording controller 25 is controlled. It can be entered into the generator 7. As a result, one of the " normal write operation " and " delayed write operation &quot; can be defined inside the DRAM.

[Third Embodiment]

The third embodiment relates to another control method of the "delay recording operation" described in the second embodiment.

In the second embodiment, the actual write operation to the memory cell corresponding to the address for which the " delay write operation " is specified is performed at a high speed without an idle cycle by starting the operation from the timing at which the next write command is set. Although it has been described that successive read / write mixing cycles are feasible, there may be a case where a read command from the memory cell corresponding to this address is set immediately after the "delay write operation" is set.

Fig. 7 shows the operation timing of this access sequence. This is the case where the read command RCMD for the same address is input immediately after the delay write command WCMD corresponding to the predetermined address ADD1. In this case, since information is not recorded in the memory cell corresponding to the address for which the " delay write operation " is specified, when reading information from the memory cell, the information of the memory cell data is rewritten during delay writing. In this case, there arises a problem that data consistency (coherency) cannot be maintained. That is, since the written data is not actually written in the memory cell, the data before writing is read out.

The purpose of the third embodiment is to read the recorded data even if the recorded data is not actually recorded in the memory cell.

In order to achieve this object, in the third embodiment, when data has not yet been written to a read requested memory cell, information to be written into this memory cell is stored without reading data from the read requested memory cell. • Read data from the held input data register (4). This eliminates the problem that data integrity cannot be maintained.

8 is a block diagram schematically showing an example of the configuration of a DRAM according to the third embodiment.

As shown in FIG. 8, the DRAM according to the third embodiment is particularly different from the DRAM shown in FIG. 5 in that it blocks the read path from the coherence detector 14 and the memory cell. At the same time, the switches SW1 and SW2 are newly added to conduct the read path from the input data register 4.

When the read command is decoded by the command decoder & controller 2, the consistency determiner 14 determines whether the "delay write operation" is set before this command cycle. Thereafter, the address from the address buffer 5 is compared with the address from the address register 3, and it is determined whether or not the address corresponding to the "delay write operation" is read. When this determination result is set to "true", that is, "delay write operation", and the address of the memory cell for which the delay write request is requested and the address of the memory cell for which the read request is matched, the consistency determiner 14 is set to I / I. The non-conductive control of the switch SW1 disposed between the O control circuit 10 and the data output buffer 13 and the conduction of the switch SW2 disposed between the input data register 4 and the data output buffer 13. To control. As a result, the read path from the memory cell is interrupted and the read path from the input data register 4 is conducted so that data is read from the input data register 4. The data stored and held in the input data register 4 is data to be written to the memory cell for which read is requested. Therefore, it is possible to solve the problem of the integrity of the data that the data to be recorded is not read and the data before writing is read.

Next, a configuration example of the consistency determiner 14 for realizing the third embodiment will be described.

FIG. 9A is a block diagram schematically showing a first configuration example of the consistency determiner 14.

As shown in FIG. 9A, the first configuration example includes a first determination circuit 1ST CHECKER 31 and a second determination circuit 2ND CHECKER 32.

The first determination circuit 31 determines whether there is information in the input data register 4 that has not yet been written to the memory cell. The second determination circuit 32 determines whether the information in the address register 3 that holds the address information for which the "delay write operation" is specified and the address input from the outside match.

When the first judging circuit 31 determines that "information remains in the input data register 4", the "delay write operation" is set before the cycle in which the read command is input. In other words, the output information of the first determination circuit 31 is "true".

In addition, when the information in the address register 3 and the address input from the outside coincide with the second determination circuit 32, the memory cell in which data is written and the memory cell in which data is read out match. In other words, the output information of the second determination circuit 32 is "true".

As described above, when the output information of the first and second determination circuits 31 and 32 are both "true", the consistency determiner 14 controls the switch SW1 to be non-conductive and simultaneously switches the switch SW2. To control the conduction. As a result, as described above, the read path from the memory cell is interrupted, and the read path from the input data register 4 is conducted so that data is read from the input data register 4.

FIG. 9B is a block diagram schematically showing a second configuration example of the consistency determiner 14.

As shown in FIG. 9B, the second configuration example differs from the first configuration example in that a register circuit (REGISTER) 33 is provided instead of the first determination circuit 31. As a result, the signal input from the input data register 4 can be omitted.

An example of the register circuit 33 for omitting the signal input from the input data register 4 is set when the "delay write operation" is set, and is operated to be reset when the "conductive write operation" is set.

The second judging circuit 32 receives the output of the register circuit 33 and determines whether or not the information in the address register 3 that holds the address information for which the "delay write operation" is specified matches the address input from the outside. Determine.

When the output information of the second determination circuit 32 is " true " as described above, the consistency determination unit 14 conducts the switch SW2 at the same time as the first configuration example, while controlling the non-conduction control of the switch SW1. To control.

In addition, the function of the register set or reset by the "delay write operation" and the "normal write operation" may be incorporated in the command decoder & controller 2. In this case, the consistency determiner 14 can be comprised only by the 2nd determination circuit 32, and the consistency determiner 14 can be simplified more.

[4th Embodiment]

The fourth embodiment is an auxiliary control method for the delay recording operation described in the third embodiment.

In the embodiment of Fig. 3, it has been explained that it is possible to have data consistency by interrupting the read path from the memory cell and conducting the read path from the data input register. Thereby, for example, even when the use of a computer system is stopped, it can respond. Specifically, when the computer system is stopped, the necessary information in the memory is stored in an external large capacity nonvolatile storage device represented by a hard disk device, and then the power source is cut off. Even in this case, a read command is issued to the memory. At this time, while the write operation in the delayed write mode is performed, there may be a case where the writing of the data of the memory cell is not completed, but the read path from this memory cell is interrupted by the consistency determiner 14. By blocking and conducting the read path from the data input register, it is possible to maintain data integrity.

However, in a portable information device or the like, there may be a case where the use of the system is temporarily stopped in a state in which the memory information that is the main memory is not read by the nonvolatile external storage medium. Specifically, the resume function is a case where the power of the external memory device, the MPU, the character information display device, and the like is cut off while the information of the main memory DRAM is maintained by the refresh operation. The configuration corresponding to this is the fourth embodiment.

10 is a block diagram schematically showing an example of the configuration of a DRAM according to the fourth embodiment. As shown in FIG. 10, the DRAM according to the fourth embodiment is particularly different from the DRAM shown in FIG. 8 in that a refresh controller 15 is added.

When the refresh command is decoded by the command decoder & controller 2, the refresh controller 15 determines whether the "delay write operation" is set before this command cycle. Then, when this determination result is set to "true", that is, "delay write operation", the refresh controller 15 immediately activates the control signal generator 7 to the address held in the address register 3. Control to start a recording operation. As a result, the delay write data held in the input data register 4 is written to the memory cell. Subsequently, the normal refresh operation is started, thereby enabling the above-described resume function.

Next, specific circuit examples of the control signal generator 7, the consistency determiner 14 and the refresh controller 15 will be described.

[Control signal generator 7]

FIG. 11A is a circuit diagram illustrating an example of a circuit of the control signal generator 7.

As shown in Fig. 11A, the control signal generator 7 according to one circuit example has a control signal generator circuit 41 for a write operation and a control signal generator circuit 42 for a read operation.

The control signal generation circuit 41 for the write operation includes an input circuit 43, a shift register circuit 44, a control circuit 45 for the delay write operation, an output circuit 46, and an output control circuit 47. .

One circuit example of the input circuit 43 is the NAND gate circuit 51. The peripheral circuit activation signal ACT and the write command activation signal WCMD are input to the NAND gate circuit 51. The output of the NAND gate circuit 51 is input to the shift register circuit 44.

One circuit example of the shift register circuit 44 is six-stage shift registers 52 (52-1 to 52-6) connected in series with each other. One circuit example of the shift register 52 is shown in Fig. 11B.

As shown in Fig. 11B, the shift register 52 includes a clock-type inverter 61 whose output is controlled by a signal shift, an inverter 62 to which an output of the clock-type inverter 61 is input, and an inverter. An output of 62 is input and includes a clock type inverter 63 whose output is controlled by a signal / SHIFT 180 degrees out of phase from the signal SHIFT. The output of the clocked inverter 63 is connected to the output of the clocked inverter 61. The shift register 52 outputs the output OUT inverting the signal level of the input IN when the signal SHIFT = "HIGH" and the signal / SHIFT = "LOW". Also, when signal SHIFT = "LOW" and signal / SHIFT = "HIGH", the signal level (information) of the output OUT is maintained. The signal SHIFT corresponds to the clock CLK or clock / CLK shown in Fig. 11A.

Basically, the clock CLK synchronized with the external clock and the clock / CLK shifted 180 degrees out of phase from the clock CLK are alternately input to the six-stage shift registers 52-1 to 52-6. This is for shifting the information held in each of the shift registers 52-1 to 52-6, respectively. The timings of the clock CLK and the clock / CLK are shown in Fig. 11C.

However, the clock CLK is input to the fourth-stage shift register 52-4 after passing through the control circuit 45 for the delay write operation. This is to stop the shift operation of the shift register 52-4 during the delay write operation.

One circuit example of the control circuit 45 is a combination logic circuit of the AND gate circuit 71 and the NOR gate circuit 72. The delay write command activation signal DWCMD and the output of the fifth-stage shift register 52-5 are input to the AND gate circuit 71. The output of clock / CLK and AND gate circuit 71 is input to NOR gate circuit 72. The output of the NOR gate circuit 72 is a signal functioning as the clock CLK, and is input to the shift register 52-4 in the fourth stage. In addition, the output of the last shift register 52-6 is input to the output circuit 46.

One circuit example of the output circuit 46 is a clocked inverter 81. The output of the clocked inverter 81 is controlled by the output of the output control circuit 47.

One circuit example of the output control circuit 47 is a combination logic circuit of the AND gate circuits 91 and 92 and the NOR gate circuit 93. The signal inverting the levels of the signal WCMD and the signal DWCMD is input to the AND gate circuit 91. In addition, the signal DWCMD and the signal ACT are input to the AND gate circuit 92. The output of each of the AND gate circuits 91 and 92 is input to the NOR gate circuit 93. The output of the NOR gate circuit 93 is input to the clock type inverter 81. The clocked inverter 81 outputs the core circuit activation signal CACT in synchronization with the signal ACT when the output of the output control circuit 47 is "HIGH".

The control signal generation circuit 42 for the read operation includes an input circuit 48 and an output circuit 49.

One circuit example of the input circuit 48 is the inverter 52. The signal ACT is input to the inverter 52. The output of the inverter 52 is input to the output circuit 49.

One circuit example of the output circuit 49 is a clocked inverter 82. The output of the clocked inverter 81 is controlled by the read command activation signal RCMD. The clocked inverter 82 outputs the core circuit activation signal CACT in synchronization with the signal ACT when the signal RCMD is "HIGH".

Next, the operation will be described.

[Normal recording operation]

In the normal write operation, the signal WCMD = "HIGH", the signal DWCMD = "LOW", and the signal RCMD = "LOW".

As a result, the control signal generation circuit 41 for write operation is delayed three clock cycles from the activation of the signal ACT, thereby activating the signal CACT.

[Delay recording operation]

During the delay write operation, the signal WCMD = "HIGH", the signal DWCMD = "HIGH", and the signal RCMD = "LOW".

As a result, the shift register circuit 44 stops the shift operation at the stage 2.5 clock passes from the activation of the signal ACT. As a result, the output of the shift register 52-6 at the last stage maintains the "LOW" state. In the next write cycle, the output control circuit 47 activates the signal CACT in synchronization with the activation of the signal ACT.

[Read Action]

In the read operation, the signal WCMD = "LOW", the signal DWCMD = "LOW", and the signal RCMD = "HIGH".

As a result, the control signal generation circuit 42 for the read operation activates the signal CACT in synchronization with the activation of the signal ACT.

Consistency Checker 14

12 is a circuit diagram showing an example of a circuit of the consistency determiner 14.

As shown in FIG. 12, the consistency determiner 14 according to one circuit example includes a register circuit 101, an address comparison circuit 102, and an output circuit 103. In addition, the register circuit 101 substantially corresponds to the register circuit 33 shown in FIG. 9B, and the address comparison circuit 102 and the output circuit 103 are made of the agent shown in FIG. Corresponds almost to the two-decision circuit 32.

One circuit example of the register circuit 101 is a flip-flop circuit using a NOR gate circuit. The register circuit 101 sets the output to the "LOW" level after the delay write command is defined (DWCMD = "HIGH") and until the next write command is defined (WCMD = "HIHG"). The output of the register circuit 101 is input to the output circuit 103 via the buffer 112. One circuit example of the buffer 112 is an inverter, while the output of the register circuit 101 is at the "LOW" level, the output is brought to the "HIGH" level, and the output circuit 103 is enabled.

One circuit example of the address comparison circuit 102 is a combination logic circuit of n + 1 EX-NOR gate circuits 121-0 to 121-n and the NOR gate circuit 122. The address information ADD <0: n> from the address buffer 5 and the address information RADD <0: n> from the address register 3 are respectively input to the EX-NOR gate circuits 121-0 to 121-n. . The outputs of the EX-NOR gate circuits 121-0 to 121-n are input to the NOR gate circuit 122, respectively. The output of the NOR gate circuit 122 is input to the output circuit 103. The address comparison circuit 102 sets the output to &quot; HIGH &quot; level when the address information ADD &lt; 0: n &gt; and the address information RADD &lt;

One circuit example of the output circuit 103 is an AND circuit using the NAND gate circuit 131 and the inverter 132. The output circuit 103 activates the input data register read signal DRREAD when both the output of the buffer 112 and the output of the address comparison circuit 102 are at the "HIGH" level. By the signal DRREAD being activated, data is read from the input data register 4 rather than the memory cell.

In this way, the matching determiner 14 has completely matched the address information ADD &lt; 0: n &gt; and the address information RADD &lt; 0: n &gt; until the delayed write command is defined and until the next write command is specified. At the time, control is performed to read data from the input data register 4.

[Refresh Controller 15]

13 is a circuit diagram showing an example of a circuit of the refresh controller 15.

As shown in FIG. 13, the refresh controller 15 according to the circuit example includes a register circuit 141 and an output circuit 142.

One circuit example of the register circuit 141 is a flip-flop circuit similar to the register circuit 101 of the match determiner 14. Therefore, the register circuit 14 has its output set to the "LOW" level after the delay write command is defined (DWCMD = "HIHG"), and until the next write command is defined (WCMD = "HIGH"). do. The output of the register circuit 141 is input to the output circuit 142 through the buffer 152. One circuit example of the buffer 152 is an inverter, while the output of the register circuit 141 is at the "LOW" level, the output is brought to the "HIGH" level, and the output circuit 142 is enabled.

One circuit example of the output circuit 142 is an AND circuit using the NAND gate circuit 161 and the clock inverter 162. The output of the buffer 152 and the refresh command activation signal REFCMD are input to the NOR gate circuit 161. The output of the NOR gate circuit 161 is input to the clock type inverter 162. The output of clocked inverter 162 is controlled by signal REFCMD. The output circuit 142 activates the signal CACT when both the signal REFCMD and the output of the buffer 152 are at the "HIGH" level. By activating the signal CACT, the core circuit is activated to perform a write operation to the memory cell.

In this manner, the refresh controller 15 activates the signal CACT immediately after the start of the refresh operation when the refresh command activation signal REFCMD is specified after the delay write command is defined and until the next write command is specified. The write operation to the memory cell is controlled.

As mentioned above, although this invention was demonstrated by four embodiment, this invention is not limited to the above-mentioned four embodiment, It can implement in a various deformation | transformation in the range which does not deviate from the summary of this invention.

In addition, although the prior art and the embodiment of the invention have been described particularly with respect to DRAM, the present invention sets WL and RL to the same clock cycle value, and in particular, delays the start timing of the write operation inside the chip compared to the read operation. It is also applicable to other memories such as FRAM and PROM using the method.

According to the present invention, there is provided a semiconductor integrated circuit device having a memory unit capable of reading information from a memory cell in response to a read command and writing information into the memory cell in response to a write command. It is possible to provide a semiconductor memory device having a high added value that can achieve high data transfer efficiency in either of the operation and the continuous read / write operation.

Claims (20)

In a semiconductor memory device, A read operation for reading information from the memory cell in accordance with a read command among a plurality of commands set in synchronization with an external clock, the memory cell array including a plurality of memory cells integrated and arranged in a matrix; A memory unit capable of each of writing operations for writing information in the memory cells according to a command; And A controller for initiating an access operation to the memory unit, wherein the controller is configured to perform a first delay time from setting of the read command to confirming read data, and from preparing the write command to preparing valid write data. When the delay time is set to the same clock cycle value, the access operation is started at different timings in the read operation and the write operation. And a semiconductor memory device. 2. The semiconductor memory device according to claim 1, wherein the access operation start timing at the write operation is delayed at least one clock cycle or more than the access operation start timing at the read operation. The semiconductor memory according to claim 2, wherein a difference between the access operation start timing at the write operation and the access operation start timing at the read operation is equal to or longer than a cycle time of the memory section. Device. The semiconductor memory device according to claim 1, wherein the access operation start timing is a timing at which a sequence of sequences starting from a procedure of activating a word line is started. The semiconductor memory device according to claim 1, wherein the memory cell is a one-capacitor-transistor-type dynamic memory cell. 6. The semiconductor memory device according to claim 5, wherein the memory unit including the dynamic memory cell does not have a page cycle function. In a semiconductor memory device, A read operation for reading information from the memory cell in accordance with a read command among a plurality of commands set in synchronization with an external clock, the memory cell array including a plurality of memory cells integrated and arranged in a matrix; A memory unit capable of each of writing operations for writing information in the memory cells according to a command; And A controller for initiating an access operation to the memory section, the controller further comprising a first delay time from the setting of the read command until the read data is confirmed, and from the setting of the write command to preparing valid write data; When the second delay time is set to the same clock cycle value, a first write operation mode in which information writing to a memory cell is completed within a write operation command cycle in which the write command is set, and in a write operation command cycle in which the write command is set; Sets one or both of the second write operation modes in which information writing to the memory cell is not completed. And a semiconductor memory device. 8. The semiconductor memory device according to claim 7, wherein the write operation in which the second write operation mode is set starts immediately after the reception of the next write command cycle. The semiconductor memory device according to claim 7, wherein the first and second write operation modes are set by a signal input to a control pin which is an external terminal. 8. The semiconductor memory device according to claim 7, wherein the first and second write operation modes are set by a mode register setting cycle. 10. The apparatus of claim 9, further comprising decryption control means for decrypting the plurality of commands and controlling the memory unit according to the decrypted result, And said decoding control means includes a function of detecting whether it is said first write mode or said second write mode. 12. The semiconductor memory device according to claim 11, wherein the readout control means includes a detection circuit that detects whether the first write operation mode or the second write operation mode is present. 12. The apparatus of claim 11, further comprising control signal generating means controlled by said decryption control means, The decryption control means includes first control means for setting the first recording operation mode, second control means for setting the second recording operation mode, and the first control when the first recording operation mode is detected. And means for coupling the means to the control signal generating means and for coupling the second control means to the control signal generating means when the second write mode of operation is detected. 15. The apparatus of claim 13, wherein the readout control means combines the first control means with the control signal generating means when the first write operation mode is detected, and when the second write operation mode is detected. And a switching circuit for coupling the control means to the control signal generating means. 8. The apparatus of claim 7, further comprising a first register for holding write information, and a second register for holding address information of an address to be written, And the first and second registers are respectively activated when the second write operation mode is set. 17. The read information from the memory cell is interrupted when the read command requesting access to the address at which the second write mode is set is continued following the second write operation mode. And switching means for conducting a read path from the first register circuit for holding the circuit. 17. The apparatus according to claim 16, wherein the function of determining whether or not the read command continues to the second write operation mode, and whether or not an address to which access is requested by the read command is an address for which the second write mode is set. Further comprising a consistency determiner comprising a function to determine, And said switching means is controlled by said matching determiner. 18. The apparatus of claim 17, wherein the consistency determiner determines a first circuit to determine whether the read command continues to the second write mode of operation; And a second circuit for determining whether or not the address for which access by the read command is requested is an address for which the second write mode is set. 19. The semiconductor memory device according to claim 18, wherein the first circuit includes a register set when the second write operation mode is set and reset when the first write operation mode is set. 8. The method according to claim 7, wherein when the second write mode is set, the write operation to the memory cell corresponding to the address at which the second write mode is set is performed immediately after receipt of the next write command and immediately after receipt of the next refresh command. Disclosed in any one of the semiconductor memory device.