KR20000016640A - Device and method for multi-level charge/storage and reading out - Google Patents

Abstract

A memory device having a memory cell capable of storing three or more charge levels is disclosed. The cell is programmed according to a single pulse charge level injection mechanism. This method does not require a program verification design, increases the speed during the program, and reduces the area required to store 1-bit information. The memory device further includes information writing (storing or program) means, information deleting means, and information reading means. Also provided are methods and circuits that implement this method of determining the charge level of a memory cell having a t (t equal to or greater than 3) possible level. The circuit measures the similarity of the memory cell drain current and the drain current of each of the n references to determine one reference that is most similar to the memory cell, thereby identifying the charge level of the memory cell.

Description

Multi-level charge storage device and method and reading device and method thereof

Nonvolatile semiconductor memory devices are an important field of semiconductor memory devices. One special type of inactive semiconductor memory device is a flash EEPROM device. The main mechanism by which data is stored in inactive memory devices is access to memory cells. The demands of high density flash EEPROM memory devices in portable computing and communications applications provoke ongoing efforts in shrinking flash EEPROM memory cell sizes. In order to further increase the storage capacity of flash memory devices, multi-level charge storage (MLCS) technology has been developed. This technique can reduce the cost per bit of information in flash EEPROM nonvolatile memory devices.

In general, an MLCS memory device is configured such that 2 ⁿ different charge levels corresponding to threshold voltage levels can be stored in one memory cell, and current corresponding to these other threshold voltage levels can be read. As such, the storage and reading of n-bit (n is 2 or more) data may be performed in a single memory cell. For MLCS technology, the cost per information bit is reduced to 1 / n.

Multi-level storage (write or program) circuits and techniques, and read circuits and techniques are disclosed. Harrier's US Pat. No. 5,043,940 discloses a split channel EEPROM device that can be programmed to two or more programmable threshold states. US Patent No. 4,771,404 to Mano et al. Discloses a memory device having a memory cell capable of storing three or more pieces of information. The memory device has a multi-level detector for detecting the information of the memory cells at one time and a reference generator for generating a reference level. U. S. Patent No. 5,163, 021 to Merotra et al. Discloses improvements in circuitry and techniques for reading, writing, and erasing multi-state EEPROM memory devices, which circuits provide a threshold level provided with a corresponding set of reference cells. Read in relation to the set. U.S. Patent No. 4,415,992 discloses a readout structure for identifying n charge levels of a memory cell, wherein (n-1) comparators and (n-1) voltage references are used in parallel to determine the charge level of the memory cell. Decide Additional decoding logic is needed to convert the output of the comparator to bits. All (2n-1) different voltage amplitudes are needed and must also be implemented on the chip. Other multilevel storage memory devices and programming methods are disclosed in WO 95/34074, US Pat. No. 5,422,845, and WO 95/34075.

A problem of the memory device shown in the prior art is that it performs a bit-by-bit program verification procedure in operation. This procedure has an optional relationship between storage level accuracy and program speed. As a result, program operation becomes slow. In addition, the chip implementation of the verification procedure increases the chip dimension. In addition, the memory devices disclosed in the prior art utilize read circuits based on a number of comparators and decoding logic, which not only increases the complexity of the memory device but also increases the chip dimensions.

Prior art memory cells for multi-level charge storage use programming methods based on Fowler Nordheim Tunneling (FNT) or Channel Hot Electron (CHE) injection. The prior art multi-level programming method utilizes a 'program checking structure' comprising the following common steps:

(1) a programming pulse, typically having a duration of 100 microseconds to 1 millisecond, is applied to the memory cell being programmed;

(2) the drain current of the memory cell to be programmed is sensed and applied to the comparator, where the current of the reference current source corresponding to one of the multi-level charge levels to which the cell is to be programmed is also applied;

(3) When the current of the memory cell and the current of the reference current source coincide, the cell is in a corrected state and no further programming is necessary. However, if the currents do not match, steps (1) and (2) are repeated.

Prior art programming methods do not disclose an MLCS method characterized by the high speed programming and small chip size required to implement a memory device. The prior art programming method requires several iterations of the programming steps and a sensing step to correctly program the cell to the intended charge level after each step, which significantly impairs the speed of the overall program operation. In addition, the speed is a function of the specific charge level to be programmed. This problem significantly reduces the data throughput of the memory device. The second problem is related to silicon area consumption, and the use of silicon in the 'program verification structure' increases chip size.

The present invention relates to an inactive memory device for multilevel charge storage, and more particularly to a device and method for multi-level charge storage and to an apparatus and method for reading such a device.

1 is a memory cell in accordance with a preferred embodiment of the present invention;

2 is an array of memory cells in accordance with a preferred embodiment of the present invention;

3 is a diagram illustrating a threshold voltage and a read current of a cell programmed according to the voltage variable source side injection method of the present invention;

4 is a programming characteristic of voltage variable source side injection;

5 is a state of the read architecture;

6 is an operating principle of a read architecture in accordance with a preferred embodiment of the present invention;

7 is a block diagram of a read architecture in accordance with a preferred embodiment of the present invention;

FIG. 8 is a configuration diagram of the subcircuits 400, 401, 402, and 403 of FIG. 7;

9 is a configuration diagram of the subcircuit 500 of FIG. 7;

10 is a detailed layout of a read architecture in accordance with a preferred embodiment of the present invention;

11 shows experimental results of sub-circuits 400, 401, 402 and 403; And

12 shows experimental results of a read architecture according to a preferred embodiment of the present invention.

It is an object of the present invention to disclose a memory device having a memory cell capable of storing three or more charge levels in the memory cell. The memory cell can be programmed according to a method comprising a single pulse charge level injection mechanism in the cell. This method does not require a charge level checking scheme, increases program speed, and reduces the space needed to store one bit of information. The speed of the programming mechanism is at least two orders of magnitude faster than other multi-level programming mechanisms disclosed in the prior art. The memory device of the present invention further has information writing or information storing or information program means, information deleting means, and information reading means. It will be appreciated later that the term write or store or program refers to the same method or circuit or means.

It is another object of the present invention to provide a method, apparatus and circuit for implementing the aforementioned method for reading the charge level of a memory cell having t possible states (t is 3 or more). The circuit determines the charge level of the memory cell by measuring the similarity between the drain current of the memory cell and each drain current of the m references stored in the dummy cell to determine the one reference closest to the memory cell.

A first example of the present invention discloses a memory device for multi-level charge storage. The memory device includes a plurality of flash EEPROM memory cells, further comprising means for programming a charge level and reading means for outputting binary data in parallel corresponding to the charge level stored in the cell. The memory cell of the memory device has a source region, a drain region and a channel region in the semiconductor substrate. The memory cell further includes a floating gate, the floating gate including first and second floating gate portions, the first floating gate portion extending over the channel region, and the second floating gate portion extending away from the channel region. The memory cell includes a program gate and a control gate, and the program gate forms a capacitor with the second floating gate portion. The programming means of the memory device comprises means for applying a high voltage pulse having a predetermined amplitude and a fixed time width selected from the plurality of predetermined amplitudes to the cell. The predetermined amplitude determines the charge level. The charge level matches the other threshold voltage level of one memory cell. Memory cells of a memory device are arranged in an array having rows and columns, with drains of cells belonging to the same column connected to each other to form data output lines, and program gates of cells belonging to the same column connected to each other to input data Form a line. Control gates of cells belonging to the same row are connected to each other to form a word line.

A second example of the present invention discloses a method of storing one of a plurality of charge levels in a memory cell. The memory cell includes a source region, a drain region, a channel region, and a floating gate, wherein the floating gate includes first and second floating gate portions, the first floating gate portion extends over the channel region, and the second floating gate portion is a channel region. Extending away from the memory cell further includes a program gate and a control gate, the program gate forming a capacitor with the second floating gate portion. The method includes applying a low voltage to the control gate; Applying a voltage of 5 volts or less to the drain region; And applying to the program gate a high voltage pulse having a predetermined amplitude and a fixed time width selected from among the predetermined amplitudes determining the charge level. In addition, the method further includes capacitively coupling the high voltage pulse to the second floating gate portion to inject thermal electrons into the floating gate such that one of the plurality of charge levels is stored in the memory cell.

A third example of the present invention discloses a method of equalizing the field stress induced by programming memory cells to different charge levels in an array of memory devices. The method includes applying a low voltage to the control gate of each of the memory cells of the array; Applying a voltage of 5 volts or less to the drain region of each of the memory cells of the array; And applying a high voltage pulse having a predetermined amplitude and a fixed time width to a program gate of each cell of the array; Thereafter, deleting the cell.

A fourth example of the present invention discloses a method of reading the charge level of a memory cell of a memory device. The method includes sensing a drain current of the memory cell; Sensing drain current of the plurality of dummy cells; Measuring the similarity between the drain current of the memory cell and the drain current of the plurality of dummy cells to obtain a plurality of intermediate voltages representing the similarity; Determining the highest voltage among the intermediate voltages to identify a dummy cell having a drain current closest to the drain current of the memory cell; And setting a predetermined voltage to an output terminal corresponding to the dummy cell identified in the checking step.

A fifth example of the present invention discloses an apparatus or circuit for reading the charge level of a memory cell. The apparatus comprises a plurality of dummy cells carrying a plurality of reference currents; Means for reading a reference current and a memory cell current; A plurality of analog circuits measuring a similarity between the current of the memory cell and each reference current, and outputting a plurality of intermediate voltages representing the similarity; And a decision circuit for determining a dummy cell having a drain current closest to the drain current of the memory cell by determining the highest voltage among the intermediate voltages, and setting a predetermined voltage at an output terminal corresponding to the determined dummy cell.

It is an object of the present invention to disclose a memory device having a memory cell capable of storing three or more charge levels. The cell can be programmed according to a method comprising a single charge level injection mechanism in the cell. This method does not require a program verification structure, increases the program speed, and reduces the area required to store one bit of information. The speed of the programming mechanism is at least two orders of magnitude faster than other multi-level programming mechanisms disclosed in the prior art. The memory device of the present invention further includes information writing means, information deleting means and information reading means.

For purposes of the disclosure, the implementation of the memory device and the method of storing data in the memory device disclose for the case where n = 2 for the case where 2 ⁿ different threshold voltage levels can be stored. According to the present disclosure, other embodiments may be implemented by those skilled in the art for the case of n> 2, and the scope of the present invention is determined by the appended claims.

1 illustrates a memory cell of a memory device according to a preferred embodiment of the present invention. The memory cell is a flash EEPROM cell structure implemented in a silicon substrate and has a source region 1, a drain region 2, and a channel region 3 therebetween. The memory cell has a floating gate 4. The floating gate has first and second floating gate portions, the first floating gate portion extending over the channel region 3 with a thin film oxide layer therebetween, and the second floating gate portion extending away from the channel region. The memory cell has a program gate 6 and a control gate 5. The program gate 6 forms a capacitor with the second floating gate portion, and the control gate extends over the first floating gate portion. The program gate 6 forms a capacitor with the floating gate 4 with a coupling ratio of at least about 50%. The dielectric layer is present between the program gate and the floating gate, and between the control gate and the floating gate. The structure of memory cells and possible programming mechanisms are described in detail in US Pat. No. 5,583,811, US Pat. No. 5,583,810, and European Patent No. 0,501,941. The disclosures thereof are cited here. This memory cell can be implemented in CMOS silicon technology of 3 μm, 1.2 μm, 0.7 μm, 0.5 μm, 0.35 μm, 0.25 μm, 0.18 μm, or 0.12 μm, or in other CMOS technologies with the layout rules and characteristic dimensions of transistors. Can be. A memory cell according to a preferred embodiment of the present invention may have a floating gate 4, a program gate 6, and a control gate 5 of polysilicon material when implemented in a 0.7 μm CMOS technology. The dielectric layer is an oxide layer having a thickness of 25-30 nm. The thin film oxide layer has a thickness of 7-9 nm. The floating gate length and the control gate length are 0.7 mu m and the width of the memory cell is 1.8 mu m.

The memory device includes an array of cells as described above above. 2 shows a configuration of an array 11 according to an embodiment of the present invention. The array is the geometry of the EEPROM cells 10 each addressable as described above. The memory cell has a control gate 4, a program gate 6, a drain gate 2, and a source region 1. The source 1 of all cells in the array is grounded and therefore not shown in FIG. 2. The memory array 11 is arranged in m rows and z columns. Each cell belongs to only one column and one row. The last four cells of each row are dummy cells and are used as a reference during a read operation of the memory device. Along each row, a word line is connected to all control gates 5 of the cell in the row. Along each column, an output bit line is connected to all drains 2 of the cell. The input bit line is connected to every program gate 6 of the cell in the column. The program gate 6 is routed in the same direction as the drain region 2. The control gate 5 is routed perpendicular to the direction determined by one of the program gates and the drain. The program gate must be routed in parallel to the drain region in the multilevel array. On the other hand, in a binary array, the program gate must be routed horizontally. In the voltage-variable source-side injection (VVSSI) multilevel programming method disclosed herein, the data programmed into the cell is applied to the program gate and the data read from the cell is sensed from the drain, so that the drain and program gate of the cell are individually programmed and It must be routed in the same direction to enable reading. There are two bit lines in this multilevel flash EEPROM array. The output bitline is used to read the charge storage level from the cell and the input bitline is used to program the charge storage level into the cell.

A first example of the invention relates to a method of storing one of a plurality of charge levels in a memory cell. The difference between the conventional multilevel charge storage memory cell and the memory cell structure of the present invention is that the conventional memory cell requires a programming structure based on Fowler Nordheim Tunneling (FNT) or Channel Hot Electron (CHE) injection. Voltage Variant Source Side Injection (VVSSI) programming method is used. This new programming method is based on the source side injection (SSI) programming method of memory cells. Each of the multilevel charge storage levels corresponds to a particular threshold voltage stored in the floating gate 4 of the EEPROM memory cell. The threshold voltage of the memory cell is defined as the voltage to be applied to the program gate 6 to obtain a drain current of 1 mA at a fixed control gate voltage and drain region voltage. This definition differs from other inactive memory cells in which the threshold voltage of the device is defined at the control gate.

The SSI program method applies a high voltage to the program gate 6, capacitively couples the high voltage to the floating gate 4, applies a low voltage to the control gate 5 and applies a voltage of 5 volts or less to the drain region. This allows very high hot electrons to be injected into the floating gate 4 during programming of the memory cell. VVSSI multilevel charge level programming includes applying a single programming pulse (V _PG ) to the cell's program gate 6, where the drain region 2 and the control gate 4 are constant according to the conditions of Table 1. Are maintained at bias V _D and V _CG . The programming pulse applied to the program gate 6 of the memory cell has a width T of about 1 microsecond regardless of the charge level being programmed, while the amplitude is related to the charge level being programmed. The amplitude of the programming pulse is given in volts (V).

level V _CG (V) V _PG (V) V _D (V) T VVSSI 1230 1.51.51.51.5 7.08.012.00.0 5.05.05.05.0 1.0 ㎲1.0 ㎲1.0 ㎲1.0 ㎲ Reading all 4.0 0.0 2.0

Table 1: Operating conditions of the multi-level charge storage program method according to a preferred embodiment of the present invention.

The values given in Table 1 relate to the implementation of the memory cell of the preferred embodiment in a 0.7 μm CMOS technology. As shown in Table 1, the V _D (i.e. 5 volts) value is the power supply voltage value of the 0.7 μm CMOS technology. If the power supply voltage is reduced for the other CMOS technologies described above (e.g. 3.3 volts in 0.35 um CMOS technology), the other voltage values shown in Table 1 should be changed as follows. V _D is reduced to the power supply voltage, other V _PG voltages are reduced as elimination by almost twice the amount that the power supply is reduced, and V _CG is 0.5-1.3 volts. V _CG for 0.7 μm CMOS technology may range from 1.5 to 1 volt or lower. For example, for a supply voltage of 5 to 3.3 volts, V _D is 3.3 volts for different charge storage levels, and V _PG is about 9 volts, 6 volts, 5 volts and 0 volts. For 0.7 μm CMOS technology, the V _PG voltage shown in Table 1 may vary. Programming voltage sets such as 10 volts, 8 volts, 6 volts and 0 volts can be used for other charge storage levels. The set of programming voltages given in Table 1 is a compromise between programming speed requirements and the accuracy of the programmed charge levels. Taking the pulse width of one or more microseconds of programming pulses (V _PG ) causes all levels to be taken in the saturation region of each programming characteristic. Therefore, a pulse width of 1 microsecond is appropriate for VVSSI. The programming characteristic of a memory cell is defined as the shift of the threshold voltage of the memory cell relative to the programming time. As far as the time span of a pulse is concerned, it is almost the same as shrinking CMOS technology and power supplies. This is one obvious advantage. This is because the next generation VVSSI based on EEPROM memory devices is small in area but not slow in speed compared to the embodiment in the 0.7 μm CMOS technology.

The method of storing one of a plurality of charge levels in a memory cell utilizes one one microsecond programming pulse and does not require a program verification structure to verify the accuracy of the programmed charge storage level. It details the performance of program performance, information identification, and persistence characteristics. The speed of the program mechanism is conventional, for example, as in M. Ohkawa et al. "98 mm2 64 Mb flash memory with FN-NOR type four-level cells" (ISSCC 96, TP 2.3, pg.36). It is at least two orders of magnitude faster than other multi-level programming mechanisms based on the FNT disclosed in the art. The main advantage of VVSSI over CHE is a much larger current window.

Forty EEPROM memory cells fabricated from 6-inch silicon wafers in 0.7 μm CMOS technology are programmed to four levels according to the conditions mentioned in Table 1. This level of dispersion is measured with threshold voltage V _T and read current I _D , and is shown in FIG. 3. 3 shows the mean value X and the standard deviation s for each variance. The cell is measured according to the read conditions shown in Table 1. It is obvious that the variance is narrow and separated from each other. As such, the method of storing one of a plurality of charge levels in accordance with the present invention does not require a program verification structure to verify the accuracy of the programmed charge storage level.

The advantage of programming pulses of the same time width but different amplitudes is that the pulse width can be selected in such a way that all levels are located in the same region of each programming characteristic. In fact, in this particular case, one microsecond is the minimum time required for all levels to be terminated in the saturation region of the transient characteristic as can be understood in FIG. 4.

In order to program the EEPROM memory cells according to the MLCS method of the present invention, the memory cells are deleted beforehand. Level 0 mentioned in Table 1 is an erased state of an EEPROM memory cell according to a preferred embodiment of the present invention. On the other hand, the VVSSI programming pulse according to the logic levels 1, 2 and 3 of Table 1 shifts the threshold voltage of the floating gate of the memory cell by injecting an amount of charge proportional to the amplitude of the programming pulse into the floating gate, while level (0) Programming pulse does not shift the threshold voltage because the amplitude of the pulse is zero. In order to delete an EEPROM memory cell according to a preferred embodiment of the present invention, a method comprising the following two steps is introduced:

(1) A pre-erase programming pulse is applied to an EEPROM memory cell according to a preferred embodiment of the present invention.

(2) The erase pulse is applied to the EEPROM memory cell. The erase pulse can be applied in other ways.

First, a method of applying a pre-erase pulse will be described. In order to minimize the effects of circulation, the field induced stress of the device should be kept as uniform as possible. Unfortunately in multilevel memory devices, this stress is a function of the data stored in the device. For example, the stress produced in a memory cell programmed 10 times in level 3 is much higher than the stress in other memory cells programmed 9 in level 0 and 1 in level 1. This uneven nature of stress results in an unexpected shift in read current, which greatly impairs the charge storage level identification capability of the memory device. This problem can be overcome by applying an additional write pulse prior to the erase operation. As can be understood from the instantaneous nature of the SSI shown in Figure 4, the highest voltage (12 volts) 10 microsecond pre-erase programming pulse puts all devices into the same state (V _T ) prior to the erase operation. This is independent of the initial V _T stored in the cell.

Second, a method of applying an erase pulse to an EEPROM memory device is described. The following options can be selected. Deletion can be done in other ways:

1) The Fowler-Nordheim tunneling of electrons from the floating gate to the drain junction is activated by applying a negative high voltage (-10 to -12 volts) to the floating gate, while the supply voltage (5 volts) is applied to the drain. In this erase mode, the control gate remains grounded, to maximize the tunneling field at drain to floating gate overlap. The potential applied to the source junction is not critical during deletion.

2) If the word lines and program lines of the memory device sector are connected during erase, a lower gate voltage is sufficient (usually -7 to -8 volts). Parasitic control gate to floating gate capacitance is used to further enhance the electric field across the tunnel oxide. In this case, the erasing mechanism is essentially the same as in the previous case, but the required negative voltage is lowered at the expense of additional switching circuitry.

3) Another possible deletion scheme is provided by the channel deletion mechanism. In this case, a negative voltage is applied to the program line, which in turn is coupled with the supply voltage to the substrate (or p-well) of the memory array. In this case, a uniform erase current is obtained in the tunnel oxide region which is beneficial in terms of oxide stress and programming window closure after the write / erase cycle. The main advantage of this structure is that there is no band-to-band tunneling current from the drain junction to the substrate or well.

4) Another possible erasure mechanism is polyoxide induction from the floating gate to the control gate, which can be achieved by applying a positive high voltage to the control gate. This is possible without any change to the cell design. Such a deletion structure is also disclosed in US Pat. No. 5,583,810.

Possible deletion modes are summarized in Table 2.

sauce drain Control gate Programmable gate Substrate or p-well writing 0 V 3.3V / 5V 1V / 1.5V 12 V 0 V Delete tunnel - 3.3V / 5V 0 V -12V 0 V Delete tunnel (alternative) - 3.3V / 5V -7V -7V 0 V Delete channel 3.3V / 5V 3.3V / 5V 0 V -12V 3.3V / 5V Delete channel (alternative) 3.3V / 5V 3.3V / 5V -7V -7V 3.3V / 5V Polyoxide Deletion - 0 V 12 V 0 V 0 V

Table 2: Typical Operating Voltages for Memory Cells in SSI Write and Other Erase Modes

Read architecture

Conventional multi-level memory devices rely on a parallel architecture for reading information stored in memory cells similar to that of FIG. The memory cell read current I _C is compared in parallel with the three reference currents, which is selected as the average of the currents corresponding to two adjacent logic levels. Each comparator 37 produces a binary output which is fed to a decoder 38 from which two bits of information are obtained. Due to the significant area cost of comparator 37, this architecture excessively increases the perimeter of the memory device. In fact, while the comparator used to distinguish between zeros and ones is simple and small in binary memory (1 bit resolution), comparators in MLCS memory devices that need to be more accurate (8 bit resolution) take up a significant area. In addition, this architecture ensures that the read current corresponding to level (i) is always greater than reference (i) and less than reference (i-1), regardless of wafer dispersion for read currents, process variables, disturbances and circulation. It is based on the home. Otherwise, the comparator is switched, which leads to an error in verifying the stored charge level. Such assumptions are only made if programming is made using program verification techniques. Since the VVSSI program method is suitable for not using program verification, a newly designed architecture has been developed.

In order to minimize the effects of processing variables and circulation, four dummy cells D0, D1, D2 and D3 are provided in each row of the memory array described above. These dummy cells are programmed at levels 0, 1, 2 and 3, respectively, as described in Table 1 and used as reference during the read operation.

When memory cell 10 is being read, its read current and the current of dummy cells D0, D1, D2 and D3 in that row are sensed in parallel. Methods of implementing the sensing device are known. The read current I _dc of the memory cell is compared with each of the currents I _dx of the dummy cell to determine which of the four charge storage levels (0, 1, 2 and 3) it belongs to. Dedicated circuitry is used to perform these comparisons in parallel to reduce access time. The circuit operating principle and block diagram are shown in FIGS. 6 and 7, respectively. In order to realize the multilevel signal comparison, the difference between each of the read current and the dummy cell current is measured by the four subcircuits 400, 401, 402 and 403 of FIG. 7. Each of these produces an intermediate output voltage that is proportional to the similarity of the measured currents. This intermediate output voltage is labeled with a Matching-Score signal MS. Four MSs are supplied to the second stage 500 of the circuit of FIG. This sub-block 500 determines which of the four MSs is the highest to bring the corresponding output terminals 600, 601, 602 or 603 into a high digital state, while the other three outputs remain in a low digital state. Will be. The high digital state is the same voltage as the power supply voltage, while the low digital state is ground.

As an example, the subcircuit 400 is described below. The other subcircuits 401, 402 and 403 are similar to the subcircuit 400. The sub circuits 400, 401, 402 and 403 receive two current input signals I _c and I _x and transmit an intermediate voltage output signal V _MS proportional to the similarity between the two input currents. In other words, the smaller the Euclidean difference between the currents in this example of the invention, the higher the V _MS . One-dimensional Euclidean differences known in the art are represented by the following;

(One)

Where R and L are two general one-dimensional vectors, and V _MS is a monotonically increasing function of Dist. To implement equation (1) in silicon, the inherent square law of the long channel MOSFET at saturation is used:

V _TM ≒ K (V _G -V _S -V _T ) ²

The application of the voltage signal R to the gate of the MOS is a well known technique. However, in order to apply voltage L to the source, the second MOSFET in the source follower configuration must be connected to the source of the driving n-MOS device. In this way, equation (RL) ² is implemented. The resulting current I _M is applied to the p-MOS device in a diode configuration that implements the square root function.

This consideration leads to the subcircuit of FIG. 8, which includes a pair of first drive MOS transistors with respective source followers 45 and 42 and two drive n comprising a pair of second MOS transistors. MOS devices 43 and 44, a diode connected to the p-MOS device 47 comprising a third MOS transistor and two current-to-voltage converter n-MOS devices 46 and 41.

One electrode of each of the second MOS transistors, that is, the source or the drain, is connected to one electrode of the first driving MOS transistor, that is, the source or the drain. Thus, one of the first driving MOS transistors is connected to one of the second MOS transistors. Gates of the first driving MOS transistor and the second MOS transistor are connected in a cross shape. A gate of each of the first driving MOS transistors is connected to one gate of the second MOS transistor, and the second MOS transistor is one that is not connected to one electrode of the first driving MOS transistor. The third MOS transistor is connected to another electrode of the first driving MOS transistor, that is, a source or a drain, and the other electrodes described above of the first driving MOS transistor are connected.

The dimensions of the transistors are given in the figure. 42 and 45 have an aspect ratio (W / L) of 5 to 50 times that of 43 and 44 because they are the source follower transistors used to bias the source of the drive transistors. However, the wider the source follower for the drive transistor, the more accurately the source follows the gate. The simulation shows that a good compromise between accuracy and area consumption is factor 10.

Transistors 46 and 41 convert I _C and I _X into V _C and V _D , respectively. If I _C is greater than I _X , 44 is cut off because the source voltage V _C is higher than the gate voltage V _D. However, 43 is on and the greater the difference between V _C and V _D, the larger the drain current and the smaller V _MS . Conversely, if I _C is less than I _X , 43 is cut off and 44 is on.

9 shows a proposed subcircuit 500 in accordance with one embodiment of the present invention, which comprises four current n-MOS conveyors 50, 51, 52 and 53 and four current comparators (comprising transistors). 56, 57, 58, and 59). The sub-circuit receives four V _MSs from the dummy cells D0, D1, D2 and D3 as input signals at the gate of the current conveyor and delivers four binary output signals. The current conveyor has a source node X in common and is biased with the same biasing current I _B. When V _MS is applied to the gate of the conveyor, node X follows the largest input voltage and blocks the other three conveyors: the biasing current flows only through the conveyor with the largest V _MS . Only the conveyor with the largest V _MS drives the current, while the other three conveyors do not. The drain of each conveyor is connected to the drain of transistor 54 of the current comparator located above the conveyor. A current comparator implemented according to the prior art compares the current from the conveyor with the bias current I _B / 2. If the current from the conveyor is greater than I _B / 2, the output of the comparator goes high. In contrast, when the current from the conveyor is smaller than the bias current I _B / 2, the output of the comparator is low. Since current I _B flows almost entirely on one and only one of the conveyors, only one of the current comparators sets themselves to a high digital state, while the other three current comparators set their outputs to a low digital state. do.

As shown in FIG. 10, the circuit is integrated in a standard double-polysilicon double-metal 0.7 μm process in the silicon region of only 140 × 100 μm ² and has been widely evaluated. The silicon area for implementing a single 8-bit comparator is estimated to be approximately 70 × 50 μm ² . Since three comparators are needed, the typical architecture of FIG. 5 occupies at least 210 × 150 μm ² and has a level identification block that is nearly 2.3 times larger than that proposed in the present invention. For power consumption over the same area, they show a significant propagation delay. However, in the circuit proposed here, it is possible to significantly reduce the propagation delay by only increasing the circuit biasing current. The increase in biasing current is not so simple in standard comparators leading to greater offset voltages and lower accuracy. Read speed and level checking circuits significantly affect the data throughput of the memory. This is because the program verification structure is usually used in MLCS.

FIG. 11 shows V _MS experimentally evaluated as a function of swept cell current at a reference current of 25 mA. As expected, the higher the current, the higher the V _MS . 12 experimentally shows the output voltage of the readout circuit as a function of the swept cell current at reference currents of 30, 80, 120 and 160 mA. Only one output voltage is high for any given cell current value.

Every time a memory device is flash erased. For example, prior to a write operation, dummy cells belonging to that particular sector are also deleted and reprogrammed to the reference level. This technique allows both dummy and memory cells to have the same duty cycle, thus achieving the same current shift. This means that there is no overall shift due to cycling when comparing the dummy and memory cells during readout. Iterating the dummy cells on each wordline eliminates other influences that play an important role in high density memory: drain resistance effects. Due to the resistive nature of the drain line, there is a difference in the read current of the cells belonging to the same column. This difference, although negligible for memory cells that are adjacent to each other, becomes quite large for distant cells and therefore should not be considered unless the dummy cell is in the same row as the cell being read out. In terms of the silicon area of such architecture, the additional cost is very limited since it consists of only four cells per wordline.

Claims (18)

A memory device for use in multi-level charge storage, A floating gate comprising a source region, a drain region, a channel region, and first and second floating gate portions, wherein the first floating gate portion extends over the channel region and the second floating gate portion extends away from the channel region. And a plurality of flash EEPROM memory cells including a program gate forming a capacitor with the second floating gate portion, and a control gate; Reading means for parallel outputting binary data according to the charge level stored in the cell; And And programming means for applying a high voltage pulse having a predetermined amplitude and a fixed time width selected from the plurality of predetermined amplitudes to determine the charge level to the cell. The memory device of claim 1, wherein the plurality of memory cells are arranged in an array having rows and columns, A drain of cells belonging to the same column connected to form a data output line; A program gate of cells belonging to the same column connected to form a data input line; And And a control gate of a cell connected to belong to the same row to form a word line. 3. The apparatus of claim 2, wherein the data input line and the data output line are parallel and routed in the same direction; And the word line is routed in a direction perpendicular to the direction of the data input line and the data output line. 4. The memory device of claim 3, wherein the array further comprises a dummy cell on each row of the array that provides a reference current in a read operation. A source region, a drain region, a channel region, and a floating gate, wherein the floating gate includes first and second floating gate portions, the first floating gate portion extends over the channel region, and the second floating gate portion is Extend away from the channel region; Further comprising a program gate and a control gate, wherein the program gate forms a capacitor with the second floating gate portion, the method for storing one of a plurality of charge levels in a memory cell of a memory device for multi-level charge storage. , Applying a low voltage to the control gate; Applying a voltage of 5 volts or less to the drain region; And And applying a high voltage pulse having a predetermined amplitude and a fixed time width selected from among the predetermined amplitudes to determine the charge level to the program gate. 6. The method of claim 5, further comprising deleting the cell, and then performing the step of claim 4. 7. The method of claim 6, wherein the memory cells are deleted respectively, and the memory cell erasing step includes: Applying a low voltage to the control gate of each of the cells of the array; Applying a voltage of 5 volts or less to the drain region of each of the cells of the array; And Applying a high voltage pulse having a predetermined amplitude and a fixed time width to the program gate of each of the cells of the array; Then, the charge level storage method, characterized in that to perform the step of claim 6. 6. The method of claim 5, wherein the high voltage pulse is capacitively coupled to the second floating gate portion, and charge level is stored in the memory cell by injecting hot electrons into the floating gate. 9. The memory cell of claim 8, wherein the memory cell employs a 0.7 micron CMOS technology, wherein the low voltage is less than 1.5 volts, the high voltage pulse is selected from 12 volts, 8 volts, or 7 volts, with a width of about 0 volts. Charge level storage method characterized in that the microseconds. A source region, a drain region, a channel region, and a floating gate, wherein the floating gate includes first and second floating gate portions, the first floating gate portion extends over the channel region, and the second floating gate portion is Extend away from the channel region; A method of reading a charge level of a memory cell of a memory device, the method comprising: a program gate and a control gate, wherein the program gate forms a capacitor with the second floating gate portion. Sensing a drain current of the memory cell; Sensing drain current of the plurality of dummy cells; Measuring a similarity between the drain current of the memory cell and the drain current of the plurality of dummy cells to obtain a plurality of intermediate voltages representing the similarity; Determining a dummy cell having a drain current closest to a drain of the memory cell by determining the highest voltage among the intermediate voltages; And And setting a predetermined voltage at an output terminal corresponding to the dummy cell identified in the checking step. A source region, a drain region, a channel region, and a floating gate, wherein the floating gate includes first and second floating gate portions, the first floating gate portion extends over the channel region, and the second floating gate portion is Extend away from the channel region; An apparatus for reading a charge level of a memory cell of a memory device, further comprising a program gate and a control gate, wherein the program gate forms a capacitor with the second floating gate portion. A plurality of dummy cells carrying a plurality of reference currents; Means for reading the reference current and the memory cell current; A plurality of analog circuits measuring a similarity between the current of the memory cell and the respective reference currents, and outputting a plurality of intermediate voltages representing the similarity; And A decision circuit for determining a dummy cell having a drain current closest to a drain current of the memory cell by determining the highest voltage among the intermediate voltages, and setting a predetermined voltage at an output terminal corresponding to the determined dummy cell; A charge level reading device of a memory cell, characterized in that. 12. The apparatus of claim 11, wherein the similarity is measured as a Euclidean distance between the current of the memory cell and the respective reference currents. 13. The apparatus of claim 12, wherein the analog circuit comprises a long channel metal oxide semiconductor (MOS) transistor. The method of claim 12, wherein the analog circuit is A pair of first driving MOS transistors; And a pair of second MOS transistors, wherein one electrode of each second MOS transistor is connected to one electrode of the one first driving MOS transistor so that the one first driving MOS transistor is connected to the one first. 2 MOS transistors, a gate of each of the first driving MOS transistors is connected to a gate of the one second MOS transistor, and another second MOS transistor is not connected to one electrode of the first driving MOS transistor. Gates of the first driving MOS transistor and the second MOS transistor are configured to cross each other; And And a third MOS transistor connected to another electrode of the first driving MOS transistors, wherein another electrode of the first driving MOS transistors is connected to the charge level reading device of the memory cell. 15. The apparatus of claim 14, wherein a gate of the third MOS transistor is shorted with an electrode of the third MOS transistor connected to the first MOS transistors. 16. The MOS transistor of claim 15, wherein the first driving MOS transistor is an n-MOS transistor, the one electrode is a source of the first driving MOS transistor, and the other electrode of the first driving MOS transistor is the first driving MOS transistor. The drain of the transistor, wherein the third MOS transistor is a p-MOS transistor, characterized in that the charge level reading device of the memory cell. 15. The apparatus of claim 14, wherein the second MOS transistor has an aspect ratio of about 10 times the aspect ratio (W / L) of the first MOS transistor. 12. The circuit of claim 11 wherein the decision circuit comprises a plurality of current conveyor transistors and current comparators, the current conveyor having one electrode connected to the same current biasing source, the gate electrode of the current conveyor being the intermediate voltage. The charge level reading device of a memory cell, characterized in that modulated by.