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KR20000015113A - Method for forming a contact hole of semiconductor devices - Google Patents

Method for forming a contact hole of semiconductor devices Download PDF

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Publication number
KR20000015113A
KR20000015113A KR1019980034854A KR19980034854A KR20000015113A KR 20000015113 A KR20000015113 A KR 20000015113A KR 1019980034854 A KR1019980034854 A KR 1019980034854A KR 19980034854 A KR19980034854 A KR 19980034854A KR 20000015113 A KR20000015113 A KR 20000015113A
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South Korea
Prior art keywords
contact hole
forming
interlayer insulating
insulating film
semiconductor substrate
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Korean (ko)
Inventor
조원석
김석규
이광재
황덕성
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윤종용
삼성전자 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명의 반도체 장치의 콘택홀 형성방법은 반도체 기판 상에 복수의 층간절연막을 형성하는 단계와, 사진식각공정을 이용하여 복수의 층간절연막을 식각하여 콘택홀을 형성하는 단계와, 상기 콘택홀이 형성된 반도체 기판의 전면에 보호층을 형성하는 단계와, 상기 보호층이 형성된 반도체 기판을 에치백하여 상기 콘택홀의 양측벽에 보호층을 남기는 단계와, 상기 콘택홀의 양측벽에 보호층이 형성된 반도체 기판을 습식 세정하는 단계를 포함한다. 이로써, 상기 콘택홀에 금속층을 증착할 때 배리어 금속층의 불균일한 형성 및 알루미늄 스파이크 현상등을 방지할 수 있다.A method of forming a contact hole in a semiconductor device of the present invention includes forming a plurality of interlayer insulating films on a semiconductor substrate, forming a contact hole by etching a plurality of interlayer insulating films using a photolithography process, and forming a contact hole. Forming a protective layer on the entire surface of the formed semiconductor substrate, etching back the semiconductor substrate on which the protective layer is formed, and leaving a protective layer on both side walls of the contact hole, and a protective substrate formed on both side walls of the contact hole. Wet cleaning. As a result, when the metal layer is deposited in the contact hole, non-uniform formation of the barrier metal layer and aluminum spike phenomenon may be prevented.

Description

반도체 장치의 콘택홀 형성방법Contact hole formation method of semiconductor device

본 발명은 반도체 장치의 콘택홀 형성 방법에 관한 것으로, 특히 다층의 층간절연막을 갖는 반도체 장치의 콘택홀 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact hole in a semiconductor device, and more particularly to a method for forming a contact hole in a semiconductor device having a multilayer interlayer insulating film.

고집적 반도체 소자를 구현하기 위하여 다층 배선 구조가 매우 폭 넓게 적용되고 있고, 이런 다층 배선 구조를 이루기 위해서는 층간절연 및 평탄화를 이루기 위하여 여러종류의 층간절연막 막질을 사용하여야 한다. 다시 말하면, 반도체 제조 공정의 다층 배선 구조를 형성하는데 있어서, 패턴된 층간의 분리 및 패턴 형성에 따라 발생하는 토폴로지 차이를 해소하기 위한 평탄화를 위하여 층잔절연막을 형성하고, 패턴간의 배선 연결을 위하여 해당 부위에 콘택홀을 형성한다.In order to implement a highly integrated semiconductor device, a multilayer wiring structure is widely applied, and in order to achieve such a multilayer wiring structure, various kinds of interlayer insulating film materials must be used to achieve interlayer insulation and planarization. In other words, in forming a multi-layered wiring structure of a semiconductor manufacturing process, a layer residue insulating film is formed for the purpose of planarization to solve the separation between the patterned layers and the topology difference caused by the pattern formation, and the corresponding portions for wiring connection between the patterns. A contact hole is formed in the hole.

도 1 내지 도 3은 종래 기술에 의하여 다층의 층간절연막을 갖는 반도체 장치의 콘택홀 형성방법을 설명하기 위한 단면도들이다.1 to 3 are cross-sectional views illustrating a method for forming a contact hole in a semiconductor device having a multilayer interlayer insulating film according to the prior art.

도 1을 참조하면, 반도체 기판(1), 예컨대 실리콘 기판 상에 각 층의 특성에 부합되는 절연막으로써, 제1 층간절연막(3), 제2 층간절연막(5) 및 제3 층간절연막(7)을 형성한다.Referring to FIG. 1, an insulating film corresponding to the characteristics of each layer on a semiconductor substrate 1, for example, a silicon substrate, includes a first interlayer insulating film 3, a second interlayer insulating film 5, and a third interlayer insulating film 7. To form.

도 2를 참조하면, 상기 제3 층간절연막(7) 상에 포토레지스트 패턴(도시 안됨)을 형성한다. 이어서, 상기 포토레지스트 패턴을 마스크로 제3 층간절연막(7) 및 제2 층간절연막(5)을 참조번호 8과 같이 습식 식각방법으로 식각한 후, 다시 상기 제2 층간절연막(5) 및 제1 층간절연막(3)을 참조번호 9와 같이 건식식각방법으로 식각하여 콘택홀(10)을 형성한다.Referring to FIG. 2, a photoresist pattern (not shown) is formed on the third interlayer insulating film 7. Subsequently, the third interlayer insulating film 7 and the second interlayer insulating film 5 are etched by a wet etching method as shown by reference numeral 8 using the photoresist pattern as a mask, and then the second interlayer insulating film 5 and the first interlayer insulating film 5 and the first interlayer insulating film 5 The interlayer insulating film 3 is etched by a dry etching method as shown by reference numeral 9 to form a contact hole 10.

도 3을 참조하면, 후속공정을 진행하기 전에 상기 콘택홀(10) 내에 자연 산화막에 의한 상기 콘택홀의 콘택 저항을 낮추기 위하여 습식 식각 용액을 이용하여 세정 처리한다. 이때, 상기 층간절연막들(3,5,7) 간의 습식 식각 속도 차이로 인하여 음의 단층(11)이 형성된다. 이렇게 음의 단층(11)이 콘택홀(10) 내에 존재하게 되면, 이후 배선층으로 사용되는 금속의 스퍼터링 공정시 상기 음의 단층(11)에 배리어 금속막이 제대로 형성되지 않아 리키지 소스로 작용하거나 심할 경우 알루미늄 스파이크 현상등을 유발하게 된다.Referring to FIG. 3, the wet etching solution may be cleaned using a wet etching solution to lower the contact resistance of the contact hole due to the natural oxide layer in the contact hole 10 before proceeding to the subsequent process. In this case, a negative single layer 11 is formed due to the difference in wet etching rates between the interlayer insulating layers 3, 5, and 7. When the negative single layer 11 is present in the contact hole 10, the barrier metal film is not properly formed in the negative single layer 11 during the sputtering process of the metal used as the wiring layer. This will cause aluminum spikes.

따라서, 본 발명이 이루고자 하는 기술적 과제는 상술한 층간절연막에 형성된 음의 단차를 방지할 수 있는 반도체 장치의 콘택홀 형성 방법을 제공하는 데 있다.Accordingly, an object of the present invention is to provide a method for forming a contact hole in a semiconductor device capable of preventing a negative step formed in the interlayer insulating film described above.

도 1 내지 도 3은 종래 기술에 의하여 다층의 층간절연막을 갖는 반도체 장치의 콘택홀 형성방법을 설명하기 위한 단면도들이다.1 to 3 are cross-sectional views illustrating a method for forming a contact hole in a semiconductor device having a multilayer interlayer insulating film according to the prior art.

도 4 내지 도 7은 본 발명에 의하여 다층의 층간절연막을 갖는 반도체 장치의 콘택홀 형성방법을 설명하기 위한 단면도들이다.4 through 7 are cross-sectional views illustrating a method for forming a contact hole in a semiconductor device having a multilayer interlayer insulating film according to the present invention.

상기 기술적 과제를 달성하기 위하여, 본 발명은 반도체 기판 상에 복수의 층간절연막을 형성하는 단계와, 사진식각공정을 이용하여 복수의 층간절연막을 식각하여 콘택홀을 형성하는 단계와, 상기 콘택홀이 형성된 반도체 기판의 전면에 보호층을 형성하는 단계와, 상기 보호층이 형성된 반도체 기판을 에치백하여 상기 콘택홀의 양측벽에 보호층을 남기는 단계와, 상기 콘택홀의 양측벽에 보호층이 형성된 반도체 기판을 습식 세정하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 장치의 콘택홀 형성 방법을 제공한다.In order to achieve the above technical problem, the present invention comprises the steps of forming a plurality of interlayer insulating films on a semiconductor substrate, forming a contact hole by etching a plurality of interlayer insulating films using a photolithography process, and the contact holes Forming a protective layer on the entire surface of the formed semiconductor substrate, etching back the semiconductor substrate on which the protective layer is formed, and leaving a protective layer on both side walls of the contact hole, and a protective substrate formed on both side walls of the contact hole. It provides a method for forming a contact hole of a semiconductor device comprising the step of wet cleaning.

이하, 첨부 도면을 참조하여 본 발명의 실시예를 상세히 설명한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 4 내지 도 7은 본 발명에 의하여 다층의 층간절연막을 갖는 반도체 장치의 콘택홀 형성방법을 설명하기 위한 단면도들이다.4 through 7 are cross-sectional views illustrating a method for forming a contact hole in a semiconductor device having a multilayer interlayer insulating film according to the present invention.

도 4을 참조하면, 반도체 기판(21), 예컨대 실리콘 기판 상에 각층에 부합되는 특성을 갖는 절연막으로써, 제1 층간절연막(23), 제2 층간절연막(25) 및 제3 층간절연막(27)을 형성한다. 상기 층간절연막들의 예로는 산화막 계열, BPSG 계열 또는 TEOS 계열을 사용할 수 있다.Referring to FIG. 4, an insulating film having characteristics corresponding to each layer on a semiconductor substrate 21, for example, a silicon substrate, includes a first interlayer insulating film 23, a second interlayer insulating film 25, and a third interlayer insulating film 27. To form. Examples of the interlayer insulating films may include an oxide film series, a BPSG series, or a TEOS series.

도 5를 참조하면, 사진공정을 이용하여 상기 제3 층간절연막(27) 상에 포토레지스트 패턴(도시 안됨)을 형성한다. 이어서, 상기 포토레지스트 패턴을 마스크로 상기 제3 층간절연막(27) 및 제2 층간절연막(25)을 참조번호 28과 같이 습식 식각방법을 이용하여 식각한 후, 다시 상기 제2 층간절연막(25) 및 제1 층간절연막(23)을 건식식각방법을 이용하여 식각하여 콘택홀(30)을 형성한다.Referring to FIG. 5, a photoresist pattern (not shown) is formed on the third interlayer insulating layer 27 by using a photolithography process. Subsequently, the third interlayer insulating film 27 and the second interlayer insulating film 25 are etched using a wet etching method as shown by reference numeral 28 using the photoresist pattern as a mask, and then the second interlayer insulating film 25 is again etched. And the first interlayer insulating layer 23 is etched using a dry etching method to form a contact hole 30.

도 6을 참조하면, 상기 콘택홀(30)이 형성된 반도체 기판(21)의 전면에 습식 식각 용액에 대하여 내성이 강한 막질로 보호층(31)을 얇은 절연막으로 형성한다. 상기 절연막은 질화막을 채용할 수 있다. 상기 보호층(31)은 종래의 습식 세정시 콘택홀의 측벽의 식각량 차이에 의한 음의 단층현상을 방지하기 위한 것이다. 이렇게 되면, 후속의 금속 증착공정시 스텝 커버리지에 안정한 구조를 갖는다. 더욱이, 층간절연막질을 선택하는데 있어서 종래에는 습식 식각 속도를 고려하여 한정된 막질만을 사용할 수밖에 없었으나 상기 보호층을 채용함으로써 절연특성 및 평탄도 측면만을 고려하여 뛰어난 막질을 채용할 수 있다.Referring to FIG. 6, the protective layer 31 is formed of a thin insulating film on the entire surface of the semiconductor substrate 21 on which the contact hole 30 is formed, with a film quality resistant to a wet etching solution. The insulating film may be a nitride film. The protective layer 31 is to prevent a negative fault phenomenon due to the difference in the etching amount of the side wall of the contact hole in the conventional wet cleaning. In this case, it has a structure stable to the step coverage during the subsequent metal deposition process. Furthermore, in selecting the interlayer insulating film quality, only a limited film quality can be used in consideration of the wet etching rate in the related art. However, by adopting the protective layer, it is possible to adopt an excellent film quality in consideration of insulation properties and flatness.

도 7을 참조하면, 콘택홀(30)을 다시 오픈하기 위하여 보호층이 형성된 기판의 전면에 에치백 공정을 진행하여 콘택홀(30) 측벽을 제외한 다른 부위에 증착된 보호막(31)을 제거한다. 이에 따라, 상기 콘택홀(30)의 양측벽에 보호층(31)이 형성된다. 다음에, 후속공정을 위하여 상기 콘택홀(30) 내의 자연산화막 등의 이물질을 제거 및 콘택저항 감소를 위하여 습식 세정을 실시한다. 이렇게 되면, 종래에 발생하던 콘택홀(30)의 측벽의 음의 단층 발생을 상기 보호층(31)으로 인하여 방지할 수 있다.Referring to FIG. 7, in order to reopen the contact hole 30, an etch back process is performed on the entire surface of the substrate on which the protective layer is formed to remove the protective film 31 deposited on other portions except the sidewalls of the contact hole 30. . Accordingly, the protective layer 31 is formed on both side walls of the contact hole 30. Next, a wet cleaning is performed to remove foreign substances such as a natural oxide film in the contact hole 30 and to reduce contact resistance for the subsequent process. In this case, it is possible to prevent the occurrence of a negative monolayer on the sidewall of the contact hole 30, which has occurred conventionally, due to the protective layer 31.

이상, 실시예를 통하여 본 발명을 구체적으로 설명하였지만, 본 발명은 이에 한정되는 것이 아니고, 본 발명의 기술적 사상 내에서 당 분야에서 통상의 지식으로 그 변형이나 개량이 가능하다.As mentioned above, although this invention was demonstrated concretely through the Example, this invention is not limited to this, A deformation | transformation and improvement are possible with the conventional knowledge in the art within the technical idea of this invention.

상술한 바와 같은 본 발명에 의한 반도체 장치의 콘택홀 형성방법에 의하면, 종래의 콘택홀 측벽의 음의 단층 형성을 배제함으로써 이루 공정에서 발생할 수 있는 여러 가지 공정상의 취약점, 예컨대 배리어 금속의 불균일, 알루미늄 스파이크현상을 해결하여 반도체 장치의 특성 및 안정화에 기여할 수 있다. 뿐만 아니라 고집적 반도체 장치의 디자인 룰의 미세화로 층간 공정 마진이 매우 협소한 현실을 감안할 때 본 발명에 의한 콘택홀 형성방법을 채용함으로써 코택 인접 층간의 공정 마진확보에도 일조를 함으로써 반도체 소자를 제조하는 안정적인 공정을 구현할 수 있다.According to the method for forming a contact hole in a semiconductor device according to the present invention as described above, various process weaknesses that may occur in the process by eliminating the negative single layer formation of the sidewalls of the conventional contact hole, such as non-uniformity of the barrier metal, aluminum It can contribute to the characteristics and stabilization of the semiconductor device by solving the spike phenomenon. In addition, in view of the fact that the interlayer process margin is very narrow due to the refinement of the design rule of the highly integrated semiconductor device, the contact hole forming method according to the present invention is adopted, thereby contributing to securing process margins between adjacent layers of the contact, thereby producing a stable semiconductor device. The process can be implemented.

Claims (1)

반도체 기판 상에 복수의 층간절연막을 형성하는 단계;Forming a plurality of interlayer insulating films on the semiconductor substrate; 사진식각공정을 이용하여 복수의 층간절연막을 식각하여 콘택홀을 형성하는 단계;Forming a contact hole by etching the plurality of interlayer insulating layers using a photolithography process; 상기 콘택홀이 형성된 반도체 기판의 전면에 보호층을 형성하는 단계;Forming a protective layer on an entire surface of the semiconductor substrate on which the contact hole is formed; 상기 보호층이 형성된 반도체 기판을 에치백하여 상기 콘택홀의 양측벽에 보호층을 남기는 단계; 및Etching back the semiconductor substrate on which the protective layer is formed, leaving protective layers on both sidewalls of the contact hole; And 상기 콘택홀의 양측벽에 보호층이 형성된 반도체 기판을 습식 세정하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 장치의 콘택홀 형성 방법.And wet-cleaning the semiconductor substrate having the protective layers formed on both sidewalls of the contact hole.
KR1019980034854A 1998-08-27 1998-08-27 Method for forming a contact hole of semiconductor devices Withdrawn KR20000015113A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7196004B2 (en) 2003-12-22 2007-03-27 Hynix Semiconductor Inc. Method and fabricating semiconductor device
KR100716651B1 (en) * 2004-06-07 2007-05-09 주식회사 하이닉스반도체 Semiconductor device manufacturing method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7196004B2 (en) 2003-12-22 2007-03-27 Hynix Semiconductor Inc. Method and fabricating semiconductor device
KR100716651B1 (en) * 2004-06-07 2007-05-09 주식회사 하이닉스반도체 Semiconductor device manufacturing method

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