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KR20000001452A - Structure of semiconductor package - Google Patents

Structure of semiconductor package Download PDF

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Publication number
KR20000001452A
KR20000001452A KR1019980021721A KR19980021721A KR20000001452A KR 20000001452 A KR20000001452 A KR 20000001452A KR 1019980021721 A KR1019980021721 A KR 1019980021721A KR 19980021721 A KR19980021721 A KR 19980021721A KR 20000001452 A KR20000001452 A KR 20000001452A
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South Korea
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lead
semiconductor package
present
leads
rows
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KR1019980021721A
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KR100331073B1 (en
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정지영
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김규현
아남반도체 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49586—Insulating layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

본 발명은 반도체패키지 구조에 관한 것이다.The present invention relates to a semiconductor package structure.

종래의 반도체패키지는 리드프레임의 구조가 단수(단층)의 리드열을 갖는 구조로서 입출력 신호선의 처리에 한계가 있어 고밀도의 반도체패키지를 제공할 수 없다는 문제점이 있었다.The conventional semiconductor package has a problem in that the structure of the lead frame has a single stage (single layer) of lead strings, so that the processing of the input / output signal lines is limited, and therefore, a high density semiconductor package cannot be provided.

본발명에서는 리드의 다단구조를 실현할 경우 이와 같은 문제점을 해결할 수 있다는 점에 착안하여 새로운 형태의 리드프레임 구조를 갖는 반도체캐키지를 발명하게 된 것으로, 본 발명에서는 리드프레임(1)에 형성되는 리드를 다단으로 형성하되 상,하층의 리드열(2′)(2)에 위치하는 리드(20′)(20)가 지그재그형으로 배치되도록 하여 많은 수의 와이어(40)를 실장할 수 있도록 한 것이다.In the present invention, a semiconductor package having a lead frame structure of a new type has been invented in view of the fact that this problem can be solved when the lead multi-stage structure is realized. In the present invention, a lead formed in the lead frame 1 is provided. Is formed in multiple stages so that the leads 20 'and 20 positioned in the lead rows 2' and 2 of the upper and lower layers are arranged in a zigzag shape so that a large number of wires 40 can be mounted. .

따라서, 본 발명에 의하면 반도체캐키지의 고밀도화를 실현하면서도 상대적으로 그 크기를 소형화할 수 있는 효과를 제공하게 된다.Therefore, according to the present invention, while providing a higher density of the semiconductor package, it is possible to provide an effect that can be relatively small in size.

Description

반도체패키지 구조Semiconductor Package Structure

본 발명은 반도체패키지 구조에 대한 것으로, 더욱 상세하게는 리드프레임에 형성되는 리드의 구성을 2단의 지그재그형 구조로 개량하여 좁은 공간에 리드의 수가 배가되도록 한 반도체패키지 구조에 관한 것이다.The present invention relates to a semiconductor package structure, and more particularly, to a semiconductor package structure in which a lead structure formed in a lead frame is improved to a two-stage zigzag structure to double the number of leads in a narrow space.

일반적으로, 반도체패키지를 제조함에 있어서는 반도체칩(30)을 탑재하기 위한 탑재판(10)과 신호의 입출력을 전달하기 위한 많은 수의 리드(20)를 구비한 리드프레임(1)을 거의 필수적으로 사용하고 있다.In general, in manufacturing a semiconductor package, a lead frame 1 having a mounting plate 10 for mounting a semiconductor chip 30 and a large number of leads 20 for transmitting and receiving signals is almost essentially required. I use it.

그런데, 한정된 크기의 리드프레임(1)에 반도체칩(30)과 대응하는 리드(20)를 만드다는 것은 기계장치의 구조적 한계로 인하여 인접한 리드(20)와 리드(20)간의 간격(피치)을 좁히는데 어느 정도 한계가 있는 것이며, 또한 리드(20)의 폭을 가늘게 만드는데도 와이어(40) 본딩을 위한 유효면적을 확보해야 하는 등의 난제를 해결해야 하는 어려움이 있는 것이다.However, the manufacturing of the lead 20 corresponding to the semiconductor chip 30 in the lead frame 1 having a limited size may cause a gap (pitch) between the adjacent leads 20 and the leads 20 due to the structural limitations of the mechanical device. There are some limitations to narrowing, and also, there is a difficulty in solving a problem such as securing an effective area for bonding the wire 40 even in narrowing the width of the lead 20.

따라서, 종래에는 도2의 예시에서 보는 바와 같이 인접하는 리드(20)와 리드(20) 간의 간격을 최대한으로 좁히는데 그친 이른바 단층구조의 리드구성을 사용하는데 만족해야만 했었다.Therefore, conventionally, as shown in the example of FIG. 2, it had to be satisfied to use a so-called single-layered lead structure that narrows the gap between the adjacent leads 20 and the leads 20 to the maximum.

그러나, 상기와 같은 반도체패키지의 구조는 입출력 신호선의 처리에 한계가 있어 고밀도의 반도체패키지를 제공할 수 없었으며, 더욱이 크기가 작고 두께가 얇은 고성능의 반도체패키지를 제조하는데에는 리드가 단층으로 구성된 리드프레임을 사용할 수가 없었다.However, the structure of the semiconductor package as described above has a limitation in processing input / output signal lines, and thus it is impossible to provide a high-density semiconductor package, and furthermore, a lead having a single layer is used to manufacture a high-performance semiconductor package that is small in size and thin in thickness. The frame was not available.

이에, 본 발명에서는 리드의 다단구조를 실현할 경우 이와 같은 문제점을 해결할 수 있다는 점에 착안하여 새로운 형태의 반도체캐키지를 발명하게 된 것으로써, 본 발명의 목적은 리드프레임에 형성되는 리드를 다단으로 형성하되 상하층에 위치하는 리드가 지그재그형으로 배치되도록 하여 리드 간의 전기적인 단락없이 많은 수의 와이어를 실장할 수 있도록 함으로써 반도체캐키지의 고밀도화를 실현하고 상대적으로 그 크기를 소형화 할 수 있도록 한 것이다.Accordingly, in the present invention, the inventors have invented a new type of semiconductor package in view of the fact that such a problem can be solved when the lead multi-stage structure is realized, and an object of the present invention is to multi-stage the lead formed in the lead frame. Formed, but the upper and lower leads are arranged in a zigzag form so that a large number of wires can be mounted without an electrical short between the leads to realize a high density of the semiconductor package and to relatively reduce its size. .

도 1은 종래 일반 반도체패키지 구성도1 is a configuration diagram of a conventional general semiconductor package

도 2는 종래 반도체패키지의 제조과정에 있어서 리드프레임에 탑재된 반도체칩과 리드프레임에 형성된 리드를 와이어로 연결한 상태를 보인 예시도(부분도)2 is an exemplary view showing a state in which a semiconductor chip mounted on a lead frame and a lead formed on the lead frame are connected by wires in the manufacturing process of the conventional semiconductor package (part view).

도 3은 본 발명의 반도체패키지 구성도3 is a configuration diagram of a semiconductor package of the present invention

도 4는 본 발명에 적용되는 리드프레임 구조를 보인 것으로, 리드프레임에 탑재된 반도체칩과 리드프레임에 형성된 리드를 와이어로 연결한 상태를 보인 예시도(부분도)Figure 4 is a view showing a lead frame structure applied to the present invention, an exemplary view showing a state in which the semiconductor chip mounted on the lead frame and the lead formed in the lead frame connected by a wire (partial view)

도 5는 도 3의 입체적 구성도5 is a three-dimensional configuration diagram of FIG.

도 6은 본 발명의 다른 실시예Figure 6 is another embodiment of the present invention

(도면의 주요부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)

1 ; 리드프레임 2, 2′ ; 리드열One ; Leadframe 2, 2 '; Lead heat

3 ; 절연수단 10 ; 탑재판3; Insulation means 10; Payload

20, 20′ ; 리드 30 ; 반도체칩20, 20 '; Lead 30; Semiconductor chip

30a ; 범프(단자) 40 ; 와이어30a; Bump (terminal) 40; wire

상기와 같은 목적을 달성하기 위한 본 발명의 반도체패키지 구조는 다음과 같은 특징을 제공한다.The semiconductor package structure of the present invention for achieving the above object provides the following features.

반도체칩(30)을 탑재하기 위한 탑재판(10)과 신호의 입출력을 전달하기 위한 많은 수의 리드(20)를 포함하는 리드열(2)을 구비한 리드프레임(1)을 사용하여 반도체패키지를 구성함에 있어서,Semiconductor package using a lead frame 1 having a mounting plate 10 for mounting the semiconductor chip 30 and a lead string 2 including a large number of leads 20 for transmitting input and output of signals. In constructing

상기 리드프레임(1)에 형성된 리드열(2)을 다단(복수)으로 구성하며,The lead row 2 formed in the lead frame 1 is configured in multiple stages (multiple),

상기 상,하단의 리드열(2′)(2)을 구성하는 각각의 인접 리드(20)(20′)가 지그재그형으로 배치되고,Adjacent leads 20 and 20 'constituting the upper and lower lead rows 2' and 2 'are arranged in a zigzag shape,

상기 상,하단의 리드열(2′)(2)은 절연수단(3)에 의해 전기적으로 차단된 구성을 갖도록 함을 특징으로 한다.The upper and lower lead rows 2 ', 2 are characterized in that they have a configuration that is electrically blocked by the insulating means (3).

따라서, 본 발명에 의하면 다단의 리드열(2)(2′)을 통해 많은 수의 와이어를 실장할 수 있어 반도체캐키지의 고밀도화를 실현하고 상대적으로 그 크기를 소형화 할 수 있는 효과를 제공하게 된다.Therefore, according to the present invention, a large number of wires can be mounted through the multi-stage lead rows 2 (2 '), thereby realizing higher density of the semiconductor package and providing an effect of relatively miniaturizing its size. .

(실시예)(Example)

이하, 본 발명을 첨부된 예시도면을 통해 보다 구체적으로 설명하면 다음과 같다.Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

도 3은 본 발명의 반도체패키지 구성도를 보인 것이며, 도 4는 본 발명에 적용되는 리드프레임(1)의 구조를 보인 것으로, 리드프레임(1)에 탑재된 반도체칩(30)과 리드프레임(1)에 형성된 리드(20)(20′)를 와이어(40)로 연결한 상태를 보인 예시도(부분도)이고, 도 5는 도 3의 있어서 상,하단 리드열(2′)(2)의 구성을 입체적으로 도시한 것이다.3 is a block diagram of a semiconductor package according to the present invention, and FIG. 4 is a view illustrating a structure of a lead frame 1 applied to the present invention. 1 is an exemplary view (part view) showing a state in which leads 20 and 20 'formed at 1) are connected with wires 40, and FIG. 5 is an upper and lower lead row 2' and 2 'in FIG. It shows the configuration of the three-dimensional.

도시한 바와 같이, 본 발명의 반도체패키지에 적용되는 리드프레임(1)은 다단(복수)으로 구성되는 리드열(2)(2′)을 구비하고 있다.As shown in the drawing, the lead frame 1 applied to the semiconductor package of the present invention includes lead rows 2 (2 ') composed of multiple stages (plural).

상기 상,하단의 리드열(2′)(2)을 구성하는 각각의 인접 리드(20)(20′)는 지그재그형으로 배치된다. 즉 하단의 리드열(2)에 배열된 리드(20)와 리드(20)의 사이에 상단의 리드열(2′)을 구성하는 각각의 리드(20′)가 위치하게 됨으로써 상,하단 리드열(2′)(2)을 구성하는 인접 리드(20)(20′)는 상하고 지그재그형의 입체적인 배치형태를 이루게 되는 것이다.Each adjacent lead 20, 20 'constituting the upper and lower lead rows 2', 2 'is arranged in a zigzag shape. That is, each lead 20 'constituting the upper lead row 2' is positioned between the leads 20 arranged in the lower lead row 2 and the leads 20, so that the upper and lower lead rows are positioned. Adjacent leads 20 and 20 'constituting (2') and (2 ') form upper and zigzag three-dimensional arrangements.

그리고, 본 발명을 구성하는 리드프레임(1)에 있어서 지그재그형으로 배치되는 상단 리드열(2′)의 리드(20′)는 하단 리드열(2)의 리드(20) 길이보다 짧게 구성되어 있다. 따라서, 와이어(40)의 본딩시 상,하단의 리드열(2′)(2)에 연결되는 와이어간의 간섭(전기적인 단락 등)을 최대한 받지 않게 된다.In the lead frame 1 constituting the present invention, the leads 20 'of the upper lead rows 2' arranged in a zigzag form are shorter than the length of the leads 20 of the lower lead rows 2. . Therefore, when bonding the wire 40, the interference between the wires (electric short circuit, etc.) connected to the upper and lower lead rows 2 ′ (2) is minimized.

한편, 상기 상,하단의 리드열(2′)(2)은 절연수단(3)에 의해 전기적으로 차단된 상태로서, 상기 절연수단(3)은 종이와 같은 얇은 두께의 부재로 구성되는데 그 예로는 절연성의 테이프 또는 비전도성의 코팅부재가 사용될 수 있다.Meanwhile, the upper and lower lead rows 2 'and 2 are electrically blocked by the insulating means 3, and the insulating means 3 is made of a thin member such as paper. Insulating tape or non-conductive coating member may be used.

이와 같은 구성으로 이루어지는 본 발명의 작용을 설명하면, 본 발명에서는 반도체칩(30)과 대응하는 리드의 구성이 하단 리드열(2)과 상단 리드열(2′)의 다단구성을 이룸과 동시에 인접하고 있는 리드(20)와 리드(20)의 사이간격(피치)에 상단 리드열(2′)을 구성하는 각각의 리드(20′)가 배치되는 상하 지그재그형의 배치형태를 취하고 있기 때문에, 많은 수(배가된)의 와이어(40)를 하단의 리드열(2)과 상단의 리드열(2′)에 지그재그형으로 연결을 할 수 있어 2배로 와이어(40)를 실장할 수 있는 것이며,Referring to the operation of the present invention having such a configuration, in the present invention, the configuration of the lead corresponding to the semiconductor chip 30 forms a multi-stage configuration of the lower lead row 2 and the upper lead row 2 'and at the same time adjacent to each other. Since the upper and lower zigzag arrangements in which the leads 20 'constituting the upper lead row 2' are arranged in the interval (pitch) between the leads 20 and the leads 20 are made, The number of wires (doubled) can be connected to the lower lead row 2 and the upper lead row 2 'in a zigzag form, so that the wire 40 can be mounted twice.

또한, 하단의 리드열(2)과 상단의 리드열(2′)에 와이어(40)를 연결함에 있어서도 상,하단 리드열(2′)(2)의 길이가 서로 다르고 배열된 높이가 달라 연결되는 와이어(40)끼리의 간격이 ½로 좁아진 상태이지만 인접 와이어간의 간섭(전기적인 단락 등)은 발생하지 않게 되는 것이다.In addition, even when connecting the wire 40 to the lower lead row 2 and the upper lead row 2 ', the lengths of the upper and lower lead rows 2' and 2 are different from each other and the heights arranged are different. The distance between the wires 40 to be narrowed to ½, but interference (electric short circuit, etc.) between adjacent wires does not occur.

그리고, 와이어(40)가 연결되는 상,하단의 리드열(2′)(2) 사이에는 테이프 등의 얇은 두께로 구성되는 절연수단(3)이 매개되어 있어 부피를 증가시키지 않으면서 리드열(2)과 리드열(2′)을 전기적으로 완전하게 차단할 수 있는 것이다.In addition, between the upper and lower lead rows 2 'and 2 to which the wires 40 are connected, an insulating means 3 composed of a thin thickness, such as a tape, is interposed, thereby increasing the volume of the lead rows without increasing the volume. 2) and the lead string 2 'can be completely blocked electrically.

한편, 본 발명의 구조는 도 3의 예시와 같이 범프(30a)가 일열로 배열된 반도체칩(30)의 경우 및 도6의 예시와 같이 범프(30)가 2열로 배열된 반도체칩(30)의 경우에 모두 적용될 수 있는 것이다.Meanwhile, the structure of the present invention is the semiconductor chip 30 in which the bumps 30a are arranged in one row as shown in FIG. 3 and the semiconductor chip 30 in which the bumps 30 are arranged in two rows as shown in FIG. In this case, all can be applied.

이와 같이, 본 발명에 의하면 다단의 리드열(2)(2′)을 통해 많은 수의 와이어(40)를 실장할 수 있어 반도체캐키지의 고밀도화를 실현하고 상대적으로 그 크기를 소형화 할 수 있는 효과를 제공하게 되는 것이다.As described above, according to the present invention, a large number of wires 40 can be mounted through the multi-stage lead rows 2 and 2 ', so that the semiconductor package can be densified and its size can be made relatively small. Will be provided.

이상에서 설명한 것은 본 발명에 의한 반도체패키지 구조를 설명하기 위한 하나의 실시예에 불과한 것이며, 본 발명은 상기한 실시예에 한정하지 않고 이하의 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진자라면 누구든지 다양한 변경 실시가 가능할 것이다.What has been described above is only one embodiment for explaining the structure of the semiconductor package according to the present invention, the present invention is not limited to the above-described embodiment without departing from the gist of the invention claimed in the following claims Various modifications can be made by those skilled in the art to which the invention pertains.

Claims (2)

반도체칩(30)을 탑재하기 위한 탑재판(10)과 신호의 입출력을 전달하기 위한 많은 수의 리드(20)를 포함하는 리드열(2)을 구비한 리드프레임(1)을 사용하는 반도체패키지를 구성함에 있어서,A semiconductor package using a lead frame 1 having a mounting plate 10 for mounting a semiconductor chip 30 and a lead string 2 including a large number of leads 20 for transferring input and output of signals. In constructing 와이어(40)가 연결되는 리드열(2)을 다단(복수)으로 형성하며, 상기 상,하단의 리드열(2′)(2)을 구성하는 각각의 인접 리드(20)(20′)가 지그재그형으로 배치되고, 상기 상,하단의 리드열(2)(2′) 사이에는 리드열(2)(2′)을 전기적으로 차단하기 위한 절연수단(3)을 매개하여서 이루어진 것을 특징으로 하는 반도체패키지 구조.The lead rows 2 to which the wires 40 are connected are formed in multiple stages (multiple), and each of the adjacent leads 20 and 20 'constituting the upper and lower lead rows 2' and 2 ' It is arranged in a zigzag shape, characterized in that made between the upper and lower lead rows (2) (2 ') via the insulating means (3) for electrically blocking the lead rows (2) (2') Semiconductor Package Structure. 반도체패키지를 구성하는 리드프레임(1)을 구성함에 있어서,In constructing the lead frame 1 constituting the semiconductor package, 하단의 리드열(2)과 상단의 리드열(2′)을 구성하는 리드(20)(20′)가 지그재그형으로 배치되고, 상기 상,하단의 리드열(2)(2′) 사이에 절연수단(3)을 부착 구성함을 특징으로 하는 리드프레임 구조.Leads 2 and 20 'constituting the lower lead row 2 and the upper lead row 2' are arranged in a zigzag shape, and are arranged between the upper and lower lead rows 2 and 2 '. Lead frame structure characterized in that the insulating means (3) attached to the configuration.
KR1019980021721A 1998-06-11 1998-06-11 Semiconductor Package Structure Expired - Lifetime KR100331073B1 (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030066994A (en) * 2002-02-06 2003-08-14 주식회사 칩팩코리아 Multi-layer lead frame and chip size package using the same
US6781306B2 (en) 2001-06-29 2004-08-24 Lg.Philips Lcd Co., Ltd. Organic electro-luminescence device and fabricating method thereof
US8049325B2 (en) 2008-11-25 2011-11-01 Samsung Electronics Co., Ltd. Integrated circuit devices having printed circuit boards therein with staggered bond fingers that support improved electrical isolation

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020007875A (en) * 2000-07-19 2002-01-29 마이클 디. 오브라이언 Leadframe for manufacturing semiconductor package

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6781306B2 (en) 2001-06-29 2004-08-24 Lg.Philips Lcd Co., Ltd. Organic electro-luminescence device and fabricating method thereof
KR20030066994A (en) * 2002-02-06 2003-08-14 주식회사 칩팩코리아 Multi-layer lead frame and chip size package using the same
US8049325B2 (en) 2008-11-25 2011-11-01 Samsung Electronics Co., Ltd. Integrated circuit devices having printed circuit boards therein with staggered bond fingers that support improved electrical isolation

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