KR19990064045A - Integrated circuit for storing and retrieving a plurality of digital bits per nonvolatile memory cell - Google Patents

Abstract

An integrated circuit storing multiple bits per memory cell is described. The amount of charge stored in a memory cell corresponds to the multiple bits in a memory cell. Latches (60-63, 65-67) are arranged in banks (A, B) and connected to the cells. The latches are controlled by control means (145, 146) so as to transfer data into the cells and to data terminals (25, 26). During writing and reading the data is transferred in parallel and serial modes.

Description

Integrated circuit for storing and retrieving a plurality of digital bits per nonvolatile memory cell

Nonvolatile semiconductor memories such as EEPROM, EPROM, and FLASH integrated circuits have typically been used to store a single digital bit per memory cell. This has been done by changing the threshold voltage (conduction) characteristics of the cell by maintaining a constant amount of charge on the floating gate of the memory cell. This threshold voltage range is typically divided into two levels (conductive versus non-conductive) to represent the storage of one digital bit per memory cell.

A wide range of charges can be reliably stored on the floating gate to represent a range of threshold voltages. The retention of charge on the floating gate can be divided to represent multiple threshold voltage ranges and the threshold voltage range can be divided into multiple ranges to represent storage of one or more digital data bits per memory cell. For example, four threshold voltage divisions may be used to represent storage of two digital bits per memory address location and sixteen divisions may be used to represent storage of four digital bits per memory address location. Moreover, the threshold voltage range can be divided into more sophisticated resolutions to represent the direct storage of analog information per memory cell.

The ability to store multiple digital bits per memory cell increases the effective storage density per unit area and reduces the storage cost per digital bit. In addition, in the semiconductor memory sector, the cost of modern manufacturing equipment exceeds $ 1 billion. The application of multiple bits of storage per cell to existing memory manufacturing processes and facilities enables the manufacture of the next generation of high density storage devices in the same manufacturing facility, thereby increasing usability and reinvesting.

Nevertheless, the operating speed, i.e., the problem of read and write operations, has not been satisfactorily described for a device having multiple bits per memory cell. The related problem is power dissipation. As more power is used to improve operating speed, power consumption also increases. Another problem is reliability. While charge can be stored in the floating gate of a memory cell for a very long time, erasing and rewriting of charge causes long-term problems with the certainty of the bits stored in the memory cell. And of course, any integrated circuit causes space problems. In integrated circuits with multiple bits per cell, additional circuitry has to be added to handle the new requirements. This partially negates the benefit of increased bits per memory cell.

The present invention solves and substantially alleviates these problems. Power distribution is reduced for read operations. The present invention also allows for reliable determination of the bits of a memory cell over a long period of time and saves space on integrated circuits.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to semiconductor memories, and more particularly to nonvolatile semiconductor memories capable of storing a plurality of digital bits per memory cell.

1 illustrates the main circuit block implemented on a single integrated circuit chip in accordance with the present invention.

FIG. 2A schematically illustrates the current-mode readout of the memory cell of FIG. 1. FIG.

FIG. 2B is a circuit diagram schematically illustrating a voltage-mode read of the memory cell of FIG. 1. FIG.

3 is a configuration diagram in which the configuration of array cells and reference cells in a block and a threshold division voltage reference generation block are connected to their respective arrays;

4 is a block diagram of the multilevel dual mode shift register of FIG.

5 illustrates the general configuration of the two Y-drivers of FIG.

FIG. 6 is a detailed view of the multilevel dual shift register of FIG. 4 showing a circuit in which a dual shift register can be used during write and read operations. FIG.

7 illustrates the reference multiplexer of FIG. 5 for each Y-driver.

8A is a detailed circuit diagram of a voltage comparator, latch, program and read control block and high voltage switch common for each Y-driver.

8B is a detailed circuit diagram of a voltage comparator, latch, program and read control block and high voltage switch and read mode path for a reference Y-driver with additional circuitry that allows all reference cells in the block to be read in parallel.

8C is a detailed view of a Y-multiplexer circuit with a reference Y-driver and a Y-multiplexer.

9A shows a Y-multiplexer common to all Y-drivers, an X-decoder block, an X-multiplexer common to each X-decoder, and one Y-driver with connections to the reference Y-multiplexer and the reference cell array; Detail view of memory cells common to one X-decoder.

9B is a circuit diagram of a single transistor memory cell in accordance with an embodiment of the present invention.

10 shows a scale from 0 volts to Vmax volts for various program threshold division voltages for the reference memory cell and the data storage memory cell.

11 is a detailed view of a threshold division voltage reference generation block.

12A illustrates tree decoding in a binary search algorithm in a read operation to determine digital bits that store selected memory cells.

12B is a flow chart for a binary search algorithm for a read operation.

The present invention provides an integrated circuit having a memory cell array in which each memory cell stores multiple bits of information and at least one terminal. The integrated circuit also has a plurality of latches connected to a memory cell array having latches that constitute the first bank and the second bank. During reading from and writing to the memory cell array, the latch and the memory cell array are controlled such that the first bank is connected to the memory cell array and the second bank is connected to the data terminals. Alternatively, the second bank is connected to the memory cell array and the first bank is connected to the data terminal. This alternating connection allows data to be transferred simultaneously between one bank of latches and a memory cell array and allows transfer between data terminals and another bank of latches for high speed read and write operations.

To reduce power dissipation, the memory cells of the array are read by voltage-mode operation. Furthermore, during the write operation, the voltage corresponding to the amount of charge stored in the selected memory cell is compared with the reference voltage to determine whether high voltage programming of the memory cell should continue. Programming of the memory cell ends when the corresponding voltage matches the reference voltage.

During a read operation, the voltage corresponding to the amount of charge stored in the selected memory cell is compared with the reference voltage sequence in a binary search pattern to determine a plurality of bits stored in the memory cell.

It should be noted that in the accompanying drawings, like reference numerals refer to like elements. This emphasizes the similar structure or behavior of the element. Moreover, the symbol of the MOS transistor is modified such that the straight line represents the source and drain of the transistor and the dotted line is parallel to the source / drain lines to represent the gate of the transistor.

Overview of Integrated Circuits

The main block of the preferred embodiment of the present invention is shown in FIG. The nonvolatile memory array 1 and the reference memory array 2 have memory cells connected to a two-dimensional array of rows and columns. This memory cell may be any device structure, such as EPROM, EEPROM, FLASH, or conventional cell structures, such as single transistors, two transistors, split-gates, NAND, AND, and DINOR cell structures, known in the art, and standards and It may be a ground array structure including a virtual ground structure. Depending on the device structure, a cell structure or ground array structure is selected, including specific voltages required for each of the cell's electrical terminals to facilitate storage of one or more digital bits per non-volatile memory cell. And reading algorithms can be easily developed. The cell may hold one or more nonvolatile devices such as NAND, DINOR or AND cell structures already known in the art. Specifics to device, array structure or cell structure and algorithms are not within the scope of the present invention.

Each of the memory arrays 1 and 2 constitutes a block having single or multiple rows. Each block consists of all or some columns of memory arrays 1 and 2. In FIG. 1 a memory block is shown with all columns in a single row. Each memory block consists of a cell from the reference array 2 and a cell from the memory array 1.

The error correction array 3 has a nonvolatile memory similar to that used for the memory array 1 and the reference array 2. In one embodiment, the error correction array 3 contains additional coding information required for on-chip ECC, known in the art as an Error Correction Code (ECC). In another embodiment, the error correction code 3 includes the full address of the defective cell to be prevented during a read or write operation. The size of the error correction array 3 depends on the maximum number of defective cells that can be corrected. During the output verification phase, the memory array 1 is tested to identify any defective cells. The addresses of these defective cells are programmed into the error correction array 3 before the chip is factory loaded. The error correction array 3 can be programmed using one or more bits per memory cell or can be programmed using a single bit per cell. If ECC correction is implemented, the error correction array 3 is automatically loaded with coding bits along with the on-chip ECC circuit. The error correction control and logic block 16 includes all addressing, decoding and sequencing circuitry necessary to implement one of the error correction embodiments as described above.

The memory management array 4 does not necessarily have to be physically contiguous in memory and address information for a block available for additional writes at any time, but the physical address for the block during sequential writes or reads of multiple logically contiguous blocks. Contains information. Memory management of the array improves long-term reliability of the product and allows for more efficient use of memory in environments where variable length serial data is frequently erased and rewritten. In this operation, only the start and end of the block address are provided and this data is accessed via clocking. Instead of providing the end of the block address, a stop signal can be used to signal the end of the variable block serial data. This mode is called "serial write and read access" mode and is generally used for digital audio record and playback systems, and also for semiconductor memory systems replacing mechanical disks. Serial write and read access modes with error correction and memory management allow the present invention to replace integrated circuit memory for digital audio record and playback systems and general digital data storage systems. Memory management logic block 24 includes sequencing circuitry necessary to perform memory management functions in conjunction with memory management array 4. The data in memory management array 4 may be one or more digital bits per cell or simply a single bit per memory cell as in arrays 1 and 2.

The spare block 5 has an additional block of memory cells that can be used to repair the entire block of cells that cannot be used. This kind of block redundancy is known to designers of memory integrated circuits. The block number of the spare block 5 defines the maximum number of blocks that can be repaired in the field during the included repair phase or during the manufacturing confirmation phase.

Addressing of the memory cells of the array 1 is provided by an address decoder 13 coupled to an externally connected serial interface block 14. The decoded address is passed from the decoder 13 to the Y-counter block 12 and the X-counter block 11. The output from the Y-counter block 12 is delivered to a Y-multiplexer block 8 that selects the desired block of memory cells of the array 1. The output of the X-counter block 11 is decoded in the X-decoder block 7 and the X-multiplexer block 6 to select the desired row of the block selected in the memory array 1.

The address decode block 13 generates the start address of the selected row. The decoded address is set in the X-counter 11 and the Y-counter 12 at the start of each new access operation for any length of the data stream. After the start address is provided, the data is serially accessed by the clock input to the chip. Serial interface block 14 includes circuitry necessary to perform the appropriate serial protocol with other external chips. The serial protocol can be any industry standard serial protocol or proprietary protocol. A typical serial interface signal entering the serial interface block 14 from this block is shown in FIG.

X-counter block 11 includes a digital counter that increments their count by clock signal YOUT and includes the output of Y-counter block 12 on line 27. The Y-counter block 12 is clocked by a signal CLCK on the input line 28 and generates a clock signal SHFT CLK on the line at various parts of the Y-driver. The Y-counter block 12 alternately provides the clock signal YOUT on the line 27 to the X-counter block 11.

The X-multiplexer block 6 provides the output of one X-decoder stage of the X-decoder block 7 to a plurality of rows of the array on an optional basis. This accommodates the circuit of the X-decoder without allowing the aspect ratio of the integrated circuit layout of the X-decoder to become excessively large. X-multiplexers and their use are known in the art. X-decoder block 7 comprises an X-decoder used to select rows of memory arrays 1 and 2. Details of the X-decoder block 7 and the X-multiplexer block 6 are described below and shown in FIG. 9A. The Y-multiplexer block 8 is the same as the X-multiplexer block 6, selecting an output of one of the Y-drivers and selecting multiple outputs of the memory array on an optional basis, as described in detail below. To any one of the columns. This is done again to match the memory array and Y-driver pitch in the column direction.

The read-write circuit block 9 comprises circuitry necessary for performing high-voltage write and low-voltage read operations on data from and into the array 1. Details of the read-write circuit block 9 are provided below.

A multilevel dual-shift register block 10 having a latch connected in series is placed between the data input and output terminals and the memory arrays 1 and 2. Data written to the memory array 1 is transferred in series to the memory array 1 through the line of data IN 25 for the block 10. Data read from the memory array 1 is moved from the memory array 1 to block 10 and then transferred serially from block 10 through the DATA OUT 26 line. System control logic block 15 includes the necessary control and sequencing circuitry to allow proper system operation. The test mode control and logic 17 block includes circuitry that allows full functional testing of the chip. Through the use of the test mode, the chip is reconfigured into various alternative test configurations that allow for faster and more efficient verification of the chip. These test modes are generally accessed at the factory confirmation phase, but any test mode can be accessed in the field, such as the array test mode using redundant block 5.

The program / erase / read algorithm block 18 provides all control and sequencing circuitry for performing intelligent programming, erasing and reading of digital data from the memory array 1.

Oscillator block 19 generates a clock signal for high voltage generation and provides a clock signal for program / erase / read algorithm block 18 and for other system clocking and synchronization purposes. Alternatively, if the oscillator block 19 is not equipped on-chip, its output signal must be supplied outside of the integrated circuit.

The charge pump 20 block generates a high voltage on-chip. The high voltage shaping and control block 20 receives the output signal of the charge pump block 20 and properly shapes the high voltage pulses with predetermined rise and fall times. High voltage pulse shaping is very important for long term reliability of the operation of integrated circuits. High pressure shaped pulses may also be provided externally. Alternatively, the unshape high voltage may be provided from an external source and pulsed with the appropriate rise and fall times into the on-chip circuit.

The nonvolatile scratch pad memory and the register block 22 have the same memory cells as the memory cells of the nonvolatile memory array 1. These memory cells are suitably configured and commonly used for external system management and characteristic requirements. In audio record and playback systems, for example, nonvolatile scratch pad memory and register block 22 include information about the number of messages and the time these messages are recorded. The data in nonvolatile scratch pad memory and registers may be stored as single or multiple bits per memory cell.

The on-chip band gap reference block 23 generates the analog voltage and current references required for the operation of the integrated circuit. These voltage and current references compensate for temperature and power supply variations. System performance is stabilized over a wide range of temperature and power supply ranges.

Typical Read Operation of Memory Cells

From now on, current-mode operation is generally described for multiple bit reads per memory cell. Current-mode reading has the advantage of fast access time. 2A has a general circuit arrangement for reading current-mode, using a single transistor memory cell. The structural features of this general circuit arrangement can be applied to other cell structures.

The nonvolatile memory cell 30 is typically connected in inverter mode. The voltage V _s at the source 31 of the transistor forming the cell 30 is grounded. The control gate 36 of the memory cell 30 is connected to an appropriate voltage V _g or switched to a power source voltage. The drain of the memory cell 30, which forms part of the column line 32 of the memory array in which the memory cell 30 is part, is generally connected to the current sense amplifier 33. The nonvolatile memory cell 30 is connected to the column line 32 via some selection circuit (not shown in the figure for simplicity). Current sense amplifier 33 is generally connected to reference current input line 34 for comparison purposes. The result of the comparison between the column line 32 and the reference current line 34 through the nonvolatile memory cell 30 is generated as a logic level at the logic output line 35.

For a single bit per cell, the presence and absence of a simple current through the memory cell 30 is determined. For many bits per memory cell, the amount of current passing through the cell 35 is compared with a set number of currents by changing the reference current at the input line 34. The signal at logic output 35 is decoded to determine the stored bit. For example, US Pat. No. 5,172,338 by Mehrotra describes a multi-bit read scheme using current-mode readout and shows various alternative embodiments. However, while current-mode reading can be used in the present invention, reading of memory cells in voltage-mode is preferred. This reduces power consumption compared to current-mode technology and allows multiple bits per memory integrated circuit cell, which is more suitable for low power, relatively slow access applications such as audio record and playback systems and mechanical magnetic disk replacement systems.

In the voltage-mode readout, the nonvolatile memory cell 30 is connected in source follower mode using a single transistor memory cell, as shown in FIG. 2B. The general voltage-mode feature can also be applied to other cell structures. The source 31 of the transistor forming the cell 30 is connected to the regulated supply voltage V _s from a stable voltage reference, such as a band gap reference. The control gate 36 is also connected to the same supply voltage as the source 31 or a voltage high enough to allow accurate reading by the highest expected voltage V _d at the drain of the cell 30. A stable constant bias current circuit 37 is connected between ground and the drain of the transistor, and also forms part of the column line 32 of the memory array, as in FIG. 2A. The amount of fixed bias current is small in the range between 0.5 microamps and 5.0 microamps. This small amount of current prevents excessive cumulative trapping of electrons during multiple read cycles, thereby preventing error reading of the memory cell 30. The drain voltage connected to the column line 32 via a selection circuit (not shown) is equal to V _g -V _gd , where V _gd is the memory cell 30 required for the current source caused by the bias current circuit 37. Is the gate-drain voltage. The drain of the transistor that is part of the column line 32 is connected to the input terminal of the voltage sense amplifier 38. The voltage sense amplifier 38 also has a reference voltage input line 39 and a logic output line 40. The voltages at transistor drain, column line 32 and reference voltage line 39 are compared so that the resulting logic output signal is provided to logic output line 40. The current required for reading in voltage-mode is much less than in current-mode. Thus, readings in voltage-mode have lower power dissipation.

The read voltage at line 32 depends on the amount of negative charge (electrons) on the floating gate 36 of the nonvolatile memory cell 30. Large amounts of charge on the floating gate increase the threshold voltage of the cell 30. Higher threshold voltages increase the gate-drain voltage of the cell 30. The voltage at line 32 drops to ground. Conversely, when the charge amount of the floating gate is small, the threshold voltage of the cell 30 is lowered and V _gd is decreased. Thus, the voltage at line 32 rises with respect to ground. By controlling the amount of charge on the floating gate, an appropriate reverse read voltage is generated in line 32. The process of injecting negative charge (electrons) into the floating gate is referred to as "erasing" the floating gate or memory cell, and removing the charge from the floating gate is referred to as "programming" the floating gate or memory cell.

During reading a plurality of bits from a single memory cell, the voltage at the drain of the transistor is compared with the various voltages at the reference voltage line 39. The logic output at line 40 is then decoded to provide the appropriate bits. With a source follower connection to memory cell 30, data access is slowed down because the entire column line 32 must be pulled up through a small memory cell. In certain applications, this slow access rate is allowed. As described below, the multilevel dual shift register effectively improves read access time.

Memory Array Configuration

3 illustrates the structure of the nonvolatile memory array 1 and the nonvolatile reference array 2. The memory cells in the nonvolatile reference array 2 are used to generate a comparison reference voltage for the voltage sense amplifier to determine the bits stored in the memory cells selected in the array 1. In a preferred embodiment of the present specification, 4 bits are stored per memory cell of each array 1 and 2. As mentioned above, each block of the preferred embodiment consists of rows. Each row consists of a reference memory cell and an array memory cell. All cells in a row are erased at the same time, and depending on the Y-multiplexer multiplexing scheme, only a portion of the row is programmed and read simultaneously. Since 4 bits are stored per memory cell, there are 16 reference memory cells per row. In this embodiment, each Y-driver drives eight memory cells, so there are two Y-drivers 42 for a row of 16 cells in the reference array 2. These Y-drivers 42 are referred to as REFY-drivers. In FIG. 3, only three Y-drivers 41 are illustrated for the memory array 1. These are M Y-drivers 41. The three memory array Y-drivers shown are labeled Y-drivers 0 through Y-drivers2. Reference threshold division voltage generation block 23, which is part of bandgap reference block 23 of FIG. 1, drives sixteen reference lines, each with one of reference voltages REFB0-REFB15, into REFY-driver 42, and FIG. Array threshold division voltage generation block 43, which is part of block 23 of 1, drives sixteen reference lines, each with one of the reference voltages REFA0-REFA15, into array Y-driver 41. The voltage relationship between the REFA0-15 and REFB0-15 signals is shown in FIG.

During the write operation, the WRITE signal on the WR line 46 is high and turns on a set of N-channel transistors 45 (denoted by dotted squares). The 16 REFA0-15 reference voltages of block 43 are passed to the Y-driver reference voltage line RFL015. These reference level voltages REFA0-REFA15 from block 43 are selectively programmed into the memory array 1 cell. Similarly, the reference voltages REBB0-REFB15 from block 44 are selectively programmed into the reference cells of array 2.

During the read operation, the write signal WRITE on the WR line 46 is driven low to turn off the transistor 45. On the other hand, a set of transistors 47 (indicated by dotted squares) are turned on to pass the reference REFB0-15 output voltage stored in the reference cell of the array 2 to the Y-driver 41 reference voltage line RFL015. The REFB0-REFB15 voltages read and stored from the cells of the reference array 2 are used as reference voltages to identify the digital bits stored in the cells of the memory array 1 through the binary search technique described below. The use of a reference cell per row or block in a preferred embodiment eliminates power supply and temperature variations by placing temperature fluctuations and the like in a common mode. Memory cells in arrays 1 and 2 are susceptible to the same temperature fluctuations. The reference cells of the array 2 are also susceptible to the same number of program and erase cycles as in the memory cells of the array 1, thus exhibiting the long-term aging effect of the cells of the common mode rows or blocks. This reference mechanism has the advantage of lowering the low current back-reading mode and allows for accurate readings of the digital bits and better long term reliability compared to the techniques already described. On-chip threshold voltage generation (compensated power supply and temperature) blocks 44 and 43 produce higher reliability than conventional effects in this field. Blocks 43 and 44 do not use nonvolatile memory cells to generate the threshold division voltage, but depend on more reliable and stable components such as resistors, operational amplifiers, and bandgap voltage sources. The present invention thus has improved long term reliability, accuracy and stability against temperature and power supply variations.

In another embodiment of the invention, the cells of the reference array 2 are programmed first. The output of the programmed reference cell from the array 2 then selects the cells of the memory array 1 with an offset to place the programmed level in the middle between the programmed reference levels as shown in FIG. 10. Used to program selectively. This method does not require block 43 to initially program the reference cell but requires additional time.

Dual Shift Registers for Data

4 is a block level representation of the multilevel dual shift register block 10 shown in FIG. 1 and is a portion of each of the Y-drivers 41 of FIG. The multilevel dual shift register block 10 has a latch consisting of two banks A and B. Each bank of latches is connected in series to form a large shift register. Each bank has four latches for each Y-driver 41. In Fig. 5, for each Y-driver 41, data is serially input through the dual shift register of block 10 and data is read serially through the dual shift register of block 10 during the write operation. Is output. Data information moves from the top to the bottom in each Y-driver 41 during the write operation and from the bottom to the top during the read operation. In general, the signal common to all Y-drivers 41 moves horizontally.

Of course, the depth of the Y-driver latch depends on the number of bits stored in one memory cell. In a preferred embodiment, four bits are stored in each cell. Therefore, there are four latches for each Y-driver 41. For example, in FIG. 4, the Y-driver 0 has four series connected latches 60-63 and the Y-driver 1 has four latches 65-67. Subsequently, the Y-driver M-1 has the last four latches connected in series. Since M is the number of Y-drivers, the total number of latches is 4 x M. Note that all latches are connected across all Y-drivers 41 in the long serial link to form a shift register. The true compensation output of all the latches is in parallel, as described below with reference to FIG. 6.

The two shift registers, bank A and bank B, are connected to data in line 25 and data out line 26 via transfer switches 145 and 146, respectively. When the REGSEL control line 147 is high, the data in line 25 and the data outline 26 are connected to the bank A shift register through the switch 145. When REGSEL control line 147 is low, data in line 25 and data outline 26 are coupled to bank B shift registers via switch 146. The SHFT CLK signal on line 29 clocks the shift register. In every cycle of the SHFT CLK signal, the data bit moves to the next latch. For example, the bits of latch 60 move to latch 61 and the bits of latch 61 previously move to latch 62, and so on. During normal operation of the dual shift register, one bank always operates in serial mode and the other bank operates in parallel mode. Banks in serial mode receive or read data from data terminals connected to data in line 25 and data out line 26. At the same time, other banks in parallel mode receive or load data from the memory cells of the array 10 in parallel. As the banks in serial mode complete their serial operations on the data, the other banks simultaneously complete their parallel operations from and to array 1. The serial bank is then switched to parallel mode and the parallel bank is switched to serial mode by changing the state of the REGSEL line 147. This synchronous switching from serial to parallel and vice versa occurs continuously during reading from the memory array 1 and writing to the memory array 1. Since there are M Y-drivers, M memory cells are written in parallel. Since 4 bits are written per cell, all 4 x M bits are written in parallel. This essentially provides a fast write rate of 4 x M compared to single bit operation. Similarly, 4 x M bits are read in parallel and then shifted to provide a high read rate of 4 x M. In fact, the read rate is performed at a higher speed by clocking the shift register at a higher clock rate. The maximum clock rate is limited by the time required for the parallel data to load into the latch during serial shifting operation. Thus, as mentioned above, the multilevel dual shift register block 10 allows for faster read and write access times for the memory cell array 1.

Switching between bank A and bank B may be asynchronous during read and write operations. For example, during a write operation, if the latch of the bank in serial mode is loaded before the latch of the other bank in parallel mode can program memory cells with multiple bits, the switches of the serial and parallel modes between the two shift registers are in parallel mode. You must wait until the bank of the section completes its programming operation. Conversely, if the parallel mode programming operation is completed before the serial operation of the first bank is completed, the parallel mode bank must wait until data is loaded into the serial mode bank. The same applies to the read operation. Thus, synchronous and asynchronous operation for dual shift register operation is possible through proper circuit implementation of system control logic block 15 (shown in FIG. 1). Details of the latches 60-63 of the Y-driver 0 and the latches 64-67 of the Y-driver 1 are shown in FIG.

Data Between Dual Shift Registers and Memory Arrays

5 illustrates the configuration of a Y-driver 41 with a multilevel dual shift register block 10, a read-write block 9 and a Y-multiplexer block 8. The individual Y-drivers 41 are identical in operation and circuit details, respectively. Only Y-driver 0 and Y-driver 1 are shown. Other Y-drivers M-1 are shown in dashed lines.

7 illustrates the circuit details for the reference multiplexer 50 of each read-write block 9 of the Y-driver 41. The true compensated output signal of each latch in the Y-driver 41 is passed to the reference multiplexer 50. Depending on the specific bits of the four latches in the Y-driver 41 (in this case Y-driver 0), the reference multiplexer 50 may pass one of the reference voltage lines RFL0-RFL15 to the RFLOUT of the multiplexer 50. Connect to the output terminal. Signals on lines 60A, 61A, 62A, 63A and 60B, 61B, 62B, 63B are provided with true and compensating output signals AA, from four latches of each Y-driver 41, as shown in FIG. AB, BA, BB, CA, CB, DA and DB).

The reference multiplexer 50 is essentially a 16 input-1 output (16-to-1) multiplexer, as is commonly known in the art. As can be seen in Fig. 7, only one of the RFL0-15 is shown as an output signal RFLOUT signal from the output terminals 60A to 63B of the latches, depending on the signals 60A to 63B. Transistors T11 to T16 are N-type transistors and the operation of multiplexer 50 should be understood. The size of the multiplexer depends on the number of bits stored in one memory cell. For example, a 6-bit storage system per memory cell requires a 64-in-1-output multiplexer.

8A shows details of the high voltage switch 54, program / read control circuit 53, latch 52 and voltage comparator 51 of the read-write block 9. The circuit of FIG. 8A is common to each of the Y-drivers 41. The voltage comparator 51 has transistors 70-76. Transistors 70 and 71 are P-channel transistors and the rest are N-channel transistors. The VBIAS voltage on line 198 from block 23 of FIG. 1 provides proper current biasing for voltage comparator 51. The circuit of the voltage comparator 51 is known in the art. Whenever the voltage on signal line 200 to the gate of transistor 73 is slightly higher than the RFLOUT voltage on the signal line to the gate of transistor 72, the SET voltage on voltage comparator output line 199 is also slightly higher. And vice versa. The gate of transistor 73 is generally referred to as a non-inverting input stage and the gate of transistor 72 is generally referred to as an inverting input stage. The signal lines 200 and 206 described below connect the non-inverting input terminal to the Y-multiplexer 55. Two lines 200 and 206 form a path for reading a plurality of bits stored in the cells of array 1. As described above, the inverting input stage receives the RFLOUT signal and the output of the reference multiplexer 50. The SET output line 199 of the voltage comparator 51 is connected to a gate and an input terminal of the transistor 80 of the latch 52.

The latch 52 has transistors 80 to 85. Transistors 82 and 83 are P-channel transistors and the rest are N-channel transistors. Latch 52 is a classic cross coupled inverter with an input node that is the gate of transistor 80 connected to SET output line 199 and another input node that is the gate of transistor 85 connected to RESET input line 202. It is a type. This latch circuit and its operation are known to integrated circuit designers. Transistors 81 and 82 form one inverter and transistors 83 and 84 form another inverter. The output node of the latch 52 is connected to the program read control circuit 53 by the signal line 201. If the signal on the SET line 199 is high, the latch output on the output line 201 is high. If the RESET line 202 is high or pulsed high, the signal on the latch output line 201 is low. The signals on SET line 199 and RESET line 202 are never high at the same time.

The program / read control circuit 53 has two AND gates 88 and 89 and two inverters 86 and 87. PROG (program) line 204 is the input to this circuit. The signal on the PROG (program) line 204 is high when the write mode is active, i.e., during the write operation, and low when the read mode is active, i.e. during the read operation. When PROG is high (when the write mode is active), the output of the AND gate 88 depends on the state of the output line 201 from the latch 202. If the latch output line 201 is low, then the output of the AND gate 88 on line 205 is high and vice versa if the PROG signal on line 204 is high. If the PROG signal on the PROG line 204 is high (write mode is active), the output of the AND gate 89 is low. The output line of AND gate 89 is connected to the gate of transistor 100. During the write operation, transistor 100 is turned off and does not allow a signal to pass from line 206 to line 200 connected to Y-multiplexer 55. Lines 200 and 206 form part of the read path.

The high voltage switch 54 has an inverter 90, two N-channel transistors 91 and 94, a capacitor 92 and a high voltage transistor 93. High voltage switch 54 does not allow high voltage on HV line 209 to pass from high voltage shaping and control block 21 (FIG. 1) to line 206 when line 205 is high, or line 205. When this is low, it acts as a transfer gate to block high voltage on HV line 209 from flowing to line 206.

Transistors 101 and 102 coupled to the read path formed by signal lines 200 and 206 provide a current load to the selected nonvolatile memory during the read operation. VB line 208 is a current bias line generated from the bandgap reference block 23 (FIG. 1) to the gate of transistor 102. Transistor 102 operates as a source of load current during read mode. Transistor 101 with its control gate connected to VCTL line 207 acts as a switch to turn the load current on and off. Inverters 103 and 104 buffer the SET output on line 199 from voltage comparator 51 and provide an output signal on read data line 210 during a read operation. Line 210 is connected to its corresponding latch (see FIG. 6) and line 206 is connected to its corresponding Y-multiplexer 55. Therefore, the transistors 101 and 102 serve as the bias current circuit 37 and the voltage comparator 51 serves as the voltage sense amplifier 38 of FIG. 2B for the read operation in the voltage mode.

8B shows the read-write block 9 of the reference Y-driver 42. The voltage comparator 51, the latch 52, the program read control circuit 53 and the high voltage switch 54 are the same as in the Y-driver 41 for the memory array 1 but with eight reference memory cells at a time. There is a modification for reading. During the read operation, the reference Y-driver 42 reads all reference cells connected to this driver. Since there are eight reference cells for each reference Y-driver of this embodiment, there are eight current loads formed by transistors 111 and 112, and each transistor output set is shown by a dashed box. The eight VCTL0-VCTL07 lines are forced high to connect current loads to their respective read lines 220-227.

During the write operation, only one of the reference cells as selected by the REF Y-multiplexer 56 is written to the reference Y-driver 42, as shown in FIG. When any one of the control lines MCTL0-MCTL7 is high, the bit line side RVD (FIG. 9A) is connected to the read path line 260-267 of FIG. 8B.

During the read operation, all VCTL0-VCTL07 and MCTL0-MCTL07 control lines are high; This allows all reference cells to be read in parallel. All VCTL0-VCTL07 control lines are high and also put a current load on each read path of the reference cell. In the read operation, the read signal 219 is also high so that the read voltage from the reference cell can be transferred to the RFL line. The eight reference voltages read from the reference cells (0-7) are passed through the reference Y-driver (0) to the RFL (0-7) signal lines, respectively, and eight read in parallel from the reference cells (8-15). The reference voltage is transmitted to the RFL 8-15 signal line through the reference Y-driver 1, respectively. In this embodiment, the voltage REREF015 (FIG. 10) is programmed to the reference cells 0-15, respectively. With the read signal on line 219 being high, transistor 211 is off and therefore no read voltage signal is transmitted to comparator input line 200. Note that transistors 110 and 93 are likewise positioned on all lines to allow the same functionality during the write mode of operation for all reference cells as occurs for memory cells of array 1 via Y-driver 41. do it.

In the reference Y-multiplexer 56 shown in Fig. 8C, each MCTL signal drives three series of transistors M1, M2, M3. This arrangement has the same impedance as provided by the Y-multiplexer 55 for the array 1 since there is a series of three transistors each time the memory array 1 cell is selected in the Y-multiplexer 55. Provide on line. This achieves better write and read mode matching characteristics between the cells of the memory array 1 and the reference array 2. Inverters 103 and 104 of Figure 8A have been removed from Figure 8B. This is because in the read operation, the digital bits are read from the cells of the memory array 1, while the reference voltage levels are read from the cells of the reference array 2.

9A shows a Y-multiplexer 55 for a Y-driver 41 for the memory array 1. Y-multiplexer 55 is the same as reference multiplexer 50. In this embodiment, the Y-multiplexer 55 is an 8 input-1 output multiplexer. The type of multiplexer varies depending on the cell size and the circuit size of the Y-driver. (N to 1) For the Y-multiplexer described, a single transmission path is used for the Y-address signals (M0A-M2A and M-A). It is connected between line 206 and one of the lines VD0 to VD7 depending on M0B-M2B). VD0 to VD7 are column lines of the memory array 1. During program and erase operations, a signal is transferred from line 206 to line VD0-7. During the read operation, a signal is transferred from line VD0-7 to line 206.

9A shows the connection to a nonvolatile memory cell for any number of arrays 1. In this embodiment, one X-decoder drives four rows of the array 1 and one Y-driver drives eight columns. Each row is considered a block in this embodiment. In other embodiments, multiple rows may form one single block. The selection of rows by a single X-decoder is performed by an X-multiplexer 58 which receives four X-address signals from the X-counter, PA to PD, as described above. This basic topology is extended in the X-direction to increase the number of rows in the array and to the Y-direction to increase the number of columns in the array to increase the size of the array.

9A also shows reference array 2 and reference multiplexer 56. There are 16 reference cells from the reference array per block. Each time a block is selected through the X-multiplexer 58, the reference and array cells are selected. The MCTL0-MCTL7 line drives the reference Y-multiplexer.

For the embodiments described herein, there are eight times more cells in one row than the number programmed at a time. Y-drivers 42 and 41 program every eighth cell in a row. A total of eight programming cycles are needed to program all the cells in a row. Thus cells 0, 8, 16 ... are programmed in the first programming cycle. Cells 1, 9, 17 ... are programmed in the second programming cycle and so on, all the cells are programmed. Eight programming cycles program one row. At the same time, the reference cells 0 and 8 are programmed in the first programming cycle. Reference cells 1 and 9 are programmed in a second programming cycle and programming for the cell continues until eight programming cycles complete programming for all 16 reference cells.

The latches of REF Y-driver 0 and REF Y-driver 1 are set at output 0 and output 8 respectively during the first programming cycle, and are set at output 1 and output 9 respectively during the second programming cycle, as shown in FIG. The reference multiplexer of reference Y-driver 42 is set to select the appropriate RFLOUT voltage at 50 output terminals of the multiplexer from REFB0-15 provided by reference generation block 44. During this write operation, the latch of the reference Y-driver 42 is internally set to program the appropriate voltage into the reference cell at the selected location of the array 2. At the same time, the latch of the Y-driver 41 is set externally by the data to be stored in the memory array 1. Of course, the number of programming cycles for a row depends on the ratio of the Y-multiplexer. The 8: 1 Y-multiplexer requires eight programming cycles, while the 16: 1 multiplexer requires 16 programming cycles.

Read Operation from Memory Array

To further understand the voltage mode reading method in the details of the circuit, reference is made to FIG. 9A. In this embodiment, the source lines common to the arrays 1 and 2 are connected to the regulated supply voltage V _s . Connections to the transistors of the cells of arrays 1 and 2 are shown in FIG. 9B. It is assumed that the cell surrounded by the circle of array 1 and marked XX is read. X-multiplexer 58 selects block 2 through line VG2, which is called a word line. The word line is connected to the control gate of each memory cell of the block. The selected word line is connected to the same supply voltage as well connected to the high voltage V _s of the source or enough to allow the accurate reading of the highest expected voltage at the column line (VD4) with respect to the ground. Y-multiplexer 55 connects column line VD4 to line 206. Referring now to FIG. 8A, line 206 is connected to line 200 through turned on transistor 100. During the read operation, PROG line 204 is low and RESET line 202 is high. This forces the gate of transistor 100 to go high to turn on transistor 100. The combination of transistors 101 and 102 forms a current source (represented as bias current circuit 37 in FIG. 2B) between line 200 and ground. Line 200 is also connected to the non-inverting input terminal of voltage comparator 51 (indicated as voltage sense amplifier 38 in FIG. 2B). Transistor 101 acts as a switch for the current source. Transistor 101 is only turned on for a short period to achieve proper voltage comparison by voltage comparator 51. The potential for power dissipation and the charge trapped in the oxide layer of the memory cell transistor is minimized. The RFLOUT input (represented as reference voltage 39 in Fig. 2B) connected to the inverting input terminal of the voltage comparator 51 is the reference multiplexer 50 from one of the lines RFL0-15 as shown in Figs. Is the voltage read from the appropriate reference cell as selected via < RTI ID = 0.0 > The result of the comparison in the voltage comparator 51 lies on the read data line 210 (shown as the logic output of FIG. 2B). During the read operation, high voltage switch 54 is turned off and high voltage line 209 is separated from line 206 by high voltage transistor 93.

As noted above, the dual shift register in block 10 is used for write and read operations to reduce the number of devices in the integrated circuit. The operation of the dual shift register during the write operation has already been described. In the read operation (see FIG. 6), four latches of the Y-driver 41 are preset through a binary search algorithm. The signals (bit 3, bit 2, bit 1, bit 0) are forced to be sequentially high in accordance with the binary search algorithm shown in Figs. 12A and 12B. Operation begins with a RESET pulse on the RESETB line of one bank of a multilevel dual shift register. The RESET pulse resets all latches on one bank of the dual shift register. According to the binary search algorithm, the bit 3 signal is forced high. This sets line 63A high and sets line 63B low for all latches (Latch 0, 4, 8, etc.) connected to the bit 3 signal line in all Y-drivers 41. The voltage on the RFL8 line of the reference multiplexer 50 is selected for the RFLOUT terminal of each Y-driver 41.

At the same time during this read operation, the RFL0-15 lines are driven in parallel by the voltage read from the cells of the reference array 2, as described above. According to the binary search algorithm, if the read voltage from the memory cell is higher than the selected voltage on RFLOUT in each driver, the data output on the read data line of each Y-driver 41 is high. This forces the output terminal 601 of the NAND gate 600 low (see FIG. 6), which sets the latch connected to the bit 3 line. The signal at the output terminal 602 of the latch remains high even when data on the line 210 is removed. Once the latch is set, the signals at output terminals 63A and 63B are high and low, respectively, even if line bit 3 is forced low. If the read voltage from the memory cell is lower than the voltage at the RFLOUT terminal, the signal on read data line 210 is low. This forces the signal at the output terminal of the NAND gate 600 high and the latch is in the reset state. Therefore, when signal bit 3 is forced low, the signals at latch output terminals 63A and 63B go low and high, respectively, and the state of the latch is reset. The binary search algorithm continues by forcing the bit 2, bit 1, and bit 0 lines high, respectively. A comparison operation is performed on the voltages on the RFLOUT line and the read data line 210 in each Y-driver 41. The connected latch remains in the set state if the read data line 210 is high or remains in the reset state if the reset data line 210 is low. Depending on the set or reset state of the latches in each Y-driver 41, different voltages from the RFL0-15 line may cause the reference multiplexer 50 inputs 63A, B to 60A, B (outputs of the latches). Is selected on the RFLOUT terminal.

Four bits from a single memory cell are read sequentially into four latches in each Y-driver. If N bits per memory cell are stored, N latches per Y-driver 41 and N bits per Y-driver are read in N cycles of the binary search algorithm. All M Y-drivers simultaneously load their respective latches. After the latch on one bank of the dual shift register is loaded, the bank is in shift mode and the latched data is then clocked out of this bank in series. While the data is shifted out, the other banks of the dual shift register are in parallel read mode and the data of the other M cells are read into the latches of this bank. As this bank completes loading its latches, the previous bank simultaneously completes its shifting operation. Alternate operations for parallel joding of data from memory cells and for orderly shifting of data provide very fast read access times.

During the read operation, the states of the four latches in each reference Y-driver 42 are not used. The RFLOUT line is not used in the reference Y-driver 42. Instead, the read voltages from all reference cells are located on the RFL0-15 line as described above and shown in Figure 8B.

Write Operation to Memory Array

For write operations, as is known in the art, programming and erasing algorithms typically use repetitive high voltage pulsed program cycles followed by regular read cycles to set the threshold voltage of a nonvolatile memory cell with high accuracy. . Prior to the start of the programming algorithm, an erase pulse of sufficient amplitude and duration is applied to complete the erase of the memory cell. Instead of one erase pulse, some algorithms repeat the high voltage erase pulse followed by a read operation as needed for the erase function. In the present invention, a single erase pulse is used so that an iterative high voltage pulse programming algorithm is applied to accurately set the threshold voltage. Also in this embodiment erase programming and reading takes place on a block basis for fast write and read access times. Thus M memory cells representing 4 times M digital bits are written or read simultaneously.

After the erase cycle erases all memory cells in the block, a programming cycle is performed. Initially the latch 52 (FIGS. 8A and 8B) of each Y-driver is reset by pulsing the reset 202 line. Thereafter, a read cycle is performed after the application of each programming pulse on an iterative basis. Within each Y-driver 41 and reference Y-driver 42, a read cycle is performed to determine whether the memory cell has reached the desired voltage level set at the RFLOUT output of the reference multiplexer 50. If the voltage level read on line 200 has not reached the RFLOUT level, latch 52 is in the reset state and an additional high voltage pulse is applied to the memory cell. The source of the high voltage pulse is the high voltage shaping and control block 21 shown in FIG.

During any iteration, if the voltage read on line 200 is higher than the voltage on RFLOUT line, latch 52 is set and the high voltage switch of each Y-driver 41 (and reference Y-driver 42) Is turned off. This stops further transmission of high voltage pulses to memory cells connected to a particular Y-driver. While some Y-drivers stop sending additional high voltages to their respective connected memory cells, other Y-drivers may deliver high voltage pulses to their respective memory cells to program the appropriate read voltage level. During programming, this read mode is exactly the same during normal read mode, except that the output signal on read data line 210 is not stored by the latch of block 10. The use of the same readout circuit during programming and readout mode provides more sophisticated and reliable data storage and retrieval.

10 shows the relationship between the threshold division reference levels for nonvolatile memory array 1 memory cells and nonvolatile memory array 2 memory cells. The divided threshold voltage range is shown from 0V to Vmax. REFA0 to REFA15 are threshold division voltages for the nonvolatile memory array 1 cells and REFB0 to REFB15 are threshold division voltages for the nonvolatile reference array 2 cells. The REFA0 through REFA15 levels are in the middle between the REFB0 through REFB15 levels. This ensures accurate and reliable long term readout of the threshold level.

FIG. 11 shows circuit details for a threshold division voltage generation block for nonvolatile memory array 1 and nonvolatile reference array 2. Bandgap voltage reference unit 300 is an on-chip temperature and power supply voltage source. The operational amplifier (OPAMP) 301 is a high gain, unconditional compensation amplifier. Circuits for the reference unit 300 and the operational amplifier 301 are known to the integrated circuit designer. Registers 302 through 318 are equivalent registers coupled as shown.

The threshold division generating block for the nonvolatile memory array 1 is formed when the register 318 is not connected in parallel to the register 317. The output is referred to as REFA0 through REFA15. When the register 318 is connected in parallel with the register 317, a non-volatile reference array 2 threshold division generating block is formed and the output is referred to as REFB0 through REFB15. Through a programming algorithm, in a preferred embodiment 16 reference cells per block are programmed to each of the threshold division voltages REB0 through REFB15. The nonvolatile memory array 1 is programmed to one of the REFA0 to REFA15 threshold division voltage levels as defined by each bit of the latch in each Y-driver 41.

In the described embodiment, there are eight times more cells in a row than the number that can be programmed at one time. Y-multiplexer 55 is programmed every 8 cells in a row. A total of eight program cycles are required to program all the cells in a row. Thus, cells 0, 8, 16 and the like are programmed during the first program cycle. Cells 1, 9, 17, etc. are programmed during the second program cycle, and so on, eight program cycles are performed to complete programming for one row.

At the same time, as selected through the reference Y-multiplexer 56, the reference cells 0 and 8 are programmed through two reference drivers 42 during the first cycle, and the cells 1 and 9 during the second cycle. Being programmed and so on. The latches of REFY-driver0 and REFY-driver1 are set to binary values "0" and "8" for the first cycle, respectively, to set the reference multiplexer 50 of the reference Y-driver 42, and the second It is set to binary values "1" and "9", respectively, during the cycle. Multiplexer 50 selects an appropriate voltage from the REFB0-15 voltage provided by reference threshold division voltage generation block 44 for the RFLOUT output voltage. In other words, during the write operation, the latch of block 10 of each reference Y-driver 42 is initially set to program the appropriate voltage to the reference cell at the selected cell location, while the memory array 1 is turned on. The latch of the block 10 of the Y-driver 41 for is set externally from the data stored in the memory array 1. The number of program cycles per row depends on the depth of the Y-multiplexers 55 and 56. For example, as described above, an 8: 1 multiplexer for the Y-multiplexer 55 requires eight program cycles, while a 16: 1 multiplexer requires 16 programs to complete programming for the entire row. Requires a cycle.

While various preferred embodiments of the invention have been disclosed in detail, it is evident that the invention is equally applicable by making appropriate modifications to the above embodiments. Therefore, the above description should not be taken as limiting the scope of the invention as defined by the appended claims.

Claims (20)

An integrated circuit having an array of each memory cell capable of storing a plurality of bits of information and at least one data terminal, A plurality of latches connected to the array of memory cells and constituting a first bank and a second bank; And Alternately, connect the first bank to the array of memory cells, the second bank to the one data terminal, connect a second bank to the array of memory cells, and connect the first bank to the one By connecting to data terminals, data is simultaneously transferred between one latch bank and the array of memory cells and between the other latch bank and the data terminals for high-speed read and write operations, and each latch bank to a memory cell block of the array. And control means for coupling, said memory cell block having M memory cells, each latch bank having NXM memory cells, and N latches being connected to each memory cell. The method of claim 1, wherein the control means is connected in series with a latch bank to the data terminal, During a write operation, the control means alternately connects the latch bank with the memory cell block to parallel transfer data from one latch bank to the memory cell block, and serially transfers data from the data terminal to the other latch bank. To connect the other latch bank to the data terminal, During a read operation, the control means alternately connects one latch bank with the memory cell block to parallel transfer data from the memory cell block to one latch bank, and transfers data from the other latch bank to the data terminal. And connect the other latch bank to the data terminal for serial transmission. 2. The apparatus of claim 1, further comprising first and second data terminals, During a write operation, the control means alternately connect the one latch bank to the memory cell block to transfer data in parallel from one latch bank to the memory cell block, and from the first data terminal to the other latch bank. Connect the other latch bank to the first data terminal for serial transmission of data; During a read operation, the control means alternately connects the one latch bank with the memory cell block to parallel transfer data from the memory cell block to one latch bank, and from the other latch bank to the second data terminal. And connect the other latch bank to the second data terminal for serial transmission of data. A circuit for storing a plurality of bits and reading the plurality of bits of an integrated circuit having a control terminal and an array of respective memory cells having first and second terminals, A bias current reference circuit for generating a bias current through the selected memory cell irrespective of the plurality of bits stored in the selected memory cell; A multiplexer circuit responsive to an address signal to couple the selected memory cell of the array to the bias current reference circuit; And A node coupled to the node between the second terminal of the selected memory cell and the bias current reference circuit and uniquely corresponding to the plurality of bits stored in the selected memory cell for the bias current to determine a bit stored in the memory cell And a voltage comparator circuit further coupled to said reference voltage for comparing a voltage at said node with a reference voltage. The method of claim 4, wherein Means for sequentially changing the reference voltage in an ordered sequence to determine a plurality of bits stored in the selected memory circuit; And a second memory array having a plurality of memory cells storing a plurality of reference voltages, wherein said means for sequentially changing connects selected memory cells of said second memory array to said voltage comparator in said ordered sequence. Characterized by a circuit. A circuit for programming an amount of charge in a selected memory cell corresponding to a plurality of bits in an integrated circuit having a memory cell array, comprising: A high voltage circuit for generating a high voltage to program a memory cell; Bias current reference circuit; A multiplexer circuit for coupling the selected memory cell to the bias current reference circuit for generating a bias current through the selected memory cell irrespective of a plurality of bits stored in the selected memory cell; A voltage comparator coupled to the node for determining a voltage at a node between the selected memory cell and the bias current reference circuit that uniquely corresponds to the amount of charge stored in the selected memory cell for the bias current; And The voltage coupled to the high voltage circuit and the voltage comparator and engaging the high voltage circuit to program the selected memory cell until the voltage corresponding to the amount of charge stored in the selected memory cell matches the reference voltage. And a programming circuit responsive to the comparator. Operating an integrated circuit having an array of respective memory cells capable of storing a plurality of bits of information, a plurality of latches connected to the array of memory cells and forming first and second banks, and at least one data terminal; In the method, Alternatively, the first bank is connected to the array of memory cells, the second bank is connected to the first data terminal, the second bank is connected to the array of memory cells, and the first bank is connected to the first bank. Connecting to one data terminal, each latch bank connected to a memory cell block of the array, the memory cell block having M memory cells, each latch bank having NXM memory cells, and N latch Is connected to each memory cell; And And simultaneously transferring data between one latch bank and said memory cell array and between another latch bank and said data terminal for high speed read and write. The method of claim 7, wherein the connecting step, A bank of latches is connected in series with the data terminal; During a write operation, one latch bank is alternately connected to the memory cell block to parallel transfer data from the latch bank to the memory cell block, and another latch bank serializes data from the data terminal to the other latch bank. Alternately connected to the data terminal for transmission; And During a read operation, one latch bank is alternately connected to the memory cell block to parallel transfer data from the memory cell block to the latch bank, and another latch bank serializes data from the other latch bank to the data terminal. Alternately connected to the data terminals for transmission. A method of reading a plurality of bits of said memory cells of an integrated circuit having first and second terminals and a control terminal and an array of respective memory cells storing a plurality of bits, the method comprising: Coupling the first terminal of the memory cell to a first voltage source; Coupling the control terminal of the memory cell to a voltage source to electrically connect the second terminal to the first terminal; Coupling the second terminal through the second terminal and the selected memory cell to a bias current circuit that generates a constant bias current independent of a plurality of bits stored in the selected memory cell; And Sense a voltage at the second terminal for a predetermined reference voltage uniquely corresponding to the plurality of bits stored in the selected memory cell for the bias current and output a digital output corresponding to the sensed voltage at the second terminal. Coupling the second terminal to a generating circuit. A method of reading a selected memory cell from said array of integrated circuits having said array of each memory cell having a floating gate capable of holding a charge amount indicative of a logic state stored in each memory cell, the method comprising: The memory cell so that a bias current is generated through the memory cell independent of the amount of charge on the memory cell floating gate and the voltage at a memory cell terminal uniquely corresponds to the amount of charge on the memory cell floating gate for bias current. Generating a memory cell voltage responsive to the amount of charge on the floating gate of the memory cell by connecting to a bias current reference circuit by a terminal of the memory cell; And Sequentially comparing the memory cell voltages with respect to one of a plurality of reference voltages, wherein each of the sequentially comparing steps includes one bit to determine a plurality of bits responsive to the amount of charge stored in the memory cell. Determining. 11. The method of claim 10, wherein said sequentially comparing comprises sequentially comparing said memory cell voltages to four reference voltages to determine four bits for said memory cells. A method of writing to a memory cell selected from said array of integrated circuits having said array of each memory cell having a floating gate capable of holding a charge amount indicative of a plurality of bits stored in each memory cell. Receiving a plurality of bits representing a plurality of bits to be stored in the selected memory cell; Generating a memory cell voltage in response to an amount of charge on the floating gate of the memory cell; Generating a plurality of reference voltages of the integrated circuit; Programming the floating gate of the memory cell such that the voltage of the memory cell matches one of the plurality of reference voltages corresponding to the plurality of bits, wherein the programming comprises: Erasing any charge from the floating gate of the memory cell; Subjecting the floating gate to a high voltage pulse; The memory cell voltage is determined by generating a bias current through the selected memory cell irrespective of the amount of charge on the floating gate of the selected memory cell, wherein the memory cell voltage is the selected memory for the bias current. Uniquely corresponds to the amount of charge on the floating gate of the cell; Comparing the memory cell voltage with the one reference voltage; And Repeating the step of determining, determining, and comparing until the memory cell voltage is matched with the one reference voltage. An array of memory cells each constituting a block having a reference memory cell and a data memory cell, the array of memory cells capable of holding voltages corresponding to a plurality of bits; A voltage generator circuit for generating a first and second reference voltage level sets; A programming circuit that simultaneously sets the voltage of the data memory cell for the first reference voltage level set and the second reference voltage level set of the reference memory cell, the voltage of the data memory cell corresponding to a data bit and ; And And a readout circuit for comparing the voltage set in the data memory cell against the second reference voltage level set in the reference memory cell to determine a data bit corresponding to the set voltage of the data memory cell. Integrated circuit. An array of memory cells each constituting a block having a reference memory cell and a data memory cell, the array of memory cells capable of holding voltages corresponding to a plurality of bits; A voltage generation circuit for generating a reference voltage level set; A programming circuit for setting the reference voltage level set in the reference memory cell and setting a voltage in the data memory cell with respect to the reference voltage level set, wherein the voltage set in the data memory cell corresponds to a data bit; And And a read circuit for comparing a voltage set in said data memory cell against said reference voltage level set in said reference memory cell to determine a data bit corresponding to said set voltage in said data memory cell. Integrated circuits. A method of operating an integrated circuit having an array of memory cells each having a reference memory cell and a data memory cell and capable of maintaining a voltage corresponding to a plurality of bits, Receiving a plurality of data bits; Programming a voltage of the data memory cell with reference to a first reference voltage level set, each voltage corresponding to a plurality of data bits; Simultaneously programming a second reference voltage level set of said reference memory cell; And Comparing the voltage programmed in the data memory cell against the second reference voltage level set in the reference memory cell to determine a data bit corresponding to the voltage programmed in the data memory cell. How to. The method of claim 15, Programming said voltage simultaneously programming the voltage of all said data memory cells of a given unit of said array and said reference voltage level set of all said reference memory cells of said unit; And said comparing step comprises simultaneously comparing the voltages of all said data memory cells of said unit against said reference voltage level set of all said reference memory cells of said unit. A method of operating an integrated circuit having a reference memory cell and a data memory cell and having an array of memory cells each capable of maintaining a voltage corresponding to a plurality of bits, Receiving a plurality of data bits; Programming a reference voltage level set of the reference memory cell; Programming a voltage of the data memory cell with reference to the reference voltage level set, each voltage corresponding to a plurality of data bits; And Comparing the voltage programmed in the data memory cell against the second reference voltage level set in the reference memory cell to determine a data bit corresponding to the voltage programmed in the data memory cell. How to. The method of claim 17, Programming said voltage simultaneously programming the voltage of all said data memory cells of a given unit of said array and said reference voltage level set of all said reference memory cells of said unit, And the comparing step comprises simultaneously comparing the voltages of all the data memory cells of the unit with respect to the reference voltage level set of all the reference memory cells of the unit. An array of memory cells each constituting a block having a reference memory cell and a data memory cell, the array of memory cells capable of holding voltages corresponding to a plurality of bits; A voltage generator circuit for generating a first and second reference voltage level sets; Programming circuitry for simultaneously setting a voltage corresponding to a data bit for said first reference voltage level set in said data memory cell and setting said second reference voltage level set in said reference memory cell; And Optionally comparing the voltage stored in the data memory cell to the second reference voltage level set of the reference memory cell to determine a data bit corresponding to the set voltage of the data memory cell, the data memory cell And a readout circuit for comparing with said first reference voltage level set to operate with said programming circuit to set a voltage for said first reference voltage level set of the < Desc / Clms Page number 12 > An array of each memory cell constituting each block having a reference memory cell and a data memory cell, the respective memory cells being capable of holding voltages corresponding to a plurality of bits; A voltage generation circuit for generating a reference voltage level set; A programming circuit for setting the reference voltage level set of the reference memory cell and setting a voltage for the reference voltage level set of the data memory cell, the voltage corresponding to a data bit; And The reference voltage of the reference memory cell to operate with the programming circuit to determine a data bit corresponding to the set voltage of the data memory cell and to set a voltage with respect to the reference voltage level set of the data memory cell. And a read circuit for selectively comparing the voltage set in said data memory cell with respect to a level set.