KR19990062003A - Method of forming multilayer metal wiring in semiconductor device - Google Patents
Method of forming multilayer metal wiring in semiconductor device Download PDFInfo
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- KR19990062003A KR19990062003A KR1019970082308A KR19970082308A KR19990062003A KR 19990062003 A KR19990062003 A KR 19990062003A KR 1019970082308 A KR1019970082308 A KR 1019970082308A KR 19970082308 A KR19970082308 A KR 19970082308A KR 19990062003 A KR19990062003 A KR 19990062003A
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- interlayer insulating
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 73
- 239000002184 metal Substances 0.000 title claims abstract description 73
- 238000000034 method Methods 0.000 title claims abstract description 28
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 239000011229 interlayer Substances 0.000 claims abstract description 31
- 239000010410 layer Substances 0.000 claims abstract description 25
- 238000000151 deposition Methods 0.000 claims abstract description 20
- 238000005530 etching Methods 0.000 claims abstract description 19
- 150000004767 nitrides Chemical class 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 230000004888 barrier function Effects 0.000 claims abstract description 6
- 239000010949 copper Substances 0.000 claims description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims 1
- 239000010936 titanium Substances 0.000 claims 1
- 229910052719 titanium Inorganic materials 0.000 claims 1
- 238000000059 patterning Methods 0.000 abstract description 9
- 230000015572 biosynthetic process Effects 0.000 abstract description 6
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 41
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 11
- 229910052721 tungsten Inorganic materials 0.000 description 11
- 239000010937 tungsten Substances 0.000 description 11
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000001465 metallisation Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- VEXZGXHMUGYJMC-UHFFFAOYSA-M Chloride anion Chemical compound [Cl-] VEXZGXHMUGYJMC-UHFFFAOYSA-M 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 평탄화시킨 산화막 위헤 질화막을 증착하여 콘택 또는 비아 패터닝용 하드마스크를 형성하고 다시 산화막을 증착한 후 메탈라인 패터닝용 감광막을 형성하여 식각함으로써 콘택과 비아와 메탈라인 패턴을 동시에 형성할 수 있도록 한 반도체장치의 다층 금속배선 형성방법에 관한 것으로, 반도체 기판상에 하부 배선을 형성하고 제1층간절연막을 증착한 후 평탄화하는 단계와, 평탄화된 제1층간절연막 전면에 질화막을 증착한 후 질화막을 식각하여 콘택홀 패턴을 형성하는 단계와, 콘택홀 패턴 전면에 제2층간절연막을 증착하는 단계와, 제2층간절연막 상부로 메탈마스크를 형성한 후 식각하여 이용하여 하부배선이 노출되도록 콘택홀을 형성하는 단계와, 콘택홀 전면에 장벽금속층을 형성한 후 메탈라인을 형성하고 평탄화하는 단계로 이루어져 공정의 단순화를 꾀할 수 있으며 금속배선 패터닝시의 마이크로 트랜치의 형성을 방지할 수 있다.The present invention is to form a hard mask for contact or via patterning by depositing a planarized oxide film on the oxide layer, and to form a photoresist film for metal line patterning after etching the oxide film to be etched to form a contact, a via and a metal line pattern at the same time A method of forming a multilayer metal wiring of a semiconductor device, the method comprising: forming a lower wiring on a semiconductor substrate, depositing a first interlayer insulating film, and then planarizing, depositing a nitride film over the entire first planarized interlayer insulating film, and then forming a nitride film. Forming a contact hole pattern by etching, depositing a second interlayer insulating film on the entire surface of the contact hole pattern, forming a metal mask on the second interlayer insulating film, and etching the contact hole to expose the lower wiring. Forming a barrier metal layer in front of the contact hole, and then forming and planarizing a metal line. Kkoehal adjuster can simplify the process and to prevent the formation of micro-trenches during the metal wiring pattern.
Description
본 발명은 반도체장치의 다층 금속배선 형성방법에 관한 것으로서, 보다 상세하게는 평탄화시킨 산화막 위헤 질화막을 증착하여 콘택 또는 비아 태너닝용 하드마스크를 형성하고 다시 산화막을 증착한 후 메탈라인 패터닝용 감광막을 형성하여 식각함으로써 콘택과 비아와 메탈라인 패턴을 동시에 형성할 수 있도록 한 반도체장치의 다층 금속배선 형성방법에 관한 것이다.The present invention relates to a method for forming a multi-layered metal wiring of a semiconductor device, and more particularly, to form a hard mask for contact or via tanning by depositing a planarized oxide film on a planarized oxide film, and then depositing an oxide film to form a photoresist film for metal line patterning. The present invention relates to a method for forming a multi-layered metal wiring of a semiconductor device to form a contact, a via, and a metal line pattern by etching.
반도체장치의 금속배선은 반도체장치의 속도, 수율 및 신뢰성에 큰 영향을 주기 때문에, 반도체장치의 금속배선 형성공정은 반도체장치 제조공정 중에 매우 중요한 위치를 차지하고 있다.Since the metal wiring of the semiconductor device greatly influences the speed, yield and reliability of the semiconductor device, the metal wiring forming process of the semiconductor device occupies a very important position in the semiconductor device manufacturing process.
일반적으로, 반도체 장치는 그 집적도가 증가하고 내부 회로가 복잡해지는 추세에 부응하여 다층의 배선 구조를 가지며, 이러한 다층 배선은 콘택 사이즈의 감소와 알루미늄의 열악한 스텝 커버리지(Step Coverage)로 인하여 화학기상증착(CVD) 방법으로 형성된 텅스텐 플러그를 통하여 서로 연결하고 있다.In general, semiconductor devices have a multi-layered wiring structure in response to a trend of increasing integration and complicated internal circuits, and the multi-layered wiring has a chemical vapor deposition due to a decrease in contact size and poor step coverage of aluminum. The tungsten plugs formed by the (CVD) method are connected to each other.
도1은 일반적인 텅스텐 플러그에 의한 반도체장치의 다층 금속배선 형성공정을 단계적으로 나타낸 단면도들이다1 is a cross-sectional view showing a step of forming a multi-layer metal wiring of a semiconductor device by a general tungsten plug.
도1a는 실리콘 기판(10)위에 소자간의 격리를 위한 필드산화막(15)과 폴리게이트(20)를 형성한 후 그 전면에 제1층간절연막(30)을 증착하고 평탄화를 시킨후 콘택을 형성하기 위한 콘택마스크(40)를 형성한 상태이다.FIG. 1A illustrates the formation of a field oxide film 15 and a polygate 20 for isolation between devices on a silicon substrate 10, and then depositing and planarizing a first interlayer insulating film 30 on the entire surface. The contact mask 40 is formed for.
도1b는 콘택마스크(40)를 통해 실리콘 기판(10)이 노출되도록 제1층간절연막(30)을 식각하여 콘택홀(45)을 형성한 상태이다.In FIG. 1B, the first interlayer insulating layer 30 is etched to expose the silicon substrate 10 through the contact mask 40 to form the contact hole 45.
도1c는 콘택홀(45) 전면에 플러그를 형성하기 위해 텅스텐을 CVD법으로 증착하고 평탄화하여 텅스텐플러그(50)를 형성한 상태이다.1C shows a state in which tungsten plug 50 is formed by depositing and planarizing tungsten by CVD to form a plug on the entire contact hole 45.
도1d는 텅스텐플러그(50) 전면에 금속배선을 위한 금속층(60)을 증착한 후 금속배선을 위한 메탈마스크(62)를 형성한 상태이다.1D is a state in which a metal mask 62 for metal wiring is formed after depositing a metal layer 60 for metal wiring on the entire surface of the tungsten plug 50.
도1e는 메탈마스크(62)를 통해 금속층(60)을 식각하여 메탈라인(64)을 형성한 상태이다.FIG. 1E illustrates a metal line 64 formed by etching the metal layer 60 through the metal mask 62.
도1f는 메탈라인(64)이 형성된 전면에 제2층간절연막(32)을 증착하고 평탄화시킨후 비아홀(70)을 형성을 상태이다.In FIG. 1F, the via hole 70 is formed after depositing and planarizing the second interlayer insulating film 32 on the entire surface where the metal line 64 is formed.
도1g는 하부의 메탈라인(64)과 서로 전기적으로 연결하기 위해 형성된 비아홀(70)에 CVD법으로 텅스텐을 형성한 후 평탄화시켜 텅스텐플러그(50)를 형성한 상태이다.FIG. 1G is a state in which tungsten plug 50 is formed by flattening after tungsten is formed in the via hole 70 formed to electrically connect the lower metal line 64 to each other by CVD.
도1h는 텅스텐플러그(50)를 형성한 후 제2층간절연막(32) 상부로 금속층을 형성한 후 패터닝하여 메탈라인(64)을 형성한 상태이다.FIG. 1H illustrates a metal line 64 formed by forming a tungsten plug 50 and then patterning a metal layer over the second interlayer insulating film 32.
위와 같이 층간절연막을 증착하고 평탄화 공정을 진행한 후 콘택 또는 비아 패턴을 형성하여 텅스텐플러그를 만든 후에, 금속 박막을 물리기상증착(Physical Vapor Depositon ; PVD)법 또는 화학기상증착(Chemical Capor Deposition ; CVD)법으로 증착한 후 패터닝된 감광막을 사용하여 식각을 함으로써 금속배선을 형성하게 된다.After depositing the interlayer insulating film and performing the planarization process as described above, after forming a contact or via pattern to form a tungsten plug, the metal thin film is deposited by physical vapor deposition (PVD) method or chemical vapor deposition (CVD). After the deposition by means of the etching method using a patterned photosensitive film to form a metal wiring.
그러나 이러한 방법을 사용하여 금속배선을 형성하는 경우에는 식각이 진행되는 동안에 염소이온(Cl-)에 의해 금속배선 측벽에서 핏팅부식(Pitting Corrosion)이 발생하기 쉬우며 금속성 폴리머를 제거하는 습식세정 공정시에 이러한 경향이 더욱 심화될 수 있다는 문제점이 있다.However, in the case of forming the metal wiring using this method, during the etching process, fitting corrosion is likely to occur on the sidewall of the metal wiring by chlorine ion (Cl − ) and during the wet cleaning process to remove the metallic polymer. There is a problem that this tendency can be further deepened.
이러한 문제점을 해결하기 위해서 반응기체에 질소(N2)를 첨가하여 금속배선의 측벽에 치밀한 보호막을 형성시키는 방법이 사용되기도 하지만, 이러한 방법도 로딩효과(loding effect)에 의해 도2에서 도시된 바와 같이 조밀한 패턴(67)과 고립된 패턴(69)에서의 측벽 경사도가 달라지는 문제점을 안고 있다.In order to solve this problem, a method of forming a dense protective film on the side wall of the metal wiring by adding nitrogen (N 2 ) to the reactor is used, but this method is also shown in Figure 2 by the loading effect (loding effect) Likewise, the side wall inclination in the dense pattern 67 and the isolated pattern 69 is changed.
본 발명은 상기와 같은 문제점을 해결하기 위해 창작된 것으로서, 본 발명의 목적은 반도체장치의 다층 금속배선 형성공정시 메탈라인 패터닝과 콘택홀 또는 비아홀 형성을 동시에 진행할 수 있도록 하는 반도체장치의 다층 금속배선 형성방법을 제공함에 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to enable metal line patterning and contact hole or via hole formation at the same time in a process of forming a multilayer metal wiring of a semiconductor device. It is to provide a formation method.
도1은 일반적인 텅스텐 플러그에 의한 반도체장치의 다층 금속배선 형성방법을 설명하기 위한 단면도들이다.1 is a cross-sectional view illustrating a method of forming a multilayer metal wiring of a semiconductor device by a general tungsten plug.
도2는 금속배선이 조밀한 부분과 고립된 부분의 측변변화를 나타낸 단면도이다.Fig. 2 is a cross-sectional view showing side changes of the dense and isolated portions of the metal wiring.
도3은 본 발명에 의한 반도체장치의 다층 금속배선 형성방법을 설명하기 위한 단면도들이다.3 is a cross-sectional view for explaining a method for forming a multilayer metal wiring of a semiconductor device according to the present invention.
- 도면의 주요부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawings-
10 : 기판 15 : 필드산화막10 substrate 15 field oxide film
20 : 폴리게이트 30,32,34 : 제1,2,3층간절연막20: poly gate 30, 32, 34: first, second, third interlayer insulating film
45 : 콘택홀 50 : 텅스텐플러그45: contact hole 50: tungsten plug
60,60a : 금속층 64,64a : 메탈라인60,60a: metal layer 64,64a: metal line
70 : 비아홀 80 : 장벽금속층70: via hole 80: barrier metal layer
90 : 질화막 95 : 구리플러그90 nitride film 95 copper plug
상기와 같은 목적을 실현하기 위한 본 발명은 반도체 기판상에 하부 배선을 형성하고 제1층간절연막을 증착한 후 평탄화하는 단계와, 평탄화된 제1층간절연막 전면에 질화막을 증착한 후 질화막을 식각하여 콘택홀 패턴을 형성하는 단계와, 콘택홀 패턴 전면에 제2층간절연막을 증착하는 단계와, 제2층간절연막 상부로 메탈마스크를 형성한 후 식각하여 이용하여 하부배선이 노출되도록 콘택홀을 형성하는 단계와, 콘택홀 전면에 장벽금속층을 형성한 후 메탈라인을 형성하고 평탄화하는 단계로 이루어지는 것을 특징으로 한다.The present invention for achieving the above object is formed by forming a lower wiring on the semiconductor substrate and depositing and then planarizing the first interlayer insulating film, by depositing a nitride film on the entire planarized first interlayer insulating film and then etching the nitride film Forming a contact hole pattern, depositing a second interlayer insulating film on the entire surface of the contact hole pattern, and forming a metal mask over the second interlayer insulating film to form a contact hole to expose the lower wiring by etching. And forming a metal line after the barrier metal layer is formed on the entire contact hole and planarizing the metal line.
상기와 같이 이루어진 본 발명은 하부 금속배선을 형성한 후 제1층간절연막을 형성한 후 평탄화시킨 후 질화막을 증착하여 콘택 또는 비아패턴을 형성하고 다시 제2층간절연막을 증착한 후 메탈라인 패터닝용 감광막을 형성하여 식각함으로써 메탈라인 패터닝과 콘택홀 또는 비아홀 형성을 동시에 진행할 수 있게 된다.According to the present invention made as described above, after forming the lower metal wiring and then forming the first interlayer insulating film, and then planarizing, depositing a nitride film to form a contact or via pattern, and again depositing a second interlayer insulating film, and then a photosensitive film for metal line patterning. Forming and etching may form metal line patterning and contact hole or via hole at the same time.
이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 설명한다. 또한 본 실시예는 본 발명의 권리범위를 한정하는 것은 아니고, 단지 예시로 제시된 것이며 종래 구성과 동일한 부분은 동일한 부호 및 명칭을 사용한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the present embodiment is not intended to limit the scope of the present invention, but is presented by way of example only and the same parts as in the conventional configuration using the same reference numerals and names.
도3은 본 발명에 따른 반도체장치의 다층 금속배선 형성방법을 설명하기 위한 도면들로서 반도체장치의 다층 금속배선 형성공정을 단계적으로 나타낸 단면도들이다.3 is a cross-sectional view illustrating a process of forming a multi-layer metal wiring of a semiconductor device according to an embodiment of the present invention.
도3a는 실리콘 기판(10) 상에 소자간 분리를 위한 필드산화막(15)과 하부배선인 폴리게이트(20)를 형성한 상태이다.FIG. 3A shows a state in which a field oxide film 15 and a polygate 20 as a lower wiring are formed on the silicon substrate 10 for isolation between devices.
도3b는 폴리게이트(20)가 형성된 전면에 제1층간절연막(30)을 형성한 후 평탄화한 상태이다.3B is a planarized state after forming the first interlayer insulating film 30 on the entire surface where the polygate 20 is formed.
도3c는 평탄화된 제1층간절연막(30) 전면에 질화막(90)을 형성하고 콘택홀을 형성하기 위한 콘택마스크(40)를 형성한 상태이다.3C is a state in which the nitride film 90 is formed on the entire planarized first interlayer insulating film 30 and the contact mask 40 for forming contact holes is formed.
도3d는 콘택마스크(40)를 이용하여 질화막(90) 만을 식각하여 콘택홀 패턴(47)을 형성한 상태이다.3D shows that the contact hole pattern 47 is formed by etching only the nitride film 90 using the contact mask 40.
도3e는 질화막(90)에 의해 콘택홀 패턴(47)이 형성된 전면에 제2층간절연막(32)을 증착하고 메탈라인 형성을 위한 메탈마스크(62)를 형성한 상태이다.3E is a state in which a second interlayer insulating film 32 is deposited on the entire surface where the contact hole pattern 47 is formed by the nitride film 90 and a metal mask 62 for forming a metal line is formed.
도3f는 메탈마스크(62)를 통해 질화막(90)에 대한 제1,2층간절연막(30)(32)의 식각 선택도가 높은 조건으로 제2층간절연막(32) 만을 선택적으로 식각하여 메탈라인 패턴(66) 부분을 형성하고 이어 질화막(90)이 드러나게 된 후 계속해서 폴리게이트(20)가 노출될 때까지 식각을 진행하면 질화막(90)이 하드마스크의 역할을 하게 되어 콘택홀(45)이 형성된 상태이다.FIG. 3F selectively etches only the second interlayer dielectric layer 32 on the condition that the etching selectivity of the first and second interlayer dielectric layers 30 and 32 with respect to the nitride film 90 is high through the metal mask 62. After forming the portion of the pattern 66 and subsequently etching the nitride film 90 until the polygate 20 is exposed, the nitride film 90 acts as a hard mask so that the contact hole 45 is formed. This is a formed state.
도3g는 도3f에서 형성된 메탈라인 패턴(66)과 콘택홀(45)에 금속층(60a)과의 접착성을 좋도록 하기 위한 장벽금속층(80)을 형성한 후 금속층(60a)인 구리(Cu)를 화학기상증착법으로 증착한 상태이다.FIG. 3G illustrates a barrier metal layer 80 formed on the metal line pattern 66 and the contact hole 45 formed in FIG. 3F to improve adhesion between the metal layer 60a and copper (Cu). ) Is deposited by chemical vapor deposition.
도3h는 금속층(60a)인 구리를 CMP를 실시하여 평탄화함으로서 첫 번째 메탈라인(64a)과 구리플러그(95)를 동시에 완성한 상태이다.3H shows that the first metal line 64a and the copper plug 95 are completed at the same time by planarizing the copper, which is the metal layer 60a, by CMP.
도3i는 평탄화된 메탈라인(64a) 위로 다층의 금속배선을 위해 제3층간절연막(34)을 형성하고 다시 질화막(90)을 형성한 후 제4층간절연막(36)을 증착하고 메탈마스크를 통해 식각하고 금속층을 증착한 후 평탄화하여 두 번째 메탈라인(64a)과 구리플러그(95)를 동시에 형성하여 다층 금속배선을 형성한 상태이다.FIG. 3i shows that a third interlayer insulating film 34 is formed over the planarized metal line 64a and a nitride film 90 is formed again, and then a fourth interlayer insulating film 36 is deposited and formed through a metal mask. After etching, the metal layer is deposited, and then planarized to form a second metal line 64a and a copper plug 95 at the same time to form a multi-layer metal wiring.
위와 같이 본 실시예는 제1층간절연막(30)을 증착한 후 제1층간절연막(30) 전면에 질화막(90)에 의한 콘택 패턴을 형성한 후 다시 제2층간절연막(32)을 증착하고 메탈마스크(62)를 통해 하부층까지 식각하여 동시에 메탈라인 패턴과 콘택홀 또는 비아홀 형성을 동시에 진행한다.As described above, in the present embodiment, after the first interlayer insulating film 30 is deposited, a contact pattern is formed on the entire surface of the first interlayer insulating film 30 by the nitride film 90, and then the second interlayer insulating film 32 is deposited again, and the metal is deposited. The lower layer is etched through the mask 62 to simultaneously form the metal line pattern, the contact hole or the via hole.
상기한 바와 같이 본 발명은 반도체장치의 다층 금속배선 형성시 금속배선 패터닝과 콘택홀 또는 비아홀 형성을 동시에 진행할 수 있기 때문에 공정의 단순화를 꾀할 수 있으며, 금속배선 패터닝에서의 마이크로 트랜치의 형성을 방지할 수 있다. 또한 금속배선의 두께를 일정하게 함으로써 금속배선의 평탄화에 용이하다는 이점이 있다.As described above, the present invention can simplify the process because the metallization patterning and the contact or via hole formation can be performed simultaneously when forming the multi-layered metallization of the semiconductor device, and the formation of micro trenches in the metallization patterning can be prevented. Can be. In addition, there is an advantage that the thickness of the metal wiring is made constant to facilitate the flattening of the metal wiring.
Claims (4)
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019970082308A KR19990062003A (en) | 1997-12-31 | 1997-12-31 | Method of forming multilayer metal wiring in semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019970082308A KR19990062003A (en) | 1997-12-31 | 1997-12-31 | Method of forming multilayer metal wiring in semiconductor device |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100395907B1 (en) * | 2001-05-17 | 2003-08-27 | 주식회사 하이닉스반도체 | Method for forming the line of semiconductor device |
| US6635566B1 (en) | 2000-06-15 | 2003-10-21 | Cypress Semiconductor Corporation | Method of making metallization and contact structures in an integrated circuit |
| KR100712817B1 (en) * | 2005-12-29 | 2007-04-30 | 동부일렉트로닉스 주식회사 | Semiconductor Device and Forming Method |
| KR100789612B1 (en) | 2006-12-11 | 2007-12-27 | 동부일렉트로닉스 주식회사 | How to Form Metal Wiring |
-
1997
- 1997-12-31 KR KR1019970082308A patent/KR19990062003A/en not_active Ceased
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6635566B1 (en) | 2000-06-15 | 2003-10-21 | Cypress Semiconductor Corporation | Method of making metallization and contact structures in an integrated circuit |
| KR100421154B1 (en) * | 2000-06-15 | 2004-03-03 | 사이프레스 세미컨덕터 코포레이션 | Method of making metallization and contact structures in an integrated circuit |
| KR100395907B1 (en) * | 2001-05-17 | 2003-08-27 | 주식회사 하이닉스반도체 | Method for forming the line of semiconductor device |
| KR100712817B1 (en) * | 2005-12-29 | 2007-04-30 | 동부일렉트로닉스 주식회사 | Semiconductor Device and Forming Method |
| KR100789612B1 (en) | 2006-12-11 | 2007-12-27 | 동부일렉트로닉스 주식회사 | How to Form Metal Wiring |
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