KR19990042744A - Device manufacturing method of semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, to form a double polysilicon layer and a double gate oxide film in a single process, and to form devices having different driving voltages in the same chip in a single process. A method for manufacturing a semiconductor device is provided.

To this end, the device forming method of the semiconductor device according to the present invention includes the steps of forming a first insulating film on the first conductive semiconductor substrate having a field oxide film, forming a first insulating film second conductive type first conductive layer and Forming a second insulating film on the first conductive layer, removing a predetermined portion of the second insulating film, the first conductive layer, and the first insulating film, and the first gate and the second insulating film protected by the remaining first insulating film and the second insulating film. Forming a storage electrode and simultaneously exposing the field oxide film and the surface of the substrate, forming a third insulating film on the entire surface of the semiconductor substrate, forming a second conductive second conductive layer on the third insulating film, and By removing a portion of the second conductive layer and the third insulating layer, the upper surface of the first gate and the first storage electrode and the surface of the field oxide layer and the semiconductor substrate are exposed, and at the same time Forming a second gate on the second insulating film and the third insulating film remaining on the ground electrode, and forming a second gate on the third insulating film of the predetermined portion, and also forming the second storage electrode and the second gate. Thereafter, forming an LED region with a second conductivity type impurity ion in a semiconductor substrate near the lower end side of the first gate and the second gate, the first gate, the second gate, the first storage electrode, and the second storage. Forming a sidewall with an insulating material on the side of the electrode, forming a second conductivity type source / drain on the side connected to the LED region in the semiconductor substrate, and forming an interlayer insulating film on the front surface of the semiconductor substrate to a sufficient thickness. It further comprises a step consisting of.

Description

Device manufacturing method of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, to form a double polysilicon layer and a double gate oxide film in a single process, and to form devices having different driving voltages in the same chip in a single process. A method for manufacturing a semiconductor device.

Recently, systems such as multimedia, which simultaneously display images, voices, and texts, are required to be miniaturized and lightweight while having various, complex, and improved functions. In order to meet the demand as described above, a technology of forming a single chip in which semiconductor circuits having different functions constituting a system are integrated and formed on the same chip has been developed.

Single-chip semiconductor circuits have different functions, and a plurality of circuits operating in different power sources must be formed such that the original functions and performances are maintained on the same semiconductor substrate. That is, a configuration of transistors having different driving voltages is required on the same semiconductor substrate, and in order to implement this, the threshold voltages of the devices must be adjusted to be different from each other.

In order to implement analog products that are rapidly increasing in demand among logic products in the process, a double polysilicon layer forming process is required, and a core in which logic operates substantially with the input / output terminal portion of a semiconductor device ( The dual gate oxide film forming process meets the requirements for products where the operating voltages of core parts are differently required. In the present invention, the low-resistance and high-speed devices required by logic are simplified while simplifying the above two processes in a single process. The purpose is to implement

In the prior art, since the process of forming the double polysilicon layer and the process of forming the dual gate oxide film are performed separately, the manufacturing process is shown in FIGS. 1A to 1D and 2A to 2D, respectively.

1A to 1D are cross-sectional views of a gate insulating film forming process in a device fabrication process of a semiconductor device according to the prior art.

In FIG. 1A, the gate oxide film 2 is thermally oxidized and grown on the surface of the silicon substrate 1, and a photoresist pattern 10 is formed on the thick gate oxide film formation site by performing a photo process for forming a thick gate oxide film. .

In FIG. 1B, a portion of the gate oxide film 3 in a portion that is not protected by the photoresist pattern 10 is removed and then a photoresist pattern (not shown) is removed. At this time, the portion removed by etching is a thin gate oxide film is formed in a subsequent process.

In FIG. 1C, the surface of the silicon substrate 1 is completely cleaned by performing pre-cleaning on the surface of the silicon substrate 1 to completely remove the remaining gate oxide film on the thin gate oxide film forming region, thereby removing the remaining gate oxide film 2. Expose

In Fig. 1D, the surface of the silicon substrate 1 is thermally oxidized to grow an oxide film on the entire surface of the substrate 1 again. Therefore, the remaining gate oxide film portion becomes thicker to form a thick gate oxide film 4 and the remaining portion becomes a thin gate oxide film 5.

2A to 2D show cross-sectional views of a manufacturing process of a semiconductor device according to the prior art.

In FIG. 2A, a first gate oxide film 23 is formed on a silicon substrate 21 on which a field oxide film 22 is formed for isolation between devices or separation of an active region and a field region, and then doped with first polysilicon. The layer 24 is formed by depositing, and again, by depositing a capping oxide layer 25 thereon, and then again by depositing a doped second polysilicon layer 26 thereon. The photoresist pattern 270 is formed by performing a photolithography process using a capacitor forming mask to be formed later.

In FIG. 2B, the second polysilicon layer 26 and the capping oxide layer 25 are etched by etching using the photoresist pattern 270 as an etch protection layer until the surface of the first polysilicon layer 24 is exposed. The first capacitor patterns 26 and 25 are formed by removing a part of the first capacitor patterns 26 and 25.

In FIG. 2C, a second photoresist pattern 280 is formed around the gate forming portion and the capacitor pattern 25 using a gate forming mask in a photolithography process to form a necessary gate.

In FIG. 2D, the first polysilicon layer 24 and the gate oxide film 23 of the portion not protected by the second photoresist pattern 280 are etched until the surface of the silicon substrate 21 is exposed. To remove it. Then, an oxide film is deposited on the entire surface of the formed device and the exposed substrate 21 by using a high temperature low pressure dielectric, etc., and then etched back to form sidewalls 200 on the side surfaces of the formed device.

Subsequently, although not shown in the drawing, an LED is formed around the lower surface side of the gate formed by ion implantation using sidewalls to form a semiconductor device and the like.

As described above, since the dual gate oxide film forming process and the double polysilicon layer forming technology are performed as separate processes in the related art, in some cases, masking is required in a process requiring both the dual gate oxide film formation and the double polysilicon layer formation. The process cost increases due to the increase in the number of steps due to the increase in the number of steps in the operation.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a semiconductor device in which a double polysilicon layer and a double gate oxide film are formed in a single process, and a device having different driving voltages in the same chip can be formed in a single process. have.

A device forming method of a semiconductor device according to the present invention for achieving the above object, the step of forming a first insulating film on the first conductive semiconductor substrate on which the field oxide film is formed, the first insulating film second conductive type first conductive layer Forming a second insulating film on the first conductive layer, and removing a predetermined portion of the second insulating film, the first conductive layer, and the first insulating film, and protecting the first insulating film and the second insulating film. Forming a first gate and a first storage electrode and simultaneously exposing the surface of the field oxide film and the substrate, forming a third insulating film on the entire surface of the semiconductor substrate, and forming a second conductive second conductive layer on the third insulating film. And forming a portion of the second conductive layer and the third insulating layer to expose the upper surface of the first gate and the first storage electrode and the surface of the field oxide layer and the semiconductor substrate. Simultaneously forming a second gate on the second storage electrode and the third insulating film remaining on the first storage electrode and on the third insulating film. The second storage electrode and the second storage electrode After the gate forming step, forming an LED region with a second conductivity type impurity ion in a semiconductor substrate near the lower end side of the first gate and the second gate, the first gate, the second gate, the first storage electrode, Forming a sidewall with an insulating material on the side of the second storage electrode, forming a second conductive source / drain on the side connected to the LED area in the semiconductor substrate, and forming an interlayer insulating film on the front surface of the semiconductor substrate to a sufficient thickness. It further comprises a step comprising the step of forming.

1A to 1D are cross-sectional views of a gate insulating film forming process in a device fabrication process of a semiconductor device according to the prior art.

2A to 2D are cross-sectional views of a manufacturing process of a semiconductor device according to the prior art.

3A to 3E are cross-sectional views of a manufacturing process of a semiconductor device according to the present invention.

The present invention implements a double polysilicon layer forming process and a dual gate oxide film forming process in a single process. In other words, the transistors having different thicknesses may be manufactured by differentiating the main logic region and the gate oxide layer from the input / output region or the specific region.

In addition, when forming a double polysilicon layer consisting of the first polysilicon layer and the second polysilicon layer, a capping oxide film may be automatically formed between the layers. In other words, in terms of the role of the transistor, a first transistor including a first polysilicon layer and a first gate oxide layer and a second transistor including a second polysilicon layer and a second gate oxide layer are formed, and a capacitor for implementing an analog process is formed. A capacitor is formed of the first polysilicon layer-capping oxide-second polysilicon.

In general, logic is designed by varying the operating voltages of the input / output part and the main core part, and in the case of the system, the demand tends to increase. This is due to the intention to operate the logic by accepting the external voltage as it is in the input / output of data and to operate the low voltage in the main core. Accordingly, problems of breakdown voltage and threshold voltage of the gate oxide film are raised. For this purpose, a dual gate oxide film forming process is used. Apart from this, the double polysilicon forming process is widely used as a method of implementing analog signals in logic. The process of simultaneously meeting the above-described needs is the significance of the present invention.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

3A to 3D are cross-sectional views of device manufacturing processes of the semiconductor device according to the present invention.

In FIG. 3A, a field oxide film 32 for device isolation is formed on a first conductive silicon substrate 31 by a LOCOS process, and then a first insulating film 33 is formed on the surface of the substrate 31. It is formed by depositing with a nitride film. In this case, the first insulating film may be a first gate insulating film and a silicon oxide film may be formed by thermally oxidizing the surface of the substrate instead of the nitride film.

In addition, a first polysilicon layer 34 doped with a second conductivity type impurity for forming the first gate and the first storage electrode is formed by depositing the first insulating layer 33 on the second insulating layer 35. The nitride film is formed by vapor deposition. The nitride film is an electrically insulator and plays a role of countering etching in the etching process.

Thereafter, a first photoresist pattern 370 is formed on the second insulating layer by performing a photolithography process using a photoresist and a mask for forming a gate and storage electrode to be formed later.

In FIG. 3B, the second insulating layer 35, the first polysilicon layer 34, and the first insulating layer 33 of the portion not protected by the photoresist pattern 370 are removed by wet etching. The first gate 344 and the first storage electrode 34 which are respectively protected by the first insulating film 33 and the second insulating film 35 having the remaining lower surfaces are formed, and the field oxide film 32 and the substrate 31 are formed. Expose the surface of the. At this time, the first gate located on the opposite side of the drawing becomes a first transistor, and the thickness of the gate insulating film of the first gate of the first transistor has the thickness of the first insulating film.

In FIG. 3C, thermal oxidation is performed on the entire surface of the substrate 31 again to protect the exposed surface of the substrate 31 and the side surfaces of the exposed first gate 344 and the first storage electrode 34. The third insulating film 36 is formed. In this case, the growth thickness of the thermally oxidized film 36, which is the third insulating film grown, is formed to be different from the thickness of the first insulating film 33 remaining under the first gate 34, so as to meet the required voltage of the transistor. Also, the oxidation reaction proceeds under the nitride film, which is the second insulating film 35 remaining on the first gate 344 and the first storage electrode 34, so that the second insulating film 35 and the first gate 344 are oxidized. And the third insulating film 36 is also formed between the first storage electrode 34 and the oxide film also serves for the interlayer buffer.

Then, a second polysilicon layer 37 doped with a second conductivity type impurity is deposited on the oxide layer, which is the third insulating layer 36, and then a photoresist is applied thereon to form the second gate and the second storage electrode. A photo process using a mask is performed to form the second photoresist pattern 380. In this case, a photoresist pattern 380 is formed on the first storage electrode 34 of the capacitor forming portion to form a second storage electrode to be formed by forming a double polysilicon layer, and on the left side of the first gate 344 in the drawing The photoresist pattern 380 for forming the second gate is positioned.

In FIG. 3D, the second polysilicon layer 37 and the third insulating layer 36 in portions not protected by the second photoresist pattern 380 are etched to remove the first gate 344 and the first gate 344. 1 The upper surface of the storage electrode 34 and the surface of the field oxide film 32 and the substrate 31 are exposed. As a result, the second storage electrode 37 is formed on the second insulating film 35 and the third insulating film 36 remaining on the first storage electrode 34 and the third gate is formed on the left side of the first gate 344 in the drawing. The second gate 377 is formed on the insulating film 36, wherein the gate insulating film of the second gate is the remaining third insulating film 36, and due to the difference in the threshold voltage of the transistor required as described above, the thickness thereof is the first. It is different from the thickness of the gate 34.

In FIG. 3E, the second conductivity type impurity ion implantation is performed at low concentration using the first gate 344 and the second gate 377 as a mask to form the LED region in the substrate 31 near the lower side of the gate. After the formation, a thick oxide film is deposited on the entire surface of the substrate 31 and then etched back to form sidewalls 300 on the side surfaces of the formed elements. The sidewall 300 formed at this time is used as a mask for forming a high concentration impurity implantation region during transistor formation while insulating side surfaces of each device exposed from etching for forming the second gate and the second storage electrode from the surroundings.

In addition, the second conductive type impurity ion implantation using the sidewalls 300 of the first gate and the second gate as a mask is performed at a high concentration to form an impurity implantation portion for the source / drain region, and then the substrate is sufficiently filled with impurity ions through a heat treatment process. The transistors and capacitors are completed by diffusing into (31) to form source / drain regions and then depositing an interlayer insulating film (not shown) to a sufficient thickness on the entire surface of the substrate (31).

Accordingly, the present invention provides an advantage of providing an analog semiconductor chip for a double polysilicon layer forming process in system design and a simple process in comparison with the conventional technology in designing devices having different operating voltages of the input / output unit and the core unit.

Claims (7)

Forming a first insulating film on the first conductive semiconductor substrate on which the field oxide film is formed; Forming a second conductive type first conductive layer on the first insulating film; Forming a second insulating film on the first conductive layer; A first gate and a first storage electrode protected by the first insulating film and the second insulating film remaining by removing predetermined portions of the second insulating film, the first conductive layer and the first insulating film are formed, and simultaneously the field oxide film is formed. Exposing a surface of the substrate; Forming a third insulating film on the entire surface of the semiconductor substrate; Forming a second conductive type second conductive layer on the third insulating film; A portion of the second conductive layer and the third insulating layer may be removed to expose an upper surface of the first gate and the first storage electrode, and a surface of the field oxide layer and the semiconductor substrate, and at the same time, on the first storage electrode. And forming a second gate on the remaining second insulating film and the third insulating film, and forming a second gate on the third insulating film of a predetermined portion. The method of claim 1, wherein after forming the second storage electrode and the second gate, Forming an LED region with a second conductivity type impurity ion in the semiconductor substrate near the lower end side of the first gate and the second gate; Forming sidewalls of an insulating material on side surfaces of the first gate, the second gate, the first storage electrode, and the second storage electrode; Forming a second conductivity type source / drain on a side surface of the semiconductor substrate connected to the LED region; And forming an interlayer insulating film in a sufficient thickness over the entire surface of the semiconductor substrate. The method of claim 1, wherein the first insulating film and the second insulating film are formed of a nitride film. 4. The method of claim 3, wherein the first insulating film is formed of a silicon oxide film. The method of claim 1, wherein the third insulating film is formed of an oxide film. The method of manufacturing a device of a semiconductor device according to claim 1, wherein the thickness of the third insulating film is different from that of the first insulating film. The method of claim 1, wherein the first gate, the first storage electrode, and the second gate and the second storage electrode are each formed by a photolithography process.