KR19990026694A - Manufacturing method of capacitor for semiconductor memory cell - Google Patents

Abstract

The present invention relates to a method of manufacturing a capacitor of a semiconductor memory cell. The capacitor forms a material layer on the semiconductor substrate on which the transistor is formed, and then forms contact holes in the material layer. Then, after forming the conductive material layer for the storage electrode of the capacitor in the contact hole and the material layer, the first etching process is performed using the first photosensitive film to form the unevenness in the conductive material layer. Then, the conductive material layer on which the irregularities are formed is separated into each storage electrode by using a second photosensitive film. Then, a dielectric film and a plate electrode are sequentially formed to manufacture a capacitor for a semiconductor memory cell. As such, in the present invention, the unevenness is formed in the conductive material layer for the storage electrode through the first etching process to maximize the surface area, and the conductive material layer having the unevenness formed in the unevenness is separated into the respective storage electrodes through the second etching process. Capacitors of area can be manufactured.

Description

Manufacturing method of capacitor for semiconductor memory cell

The present invention relates to a method for manufacturing a capacitor for a semiconductor memory cell, and more particularly, to a method for manufacturing a capacitor for an improved cylindrical semiconductor memory cell capable of further increasing an area.

In a semiconductor memory cell, in particular, a memory cell of DRAM (hereinafter referred to as DRAM) is composed of one pass transistor and one capacitor. Since the transistor serves as a switch for inputting / outputting data to and from the capacitor, and the capacitor serves as a warehouse for storing data, the capacity of the capacitor, that is, the capacitance of the capacitor, determines the storage capacity of the data. However, if the built-in capacitance is insufficient, an error occurs while storing and outputting data. In order to prevent such a data error, the DRAM performs a so-called refresh operation for restoring data after a predetermined time. Since the refresh operation depends on the capacity of the capacitor, increasing the capacity of the capacitor provides a fundamental factor in performing accurate data input / output while extending the refresh characteristic, that is, the storage time of the data. However, as the design rule of the memory device is highly integrated to 0.3 μm or less, the area of unit cells per chip is decreasing and the area where capacitors can be formed is decreasing. Therefore, as the memory device is highly integrated, it is very important in the art to increase the capacitance of a unit cell per unit area.

In general, the capacitance is proportional to the cross-sectional area where the storage electrode as the lower electrode and the plate electrode as the upper electrode are in contact with each other, and inversely proportional to the distance between the two electrodes. Therefore, increasing the surface area of the storage electrode in a small area can be said to increase capacitance. Accordingly, various manufacturing techniques for increasing the capacity of the capacitor in the same area have been studied. In order to realize the above object, a Capacitor Over Bit-line (COB) process that manufactures a capacitor on top of a bit line has begun to be used. In addition, in order to maximize the effect of the COB process to start to manufacture a three-dimensional capacitor. However, as described above, in the highly integrated semiconductor device of 0.3 μm or less, there is a problem that a capacitor of sufficient capacity cannot be manufactured even by the COB process. Due to these problems, the technical field has been trying to increase the area of the capacitor by using a hemispherical (Hemi Spherical Grain) silicon that applies the chemical properties of the conductive material used as the lower electrode of the capacitor. However, prior to using the hemispherical silicon, it is important to maximize the area of the capacitor to be performed first.

Accordingly, an object of the present invention is to provide a method for manufacturing a capacitor for a semiconductor memory cell having an improved three-dimensional structure that can further maximize the capacity of the capacitor.

1A through 1F are cross-sectional views sequentially illustrating a method of manufacturing a capacitor for a semiconductor memory cell according to a preferred embodiment of the present invention.

In order to achieve the above objects, the present invention includes forming a transistor comprising a gate insulating film, a gate electrode, a source and a drain region in a semiconductor substrate in which an active region and a field region are defined by a field oxide film; Forming a material layer on the semiconductor substrate and forming a contact hole to expose the source region by etching the material layer; Forming a conductive layer for the storage electrode, which functions as a lower electrode of the capacitor, in the contact hole and the material layer; Forming a first photoresist film on the conductive material layer; Partially etching the first photoresist film to form a pattern; Performing a first etching process of partially etching the conductive material layer using the patterned first photoresist film as a mask; Forming a storage electrode by forming a second photoresist layer on the etched conductive layer and then performing a second etching process; And forming a plate electrode functioning as a dielectric layer and an upper electrode of the capacitor in the storage electrode, thereby completing the capacitor.

Preferably, the field oxide film is formed by a conventional device isolation process, such as LOCal Oxidation Silicon (hereinafter referred to as LOCOS) or an improved LOCOS process. Preferably, the material layer is formed of a silicon oxide layer.

Also preferably, the first photoresist film forms openings at regular intervals between the first photoresist film so as to form irregularities in the conductive material layer formed below.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that the same elements in the figures are represented by the same reference numerals wherever possible. In addition, detailed descriptions of well-known functions and configurations that may unnecessarily obscure the subject matter of the present invention will be omitted.

1A to 1F are cross-sectional views sequentially illustrating steps of manufacturing a capacitor for a memory cell according to an exemplary embodiment of the present invention.

1A shows a step of forming a transistor and a contact hole. A field oxide film 102 is formed on the semiconductor substrate 100, and a gate insulating film 104 and a gate electrode 106 are formed in an active region defined by the field oxide film 102. Subsequently, impurities are implanted into the semiconductor substrate 100 using the gate electrode 106 as a self-aligned mask. As a result, the source 108 and the drain region 110 are formed. Subsequently, although not shown, a contact hole is formed in the drain region 110 to form a bit line, and then an interlayer insulating layer, for example, an oxide layer 112 is formed to cover the step formed by the bit line. Form. Subsequently, a photolithography process is performed on the oxide layer 112 to form a contact hole 114 exposing the source region 108.

FIG. 1B illustrates the steps of forming the spacer 116 and the conductive layer 118 for the storage electrode. After the insulating film is entirely formed on the semiconductor substrate 100 on which the contact hole 114 and the oxide film 112 are formed, etch back is performed. As a result, spacers 116 are formed on both sidewalls of the contact hole 114. The spacer 116 functions to prevent an electrical short between the gate and the bit line. Subsequently, a conductive material layer 118 for forming a storage electrode serving as a lower electrode of a capacitor is formed in the contact hole 114 and the oxide film 112 on which the spacer 116 is formed, for example, polycrystalline silicon doped with impurities. . Preferably, the conductive layer 118 is formed to a thickness of about 4000 kPa to 7000 kPa.

In FIG. 1C, a step of forming the first photosensitive film 120 is illustrated. The first photoresist layer is formed on the conductive layer 118, and is patterned by performing a photolithography process. In this case, the first photoresist layer 120 is patterned to form concavities and convexities in the conductive material layer 118 formed at a lower portion thereof. Referring to the drawings in more detail, the openings 122 are formed at regular intervals between the first photoresist layer 120. The first photoresist film 120 and the opening 122 are formed in a shape similar to that in which contact holes are continuously formed in an arbitrary material layer. Preferably, the thickness of the first photoresist layer 120 is somewhat thick in consideration of the amount of etching to be consumed in the subsequent dry etching process.

FIG. 1D illustrates a first etching step in which the conductive layer 118 is partially etched by the first photoresist layer 120. The conductive layer 118 formed at the lower portion is dry-etched through the opening 122 continuously formed with the first photoresist layer 120 interposed therebetween. Since the opening 122 functions as a self-aligned etching mask, the conductive layer 118 is etched at a portion corresponding to the position of the opening 122 to form irregularities as shown in the drawing. In this case, the etching amount of the conductive material layer 118 may be freely set as much as the depth to form the unevenness. As described above, in the present invention, the area of the storage electrode may be further increased by adjusting the etching amount of the conductive layer 118. At this time, the etching amount of the conductive material layer 118 is preferably set to the thickness or less of the first conductive material layer formed.

In FIG. 1E, the step of forming the second photoresist film is illustrated. The second photoresist layer 124 is formed on the conductive layer 118 where the unevenness is formed by partial etching due to the first photoresist layer 120 and the opening 122. Then, a photolithography process is performed on the second photoresist layer 124 to form a pattern. The second photoresist layer 124 and the opening 126 are formed by the photolithography process. The width of the storage electrode is determined by the second photoresist layer 124. In a subsequent process, the lower conductive layer 118 is etched through the opening 126 to be separated into each storage electrode.

Figure 1f shows a cross section of the second etching process and the finished capacitor. Dry etching is performed on the lower conductive layer 118 through the opening 126. In this case, all of the conductive layer 118 under the opening 126 is etched to separate each storage electrode. As a result, the conductive layer 118 is separated into respective storage electrodes 128 along the width of the second photosensitive film 124. Subsequently, a plate electrode 132 is sequentially formed on the storage electrode 128 and the oxide layer 112 using the dielectric layer 130 and the upper electrode of the capacitor to complete the capacitor.

In the above-described preferred embodiment of the present invention, the unevenness is formed in the conductive layer 118 by using the first photoresist film 120 in the first etching process step, and the second photoresist film 124 in the second etching process step. The uneven conductive layer 118 having the unevenness is separated into the respective storage electrodes by using.

However, in addition to the above-described embodiment, another preferred embodiment capable of forming irregularities in the storage electrode is proposed. This method will be briefly described without the accompanying drawings. Through the same process steps as in the above embodiment, a material layer having a contact hole is formed in the semiconductor substrate, and then a conductive material layer is formed. After that, a first photoresist film is formed on the conductive material layer, and an etching process is performed to pattern the storage electrode. Then, unevenness is formed on the patterned storage electrode using a second photoresist film, more specifically, a second photoresist film having a continuous and formed opening in the patterned conductive layer as a mask. Then, a dielectric film and a plate electrode are formed in the storage electrode in order to complete the capacitor.

As described above, the another embodiment may be realized by changing the order of the first etching process step and the second etching process step among the process steps of the embodiment.

As described above, in the present invention, after forming the first photosensitive film on the conductive material layer for the storage electrode, openings are formed in the first photosensitive film at regular intervals. Then, irregularities are formed by dry etching the conductive material layer through the openings. The unevenness maximizes the surface area of the storage electrode, resulting in an increase in the area of the capacitor.

Although described with reference to the preferred embodiment of the present invention as described above, those skilled in the art will understand that various modifications and changes can be made without departing from the spirit and scope of the present invention described in the claims below. Could be.

Claims (12)

Forming a transistor including a gate insulating film, a gate electrode, a source, and a drain region in a semiconductor substrate in which an active region and a field region are defined; Forming a material layer functioning as a planarization layer on the semiconductor substrate, and forming a contact hole exposing a source region in the material layer; Forming a conductive layer for a storage electrode of a capacitor in the contact hole and the material layer; Forming a first photoresist film on the conductive material layer and then patterning the first photoresist film; Performing a first etching process on the conductive material layer through the patterned first photoresist film; Forming a second photosensitive film on the etched conductive material layer, and etching the conductive material layer through the second photosensitive film to separate the respective storage electrodes; And forming a dielectric film and a plate electrode of the capacitor on the storage electrode to complete the capacitor. The method of claim 1, wherein the first photoresist film has openings formed at regular intervals to form concavities and convexities in the conductive material layer formed below. The method of claim 1, wherein the first photoresist layer is patterned in various modified forms so as to form irregularities or bends in the conductive material layer. The method of claim 1, wherein the conductive layer is formed with irregularities in a first etching process step. The method of claim 1, wherein the conductive material layer is partially etched through a first etching process. The method of claim 1, wherein the conductive material layer is patterned to be separated into respective storage electrodes through a second etching process. Forming a transistor including a gate insulating film, a gate electrode, a source, and a drain region in a semiconductor substrate in which an active region and a field region are defined; Forming a material layer functioning as a planarization layer on the semiconductor substrate, and forming a contact hole exposing a source region in the material layer; Forming a conductive layer for a storage electrode of a capacitor in the contact hole and the material layer; Forming a first photoresist film on the conductive material layer and then patterning the first photoresist film; Performing a first etching process on the conductive material layer through the patterned first photoresist layer to separate the storage electrodes into respective storage electrodes; Forming and patterning a second photoresist film on each of the etched and separated storage electrodes, and then performing a second etching process on the storage electrodes through the second photoresist film; And forming a dielectric film and a plate electrode of the capacitor on the storage electrode to complete the capacitor. The method of claim 7, wherein the conductive material layer is patterned to be separated into respective storage electrodes through a first etching process. The method of claim 7, wherein the second photoresist film has openings formed at regular intervals to form irregularities in the storage electrode. The method of claim 7, wherein the second photoresist layer is patterned in various modified shapes to form irregularities and bends in the storage electrode. The method of claim 7, wherein the conductive material layer is formed with irregularities in a second etching process step. 8. The method of claim 7, wherein the conductive material layer is partially etched through a second etching process.