KR19990024470A - Non-volatile memory device for high speed rewriting and manufacturing method thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile memory device for fast rewriting and a method of manufacturing the same. In particular, the unit cell of the nonvolatile memory device includes a select transistor having a drain connected to a bit line, a gate connected to a word line, and a source, and the select transistor. A drain connected to the source of the cell, a floating gate that accumulates channel injection electrons, a control gate connected to the sense line, a cell transistor having a source, a drain connected to the source of the cell transistor, a gate connected to the control line, a source connected to a common ground line It characterized in that it comprises a control transistor having a.

Description

Non-volatile memory device for high speed rewriting and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile memory device, and more particularly, to a nonvolatile memory device for a fast rewrite capable of selectively programming a memory cell without erasing the entire memory cell.

In general, in a nonvolatile memory device, since EEPROM can be newly changed and programmed, the EEPROM is mainly used to construct a program in consideration of a change in data or a matching with a system.

1 is a circuit diagram illustrating a conventional EEPROM type nonvolatile memory device, in which a unit cell of an EEPROM is connected to a drain and a word line (W / L) connected to a bit line (B / L), as shown in FIG. A select transistor having a gate and a source; a floating gate and a gate connected to the source of the select transistor; and a control gate and a common ground line connected to the sense line S / L. It consists of a cell transistor (sense tr) having a source connected to it.

The nonvolatile memory device configured as described above has the structure of a semiconductor device as described below with reference to FIGS. First, the cell transistor includes a channel impurity implantation region 8 in which channel impurities are implanted under a select region of the silicon substrate 2 having the device isolation region 4 for isolation between elements, and the substrate 2. A tunnel oxide film 10 obtained by selectively etching the gate oxide film 6 formed on the upper surface of the active region, and a first conductive layer that is sequentially stacked on the upper surface of the gate oxide film 6 including the tunnel oxide film 10, that is, floating A gate composed of a gate 12, an inter-gate insulating film 14 and a second conductive layer, that is, a control gate 16, and a substrate 2 near the surface of the substrate 2 so as to self-align to an edge of the gate; Source / drain regions 19 and 20 into which other impurities are implanted. In addition, the selection transistor is formed on the upper surface of the active region of the silicon substrate 2 at the same time as the inter-gate insulating film 14 of the cell transistor is formed, and the buffer oxide film 15 is formed in accordance with the gate mask 17 '. A source / drain region in which a second conductive layer, that is, the gate 17 and other impurities are implanted in the vicinity of the surface of the substrate 2 so as to self-align to the edge of the gate 17. (18, 19). Here, 18 is a bit line is formed in the wiring process, 20 is a common ground line is formed in the wiring process. In addition, a word line connecting the memory cell array is formed at the gate 17 of the selection transistor, and a sense line connecting the memory cell array is formed at the control gate 16 of the cell transistor.

1 to 4, program and erase operations of the nonvolatile memory device are as follows. When the 16V is applied to the sense line S / L and the word line W / L and 0V is applied to the bit line B / L when the data of the memory cell is erased, the select ground is selected. On, the cell transistor (sense tr) is off. Accordingly, the cell transistor (sense tr) accumulates electrons in the floating gate 12 and holes are accumulated in the surface of the substrate 2 under the floating gate 12. In addition, when 0V is applied to the sense line S / L and 16V is applied to the bit line B / L and the word line W / L when the memory cell is programmed, and the common ground line is floated, the select transistor and The cell transistor sense tr is turned on. As a result, the floating gate 12 of the cell transistor (sense tr) emits accumulated electrons to form a channel.

However, in the nonvolatile memory device, when the first memory cell A is programmed and the second memory cell B in the off state is rewritten (on), the first bit line B / L1 and the second bit line may be used. A current path through the common ground line is formed between (B / L2). As a result, the second memory cell 20 may no longer emit electrons to the floating gate of the cell transistor sense tr21 due to the voltage drop of the second bit line B / L2. Cause

In order to solve such a program failure, the nonvolatile memory device erases all the memory cell arrays and then programs only the selected memory cells, which is a hassle of erasing the entire memory cell array every time the data is rewritten. There was this.

SUMMARY OF THE INVENTION An object of the present invention is to provide a control transistor for blocking a current path through a common ground line between memory cells in order to solve the above-mentioned problems of the prior art, thereby reducing the programming time of a selected memory cell. The present invention provides a volatile memory device and a method of manufacturing the same.

In order to achieve the above object, the present invention provides a unit cell of a nonvolatile memory device, comprising: a selection transistor having a drain connected to a bit line, a gate connected to a word line, and a source; A cell transistor having a drain connected to a source of the selection transistor, a floating gate for accumulating channel injection electrons, a control gate connected to a sense line, and a source; And a control transistor having a drain connected to a source of the cell transistor, a gate connected to a control line, and a source connected to a common ground line.

According to an aspect of the present invention, there is provided a method of manufacturing a nonvolatile memory device, including applying a first insulating film to an upper surface of a semiconductor substrate, and then implanting impurities into a selected region; Selectively etching the first insulating film to form a tunnel insulating film; Sequentially forming a first conductive layer and a second insulating film on the resultant upper surface; Forming a floating gate insulated from a surface of a cell transistor that performs a program and erase function on an upper surface of the tunnel insulating layer; Forming a second conductive layer on the entire surface of the substrate; Forming a control gate of a cell transistor on an upper surface of the floating gate while simultaneously forming a gate of a control transistor that blocks current between a selection transistor and another cell on the upper surface of the substrate; And simultaneously forming impurity regions near the surface of the substrate so as to self-align the edges of the gate.

1 is a circuit diagram showing a conventional EEPROM type nonvolatile memory device.

2 is a diagram showing a layout of a conventional EEPROM type nonvolatile memory device.

3 is a cross-sectional view illustrating a structure of a nonvolatile memory device along the line X-X 'of FIG.

4 is a cross-sectional view illustrating a structure of a nonvolatile memory device along the line Y-Y 'of FIG.

5 is a circuit diagram illustrating a nonvolatile memory device according to an embodiment of the present invention.

6 illustrates a layout of a nonvolatile memory device in accordance with an embodiment of the present invention.

FIG. 7 is a cross-sectional view illustrating a structure of a nonvolatile memory device along the line X-X 'of FIG. 6; FIG.

FIG. 8 is a cross-sectional view illustrating a structure of a nonvolatile memory device along the line YY ′ in FIG. 6. FIG.

9 to 12 are process flowcharts taken along line X-X 'of FIG. 6 for explaining a method of forming a nonvolatile memory device according to the present invention.

13 to 16 are process flowcharts taken along line Y-Y 'of FIG. 6 for explaining a method of forming a nonvolatile memory device according to the present invention.

Explanation of symbols for the main parts of the drawings

100: silicon substrate 102: device isolation region

104: gate oxide film 106: impurity implantation region for channel

108: tunnel oxide film 110: floating gate of cell transistor

112: inter-gate insulating film 113: buffer oxide film

114: gate of cell transistor

115: gate of select transistor

116: gate of the control transistor

118: bit line 121: common ground line

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

FIG. 5 is a circuit diagram illustrating a nonvolatile memory device according to an embodiment of the present invention, wherein a unit cell includes a drain connected to a bit line (B / L), a gate connected to a word line (W / L), and a source. A select transistor having a select tr, a drain connected to a source of the select transistor, a floating gate for accumulating channel injection electrons, a control gate connected to a sense line S / L, and a cell transistor having a source and a control transistor having a drain connected to the source of the cell transistor sense tr, a gate connected to the control line C / L, and a source connected to the common ground line.

6 is a diagram illustrating a layout of a nonvolatile memory device according to an embodiment of the present invention, where 115 'is a gate mask of a select transistor, 108 is a mask for forming a tunnel oxide region of a cell transistor, and 110' A floating gate mask of the cell transistor, 114 'is a control gate mask of the cell transistor, 116' is a gate mask of the control transistor, and 124 is a contact region for forming a bit line.

FIG. 7 is a cross-sectional view illustrating the structure of the nonvolatile memory device along the line X-X 'of FIG. 6, and FIG. 8 is a cross-sectional view illustrating the structure of the nonvolatile memory device along the line Y-Y'.

6 to 8, the device of the nonvolatile memory device according to the present invention has the following structure. First, the cell transistor includes a gate oxide film 104 formed on the upper surface of the active region of the silicon substrate 100 having the device isolation region 102 formed therebetween, and impurities selected for the channel in the selected region of the substrate 100. The impurity implantation region 106 for the implanted channel, the tunnel oxide film 108 in which the gate oxide film 104 is selectively etched, and the gate oxide film 104 including the tunnel oxide film 108 are sequentially stacked. A gate including a first conductive layer, that is, a floating gate 110, an inter-gate insulating layer 112, and a second conductive layer, that is, a control gate 114, and a surface of the substrate 100 so as to self-align to an edge of the gate. The source / drain regions 119 and 120 into which the substrate 100 and other impurities are injected are provided. In addition, the selection transistor is formed on the upper surface of the active region of the substrate 100 at the same time as the formation of the inter-gate insulating film 112 of the cell transistor and the buffer oxide film 113 according to the gate mask 115 ′. Source / drain in which impurities other than the substrate 100 are implanted near the surface of the substrate 100 so as to self-align the second conductive layer formed on the second conductive layer, that is, the gate 115 and the edge of the gate 115. Regions 118 and 119. The control transistor may be configured to self-align the second conductive layer formed on the top surface of the buffer oxide layer 113, that is, the gate 116 and the edge of the gate 115, according to a gate mask 116 ′. 100 and source / drain regions 120 and 121 in which impurities other than the substrate 100 are implanted are provided near the surface. In the subsequent wiring process, a bit line is formed at 118 and a common ground line is formed at 121. In the subsequent wiring process, the gate 115 of the selection transistor is a word line connecting the memory cell array, the control gate 114 of the cell transistor is a sense line connecting the memory cell array, and the gate 116 of the control transistor. ) Are respectively formed control lines connecting the memory cell arrays.

According to the present invention having the structure as described above, the current path between the memory cells through the regioxy common ground line is blocked by the control transistor. For example, when the second memory cell B is to be rewritten (on) after programming the first memory cell A, the second memory cell B is applied with a voltage applied from the control line C / L1. The control transistor control tr21 is turned off to block the current path of the first memory cell A through the common ground line. As a result, the second memory cell B can stably maintain the program as the voltage applied from the second bit line B / L2 is used to emit accumulated electrons of the floating gate in the cell transistor sense tr21. Is performed.

Therefore, according to the present invention, since the control transistor is turned off by electrically applying the control voltage to the control line C / L of the memory cell to electrically separate the bit line and the common ground line, the entire memory cell is erased. It is possible to selectively rewrite the memory cells without doing so.

9 to 12 are process flowcharts taken along line X-X 'of FIG. 6 for explaining a method of forming a nonvolatile memory device according to the present invention, and FIGS. 13 to 16 are views of the nonvolatile memory device according to the present invention. It is a process flowchart by the Y-Y 'line | wire of FIG. 6 for demonstrating the formation method. Referring to the drawings, a method of manufacturing a nonvolatile memory device according to the present invention is as follows.

First, as shown in FIGS. 9 and 13, a device isolation region 103 is formed in the silicon substrate 102 for isolation between devices using a conventional locus process. Subsequently, after the gate oxide film 104 is coated on the upper surface of the substrate 102 as a first insulating film, channel impurity implantation regions 106 are formed by ion implanting channel impurities into the selected region. Subsequently, the gate oxide layer 104 is selectively etched by a photo and etching process to form the tunnel oxide layer 108. Subsequently, a polysilicon layer as a first conductive layer and an oxide film / nitride film / oxide film as a second insulating film are sequentially stacked on the upper surface of the gate oxide film 104.

10 and 14, the stacked oxide film / nitride film / oxide film and the polysilicon layer are selectively etched by the photolithography and etching processes according to the floating gate mask 110 ′ of the cell transistor to form a floating gate of the cell transistor ( After forming the inter-gate insulating film 112 and the first gate oxide film 104 that is not necessary, the first gate oxide film 104 is removed.

Then, as shown in FIGS. 11 and 15, an oxidation process is performed on the entire surface of the resultant to perform surface oxidation on the upper side of the floating gate 110 of the cell transistor, and at the same time, a buffer oxide film ( 113).

Next, as shown in FIGS. 12 and 16, polysilicon is coated on the upper surface of the buffer oxide layer 113 as a second conductive layer. The polysilicon layer is etched by the photolithography and etching processes using the control gate mask 114 ′ of the cell transistor, the gate mask 115 ′ of the selection transistor, and the gate mask 116 ′ of the control transistor. Accordingly, the gate 115 of the selection transistor and the gate 116 of the control transistor are formed on the top surface of the buffer oxide layer 113, and the control gate 114 of the cell transistor is formed on the top surface of the inter-gate insulating layer 112. Is formed.

Subsequently, the gate 100 is used as a mask to ion implant the substrate 100 and other impurities to simultaneously form the source / drains 118, 119, 120, and 121 that are self-aligned at the edges of the gates. Subsequently, as the contact process is performed, a bit line contact electrode is formed at 118, and a contact electrode for a common ground line is formed at 121. Subsequently, as a wiring process is performed, a sense line connecting the memory cells is formed at 114, a word line connecting the memory cells at 115, and a control line connecting the memory cells at 116.

Therefore, since the present invention includes a control transistor between the cell transistor and the common ground, the current path between the memory cells is blocked by the control transistor turned off without erasing all the memory cells as in the conventional reprogramming of the memory cell array. Fast writing of the selected memory cells becomes possible.

In the present invention, since the memory cell can be selectively programmed quickly, the rewrite time is significantly shorter than before, and the power consumption of the nonvolatile memory can be greatly reduced.

Claims (14)

In a unit cell of a nonvolatile memory device, A select transistor having a drain connected to the bit line, a gate connected to the word line, and a source; A cell transistor having a drain connected to a source of the selection transistor, a floating gate for accumulating channel injection electrons, a control gate connected to a sense line, and a source; And And a control transistor having a drain connected to a source of the cell transistor, a gate connected to a control line, and a source connected to a common ground line. The nonvolatile memory device of claim 1, wherein the control transistor is turned off by a voltage applied from the control line when data is written. The nonvolatile memory device of claim 1, wherein the selection transistor has a single gate. The nonvolatile memory device of claim 1, wherein the control transistor includes a single gate. The non-volatile memory device of claim 1, wherein the selection transistor includes a multilayer stacked gate. The non-volatile memory device of claim 1, wherein the control transistor includes a multilayer stacked gate. In the method of manufacturing a nonvolatile memory device, Applying a first insulating film to the upper surface of the semiconductor substrate, and implanting impurities into the selected region; Selectively etching the first insulating film to form a tunnel insulating film; Sequentially forming a first conductive layer and a second insulating film on the resultant upper surface; Forming a floating gate insulated from a surface of a cell transistor that performs a program and erase function on an upper surface of the tunnel insulating layer; Forming a second conductive layer on the entire surface of the substrate; Forming a control gate of a cell transistor on an upper surface of the floating gate while simultaneously forming a gate of a control transistor that blocks current between a selection transistor and another cell on the upper surface of the substrate; And And simultaneously forming impurity regions in the vicinity of the surface of the substrate so as to self-align the edges of the gates, respectively. 8. The method of claim 7, wherein the first conductive layer and the second conductive layer are formed of polycrystalline silicon implanted with impurities. 8. The method of claim 7, wherein the first insulating film is an oxide film. 8. The method of claim 7, wherein the second insulating film is formed by sequentially stacking oxide films / nitride films / oxide films. In the method of manufacturing a nonvolatile memory device, Applying a first insulating film to the upper surface of the semiconductor substrate, and implanting impurities into the selected region; Selectively etching the first insulating film to form a tunnel insulating film; Sequentially forming a first conductive layer, a second insulating film, and a second conductive layer on the resultant upper surface; Forming a gate of a cell transistor on an upper surface of the tunnel insulating film and simultaneously forming a gate of a control transistor on the upper surface of the first insulating film to cut off currents of a selection transistor and another cell; And And simultaneously forming impurity regions in the vicinity of the surface of the substrate so as to self-align the edges of the gates, respectively. 12. The method of claim 11, wherein the first conductive layer and the second conductive layer are formed of polycrystalline silicon implanted with impurities. 12. The method of claim 11, wherein the first insulating film is an oxide film. 12. The method of claim 11, wherein the second insulating film is formed by sequentially stacking oxide films / nitride films / oxide films.