KR19990020379A - Flash memory cell array - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

The present invention relates to a flash memory cell array, and to a flash memory cell array in which the same voltage is applied to a source and a well.

2. Technical problem to be solved by the invention

In the conventional flash memory cell array structure in which the same voltage is applied to the source and the well, since the contact portion of the well is located outside the cell array region, the voltage applied to the well is equal to a time constant even if the same voltage is applied to the source and the well. RC) Depending on the delay factor, it is in a different state from the source signal in the center of the cell array. This is to improve the reliability of the device by preventing voltage fluctuations and malfunction of the device.

3. Summary of the Solution of the Invention

The present invention forms a well contact portion between drain contacts near the source contact portion repeatedly formed every 8, 16 or 32 cells so that the source and the well voltage state is always the same in any part of the cell array.

4. Important uses of the invention

All semiconductor devices with the same voltage applied to the source and well.

Description

Flash memory cell array

The present invention relates to a flash memory cell array, and more particularly, to a flash memory cell array in which the same voltage is applied to a source and a well.

Generally, flash memory cells perform electrical read, program, and erase operations. The read operations include VG = 2 to 7V, VS = VB = 0V, and VD = 0.1 to 2.0V. The program operation is programmed by injecting a hot electron into the floating gate 22 generated under the conditions of VG = 7-15V, VS = VB = 0V, VD = 3-10V, and erase operation. Is conducted under the conditions of VG = -7 ~ -15V, VS = 3-10V, VB = 0V, where drain 24 is in an electrically floating state (where VG is the voltage applied to the control gate , VS is the voltage applied to the source, VD is the voltage applied to the drain, and VB is the voltage applied to the well). The erase operation is performed by the electrons of the floating gate flowing out to the source through the tunnel oxide film between the floating gate and the source. In this case, when the voltage of VB is increased, electrons are emitted from the floating gate to the well as well as the source, which is advantageous in improving the reliability of the device, and thus, the same voltage as the source voltage can be applied to the well during the erase operation.

Recently, in order to realize high integration of a flash memory cell array, an area occupied by each element constituting the cell array is reduced to the maximum. However, in the related art, since well contact portions are formed outside the cell array region in order to apply voltage to the wells, they act as a factor of inhibiting high integration.

1 is a layout diagram of a conventional flash memory cell array, FIG. 2 (a) is a cross-sectional view of a flash memory cell formed in a P-well structure applied to the cell array of FIG. 1, and FIG. 2 (b) is a cell array of FIG. 3 is a cross-sectional view of a flash memory cell formed in a triple P-well structure applied to the present invention, and FIG. 3 is a plan view illustrating a well contact portion located outside the cell array region of FIG. 1, with reference to these drawings. FIG. Will be described.

A plurality of field oxide films 21 are formed on the P-type semiconductor substrate 10 on which the triple P-well 1 or the triple N-well 11 including the common P-well 1 is formed. Define the active area. The plurality of field oxide films 21 are arranged in accordance with a predetermined rule in the longitudinal and transverse directions.

Floating gates 22 are formed such that portions of the plurality of field oxide films 21 overlap each of the adjacent pick oxide films 21, and the floating gates 22 are spaced apart from each other by the out-of-field oxide films 21. A plurality of cells are arranged in the entire cell array region 30 to be formed. The tunnel oxide film 2 is formed between the floating gate 22 and the general P-well 1.

The control gate 23 used as a word line is formed in a line shape so as to pass above the floating gates 22 and the field oxide films 21 arranged in the transverse direction among the plurality of floating gates 22. A plurality of control gates 23 are formed in the entire cell array region 30. The dielectric film 3 is formed between the control gate 23 and the floating gate 22.

A drain 24 is formed in each common P-well 1 between two floating gates 22 formed between neighboring field oxide films 21, and each group includes 8, 16 or 32 cells. In this case, the drain 24 is not formed at the boundary of each group, and the source 25 is formed in the form of a line in the general P-well 1 of the outer space of each of the two floating gates 22. . The source 25 in a line form the same direction as the control gate 23 in the form of a line, and a plurality of sources 25 are formed in the entire cell array region 30.

The source contact portions 28 are repeatedly formed in each of the plurality of sources 25 for every eight, sixteen, or thirty-two cells, and the drain contact portions 27 are formed in each of the plurality of drains 24.

The bit line 26 is formed to be connected to the drain 24 through the drain contact part 27. One bit line 26 is formed of drain contact parts (eg, arranged in a longitudinal direction among the plurality of drain contact parts 27). 27) and a plurality of bit lines 26 are formed in the entire cell array region 30 so as to intersect with the control gate 23 in the form of a line. The source line 29 is formed to be connected to the source 25 through the source contact part 28. One source line 29 is formed of source contact parts arranged in the longitudinal direction among the plurality of source contact parts 27 ( 28 is formed above the plurality of source lines 29 are formed in the entire cell array region 30 in the same direction as the bit lines 26. Each source line 29 is regularly arranged every eight, sixteen, or thirty-two cells according to design rules, and eight, sixteen, or thirty-two between source lines 29 and neighboring source lines 29 are arranged regularly. Bitlines 26 are arranged regularly.

A well contact portion 31 for applying a voltage to the P-well 1 is formed outside the cell array region 30.

In the conventional flash memory cell array of the above structure, since the well contact portion 31 is located outside the cell array region 30, even if the same voltage is applied to the source 25 and the P-well 1, The voltage applied to the well 1 is different from the source signal at the center of the cell array according to the time constant (RC) delay element. This causes a change in voltage and malfunction of the device, and also makes it difficult to realize high integration of the device.

Therefore, in the flash memory cell array in which the same voltage is applied to the source and the well, the present invention forms a well contact portion inside the cell array region so that the voltage state of the source and the well is always the same in any part of the cell array. It is an object of the present invention to provide a flash memory cell array that can improve the reliability.

In order to achieve the above object, the present invention uses a flash memory cell including a floating gate, a control gate, a source, and a drain as a unit cell on a well-formed semiconductor substrate, and a source line for applying a voltage to the source through a source contact is formed. And a bit line for applying a voltage to a drain through a drain contact portion, and a well contact portion formed at an outer portion of the cell array to apply a voltage to the well, wherein the well contact portion is formed from the source contact. It is formed between the drain contact portion near the portion, characterized in that the source line connected to the source contact portion is configured to be connected to the well contact portion.

1 is a layout diagram of a conventional flash memory cell array.

FIG. 2A is a cross-sectional view of a flash memory cell formed in a P-well structure applied to the cell array of FIG.

FIG. 2B is a cross-sectional view of the flash memory cell formed in the triple P-well structure applied to the cell array of FIG.

3 is a plan view of a well contact located outside the cell array region of FIG.

4 is a layout diagram of a flash memory cell array in accordance with the present invention.

FIG. 5A is a cross-sectional view of a flash memory cell formed in a general well structure taken along the line X-X of FIG. 4; FIG.

FIG. 5B is a cross-sectional view of the flash memory cell formed in the triple P-well structure cut along the X-X line of FIG.

Explanation of symbols for the main parts of the drawings

1 and 61: general well 2 and 62: tunnel oxide film

3 and 63: dielectric film 10 and 70: semiconductor substrate

11 and 71: triple wells 21 and 41: field oxide films

22 and 42: floating gate 23 and 43: control gate (wordline)

24 and 44: drain 25 and 45: source

26 and 46: bit lines 27 and 47: drain contact portion

28 and 48 source contacts 29 and 49 source lines

30 and 80: cell array regions 31 and 51: well contacts

50: mask for well pickup 52: well pickup

64: interlayer insulating film

FIG. 4 is a layout diagram of a flash memory cell array according to the present invention. FIG. 5 (a) is a cross-sectional view of a flash memory cell formed in a general well structure taken along the line XX of FIG. 4, and FIG. A cross-sectional view of a flash memory cell formed in a triple P-well structure cut along the line XX of FIG. 4 will be described in detail with reference to these drawings.

A plurality of field oxide films 41 are formed in the semiconductor substrate 70 on which the general well 61 or the triple well 71 including the general well 61 is formed to define an active region. The plurality of field oxide films 41 are arranged in accordance with a predetermined rule in the longitudinal direction and the transverse direction. The semiconductor substrate 70 contains a first conductive impurity, the triple well 71 is formed by injecting a second conductive impurity of a type opposite to the first conductive impurity, and the general well 61 is formed of the second conductive impurity. It is formed by injecting a third conductive impurity of a type opposite to the impurity.

The floating gate 42 is formed so that a part of each of the field oxide films 41 out of the plurality of field oxide films 41 overlaps, and the floating gates 42 are spaced apart from each other between the out field oxide films 41. A plurality of cells are arranged in the entire cell array region 80 to be formed. A tunnel oxide layer 62 is formed between the floating gate 42 and the general well 61.

The control gate 43 used as a word line is formed in a line shape so as to extend above the floating gates 42 and the field oxide films 41 arranged in the transverse direction among the plurality of floating gates 42. A plurality of control gates 43 are formed in the entire cell array region 80. A dielectric film 63 is formed between the control gate 43 and the floating gate 42.

When eight, sixteen, or thirty-two cells are arranged in one group, every common well 61 between two floating gates 42 formed between the field oxide films 41 out of the cells included in each group. The drain 44 is formed in each of the wells, and the well pick-up regions 52 are formed in each of the general wells 61 at the boundary portions of each group, and the general wells in the outer space portions of each of the two floating gates 22 61, a source 45 is formed in a line form. The source 45 in the form of a line forms the same direction as the contact roll gate 43 in the form of a line, and a plurality of sources 45 are formed in the entire cell array region 80. The drain 44 and the source 45 are formed by implanting a fourth conductive impurity of a type opposite to the third conductive impurity by an ion implantation process using a drain / source mask (not shown), and the well pick-up region 52 is In the ion implantation process using the well pickup mask 50, a fifth conductive impurity of the opposite type to the fourth conductive impurity is implanted.

A plurality of source contact portions 48 are formed in each of the plurality of sources 45 every 8, 16, or 32 cells, and each of the plurality of well pick-up regions 52, like the source contact portion 48, includes eight, The well contact portion 51 is repeatedly formed every 16 or 32 cells, and the well contact portion 51 is formed to be longitudinally aligned with the source contact portion 48, and each of the plurality of drains 44 is drained. The contact portion 47 is formed. The bit line 46 is formed to be connected to the drain 44 through the drain contact part 47, and one bit line 46 may include drain contact parts (eg, longitudinally arranged ones of the plurality of drain contact parts 47). 47) and a plurality of bit lines 46 are formed in the entire cell array region 40 so as to intersect the control gate 43. The source line 49 is connected to the source 45 through the source contact portion 48 and simultaneously connected to the well pick-up region 52 through the well contact portion 51. Is formed above the source contacts 28 and the well contacts 27 arranged in the longitudinal direction among the plurality of source contacts 27 and the well contacts 51, and the source line 49 is a bit. A plurality of cells are formed in the entire cell array region 80 in the same direction as the line 46. Each source line 49 is regularly arranged every eight, sixteen, or thirty-two cells according to design rules, and eight, sixteen, or thirty-two between source lines 49 and neighboring source lines 49. Bitlines 46 are arranged regularly.

In the above, when the first conductive impurity is P-type, the second conductive impurity is N-type, the third conductive impurity is P-type, the fourth conductive impurity is N-type, and the fifth conductive impurity is P-type. Type. On the other hand, when the first conductive impurity is N-type, the second conductive impurity is P-type, the third conductive impurity is N-type, the fourth conductive impurity is P-type, and the fifth conductive impurity is N-type. Type.

As described above, according to the present invention, when the same voltage is applied to the source and the well through the source line by simultaneously connecting the source and the well pick-up region to the source line through the source contact portion and the well contact portion, respectively, the cell array region It is possible to keep the source and well voltages always in the same state at any part of the circuit, reducing the time constant (RC) delay factor to prevent voltage fluctuations and device malfunctions, thereby increasing device reliability and improving device integration. It can be realized.

Claims (1)

A flash memory cell composed of a floating gate, a control gate, a source, and a drain is formed as a unit cell on a well-formed semiconductor substrate, and a source line for applying a voltage to the source is formed through the source contact, and a voltage is applied to the drain through the drain contact. A flash memory cell array in which a bit line for applying is formed and a well contact portion is formed outside of the cell array to apply a voltage to the well. And forming the well contact portion between the drain contact portion near the source contact portion, and the source line connected to the source contact portion to be connected to the well contact portion.