KR19990017546A - Decoder of turbo encoder - Google Patents

Abstract

The present invention is to provide a decoder of a turbo encoder for utilizing the repetitive effects of information, which is a decoder 1 for decoding a signal corresponding to an information bit and one signal corresponding to a depunctured parity bit, and from the decoder 1 A combiner divider for combining the repeated signals and distributing them into signals having the same value, an interleaver for interleaving the signal from the combiner, and a decoder for decoding another signal corresponding to the signal and parity bits from the interleaver. And a deinterleaver for deinterleaving the signal from the decoder 2, a combiner for combining the signal from the deinterleaver, and a hard determiner for determining the signal from the combiner to be 0 or 1.

Description

Decoder of turbo encoder

1 is a diagram showing the basic structure of a turbo encoder;

2 is a diagram showing the basic structure of a decoder of a turbo encoder;

3 is a view showing the structure of a turbo encoder using a repeater;

4 is a diagram showing the structure of a turbo code decoder of the present invention.

Explanation of symbols for main parts of the drawings

410,440 Decoder 420,460 Combined divider

430: interleaver 450: deinterleaver

470: combiner 480: hard judge

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decoder of a turbo encoder, and more particularly to a decoder having a repetitive effect of information.

Turbo codes are currently being studied as error correction codes for next generation mobile communication. The performance of the turbo code is known to be superior to that of convolutional codes, which are widely used in the current mobile communication environment. The basic structure of such a turbo code is shown in FIG.

The turbo code has a structure in which two simple RSC (recursive systematic convolutional) coders, which make a parity symbol using an input composed of frames of N information bits, are connected in parallel as shown in FIG. As shown in Fig. 1, the turbo encoder sets the information bit 101 to one output? _K 101, passes the information signal 101 through the RSC encoder 100 to obtain Y _1k 102, and the information signal 101. ) Is passed through an interleaver (110) having the same size as a frame of N information bits, and passes through another RSC encoder (120) to obtain Y _2k (104).

Therefore, the turbo code output has dual parity information due to the output of the RSC encoder as well as the output modified through the interleaver. However, in order to obtain a desired code rate in the turbo encoder, the Y _1k 102 and Y _2k 104 are punctured through the output signal. For example, to set the code rate to 1/2, you need to puncture Y _1k and Y _2k alternately. In this way, the finally obtained parity bit Y _k 105 is transmitted together with X _k .

To decode codewords encoded by the turbo code, a decoder as shown in FIG. 2 is connected in series and decoded. Each of these decoders must have an input having a value other than 0 or 1, i.e. a soft input, having a value other than 0 or 1, i.e. a soft output. Typically, these decoders use a maximum a posteriori (MAP) and soft output Viterbi algorithms (SOVA) decoder. However, the performance is known to be better MAP decoder.

Unlike the decoder of the multilevel encoder such as conventional concatenated codes, the turbo coder exchanges additional information between the two decoders so that decoding can be repeatedly performed. And as the number of iterations increases, performance also improves.

This decoder is shown in FIG. First, when x _k 201 and y _k 202 are signals through which a codeword of a turbo encoder as shown in FIG. 1 passes through a channel, x _k is a signal through which information bits pass through the channel, and y _k is The parity bit is the signal that passed through the channel. First, the parity bit 203 corresponding to the RSC encoder 1 (100) is decoded by depuncturing the received parity signal y _k (202) to the decoder 1 (210), and the parity bit corresponding to the RSC encoder 2 (120). 204 sends to decoder 2 230. First, decoder 1 210 decodes using x _k 201 and y _k 203 and then deinterleaves output 205 of decoder 1 210 and y _2k ( Decode by the decoder 2 (230) using the (204). In this case, when repeated decoding is not desired, the output signal 207 of the decoder 2 230 is deinterleaved, and the hard decision signal 208 is output as a decoding signal through the hard decision unit 250. However, in order to perform repeated decoding, the signal 209 deinterleaved the output signal 208 of the decoder 2 and the received signal x _k 201 and y _1k 203 are decoded back to the DEC1 210. This iterative decoding can be done until the desired performance is achieved.

Factors that determine the performance of the turbo code include the structure of the RSC code, the interleaver structure and size, the decoding method and the number of decoding. In order to obtain the structure of the RSC code that shows the best performance, it can be obtained through trial and error through simulation. The decoder is known to have the best performance of the MAP decoder. Also, the larger the interleaver is, the better the random interleaver is. Since the interleaver is one frame or one block unit in the turbo code, the size of the interleaver is equal to the size of one frame. However, when transmitting low speed voice or data, the size of the interleaver is reduced because the number of bits per frame is small. Therefore, it is difficult to obtain good performance due to the small size of the interleaver.

In order to solve this problem, a turbo encoder having the structure as shown in FIG. 3 has been devised. This coder is characterized by the basic structure of the structure that can achieve the desired performance by using a sufficiently large interleaver and the interleaving of low-speed information repeatedly to match the data rate of the basic structure. The operation of the encoder is the same as that of FIG. 1 except for the operation of the iterator. The decoder of the encoder as shown in FIG. 3 can be used as the decoder as shown in FIG. However, there is a disadvantage in that the effects of repetition are not used at all.

Therefore, the present invention devised a decoder considering the effects of the above information repetition. The structure of such a decoder is shown in FIG.

A decoder distributer 420 is provided between the decoder 1 410 and the interleaver 430, and the additional information signal obtained by deinterleaving the output signal of the decoder 2 440 is passed to the input of the DEC1. Decode through a combiner before hard decision on the use and final output signal.

The operation of this decoder is as follows. First, by depuncturing the signal 402 corresponding to the parity bit among the signals passing through the channel, the parity bit 403 corresponding to the RSC encoder 1 320 is the decoder 1 410, and the RSC encoder 2 ( The parity bit 404 corresponding to 330 is sent to the decoder 2 440. First, the decoder 1 410 decodes the signal 401 corresponding to the information bit and the signal 403 corresponding to the parity bit. At this time, the output signal 405 is a signal in which the repeated signals 301 are decoded by DEC1 when the number of repetitions of the repeater 300 of FIG. 3 is n. Accordingly, the n signals repeated in the combiner divider 420 are combined according to an appropriate combining method, and the combiner signals are distributed through the divider to send the n signals 406 having the same value to the interleaver 430.

An example of this bonding method is shown in Table 1. The n signals that pass through the channel are repeated s _₁ s _₂ . Let's say s _n . First, as a method of using the maximum value, s _₁ s _₂ ... When the maximum value of s _n is s _max , s _₁ s _₂ ... instead of s _n S _max is exported n times. The second method is to use the mean value, s _₁ s _₂ . the mean of s _n In this case, s _₁ s _₂ … instead of s _n Likewise, we export s average n times. In the second method, instead of the mean value, s _대신 s _₂ ... total sum of s _n s _sum {= s ₁ + s ₂ +.. You can also use + s _n }. This combination allows you to compensate the noisy signal with other signals. The signals 406 passing through the combiner 420 are interleaved through the interleaver 430 and then sent to the decoder DEC2 440 for decoding. If the decoded signal 408 is deinterleaved and the signal 409 is not desired to be repeatedly decoded, it may be output through the combiner 470 to be hard-determined by the hard determiner 480 and sent to the final output 4013. However, in order to perform repeated decoding, the deinterleaved signal 409 is sent to the combiner divider 460 to use the output signal 4011 together with the input signals 402 and 403 to decode it back to DEC1 to obtain desired performance. Repeat this process until you can. The decoder which performs this operation becomes the optimum decoder of the turbo encoder as shown in FIG.

Input and Output Signals of Combined Splitter

TABLE 1

Therefore, when the decoder of the present invention is used, there is an effect of sufficiently using the effect due to repetition.

Claims (8)

A decoder 1 that decodes a signal corresponding to an information bit and one signal corresponding to a depunctured parity bit, and a combining divider for combining the repeated signal from the decoder 1 and distributing the same signal into a signal having the same value; An interleaver for interleaving the signal from the splitter, a decoder 2 for decoding another signal corresponding to the signal and parity bits from the interleaver, a deinterleaver for deinterleaving the signal from the decoder 2, and a deinterleaver. And a combiner for combining signals and a hard determiner for determining a signal from the combiner as 0 or 1. Decoder 1 which repeats and decodes the signal corresponding to the information bit, the one signal corresponding to the depunctured parity bit, and the signal from the combined divider 2, and the signal having the same value by combining the repeated signal from the decoder 1 A decoder 2 which decodes a coupling divider 1 distributed to the processor, an interleaver interleaving a signal from the coupling divider 1, another signal corresponding to a signal from the interleaver and a parity bit, and a signal from the decoder 2. A deinterleaver for deinterleaving, a combiner divider 2 which combines the repeated signals from the interleaver, divides them into signals having the same value, and transmits them to the decoder 1, and a combiner that combines signals that do not require repetition from the deinterleaver. And a hard determiner for determining a signal from the combiner to be 0 or 1. Decoder. The decoder of claim 1, wherein the combiner divider determines a signal having the maximum value from the n signals input and replaces all the signals with a signal having the maximum value. The decoder of claim 2, wherein the combiner divider 1 and the combiner divider 2 determine a signal having the maximum value from the n signals input and replace the entire signal with a signal having the maximum value. The decoder of claim 1, wherein the combiner divider determines an average value of the n input signals and replaces all the signals with a signal having an average value. The decoder of claim 2, wherein the combiner divider 1 and the combiner divider 2 determine an average value of the n signals input and replace all the signals with a signal having an average value. The decoder of claim 1, wherein the combiner divider obtains the sum of the n input signals and replaces all the signals with the sum of the signals. The decoder of claim 2, wherein the combiner divider 1 and the combiner divider 2 obtain the sum of the n signals inputted, replace all the signals with the sum of the signals, and output the combined signals.