KR19990006172A - Ipyrom Cell - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to nonvolatile memory cells, and more particularly, to an epipyrom memory cell having a tunnel layer without using a buried oxide film.

In an y-pyrom cell having a cell portion and a pass transistor portion, a first junction region formed on a semiconductor substrate and first and second third junction layers and a second junction formed adjacent to each other at a predetermined distance from the first junction region. domain; A buried oxide film formed on the third bonding layer; A tunnel oxide film formed on the first junction layer and a first gate oxide film formed on the second junction layer and the buried oxide film; A floating gate formed on the tunnel oxide film and the gate oxide film; A second gate oxide film formed on the semiconductor substrate at a predetermined interval between the first junction region and the first junction layer and an ONO film formed on the floating gate; And a pass gate formed on the second gate oxide film and a program gate formed on the ONO film.

Description

Ipyrom Cell

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to nonvolatile memory cells, and more particularly, to an epipyrom memory cell having a tunnel layer without using a buried oxide film.

Typically, electrically erasable programmable ROM (IROM) cells used in integrated circuits in portable memory cards, including payphone cards, are basically composed of program gates, floating gates, and junction regions, and voltages at program gates and junction regions. Is applied to inject or draw electrons into the floating gate to program or erase the cell.

FIG. 1 is a cross-sectional view showing a structure of an epipyrom cell according to the prior art, wherein the pyramid cell is largely composed of a pass transistor unit A1 for selecting a specific ypyrom cell and a cell unit B1 for storing data.

Referring briefly to FIG. 1, the pass transistor section includes the channel region 11 of the pass transistor formed on the semiconductor substrate 10, the first junction region 12 of the ypyrom cell, the gate oxide film 19a, and the pass gate 20a. ), The cell portion is an N-type buried junction layer 13a for tunneling electrons during operation of the cell to the semiconductor substrate spaced apart from the first junction region by a predetermined distance, that is, the distance between the pass gate and the channel of the Ipyrom cell. Phosphorus P-type contact layer 13b, N-type buried junction layer 13c, second junction region 14 of the ypyrom cell, first buried oxide film 15 formed on junction layer, second buried oxide film 16 And a tunnel oxide film 17 formed in the first buried oxide film, a floating gate 18 formed on the entire structure, an oxide-nitride-oxide (ONO) film 19b, and a program gate.

As shown in FIG. 1, when the tunnel oxide film 17 of the ypyrom cell is formed between the thick buried oxide films 15, it is not only difficult to form the tunnel oxide film with good uniform thickness, but also the process becomes complicated and the buried oxide film Due to this, it is difficult to achieve high integration of Ipyrom cells.

The conventional ypyrom cells as described above have a problem of achieving high integration because the process is complicated and the area of the cell is large due to the specificity of the structure such as the buried oxide film.

In order to solve the above problems, the present invention has a structure in which a tunnel oxide film is directly formed on a semiconductor substrate without forming a tunnel oxide film in the buried oxide film, thereby reducing the area of the Ipyrom cell to achieve high integration of the memory cell. There is a purpose.

1 is a cross-sectional view of an ypyrom cell according to the prior art.

2 is a cross-sectional view of an ypyrom cell according to an embodiment of the present invention.

3A to 3D are cross-sectional views illustrating a manufacturing process of an ipyrom cell according to an embodiment of the present invention.

Explanation of symbols for the main parts of the drawings

A1, A2: pass transistor portion B1, B2: cell portion

10, 20: semiconductor substrate 11, 21: channel region of pass transistor

12, 14, 22, 24, 39a, 39b: junction area

13a, 13b, 13c, 23a, 23b, 23c, 31a, 31b, 31c: bonding layer

15, 16, 25, 32: buried oxide film 17, 26, 33a: tunnel oxide film

18, 28, 34: floating gates 19a, 27, 29a, 33, 37: gate oxide film

19b, 29b, 35: ONO film 20a, 30a, 38: pass gate

20b, 30b, 36: program gate

In order to achieve the above object, the present invention relates to an ear pyrom cell having a cell portion and a pass transistor portion, comprising: a first junction region formed in a semiconductor substrate and a first junction region formed adjacent to each other at a predetermined interval from the first junction region; A second third junction layer and a second junction region; A buried oxide film formed on the third bonding layer; A tunnel oxide film formed on the first junction layer and a first gate oxide film formed on the second junction layer and the buried oxide film; A floating gate formed on the tunnel oxide film and the first gate oxide film; A second gate oxide film formed on the semiconductor substrate at a predetermined interval between the first junction region and the first junction layer and a third gate oxide film formed on the floating gate; And a pass gate formed on the second gate oxide layer and a program gate formed on the third gate oxide layer.

According to the present invention, the fabrication process is simplified by directly forming the tunnel oxide film on the semiconductor substrate, and high integration of the ypyrom memory cell can be achieved.

EXAMPLE

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.

2 is a cross-sectional view of the ypyrom cell according to the present invention, and is largely composed of a pass transistor unit A2 for selecting a specific ypyrom cell and a cell unit B2 for storing data.

The pass transistor unit A2 is composed of a channel region 21, a first junction region 22, a gate oxide layer 29a, and a pass gate 30a of a pass transistor formed on the semiconductor substrate 20 as in the related art. The portion is formed by the channel portions 23a, 23b and 23c and the second junction region 24, the gate oxide layers 26 and 27 of the ypyrom cell, which are formed in the semiconductor substrate, which are largely separated by the distance between the pass gates, and the floating gate 28 and ONO. The film 29b and the program gate 30b are formed.

The channel portion is formed by adjoining the 1st-N-type, P-type, and 2-N-type junction layers on the substrate 20, and a gate oxide layer is formed thereon. The first-N-type junction layer 23a is disposed on the substrate 20. A tunnel oxide film 26 is formed to tunnel electrons during cell operation, and a gate oxide film 27 is formed on the P-type junction layer 23b and the 2-N-type junction layer 23c to form the P-type junction layer 23b. Acts to form a channel in the junction region according to the state of the data stored in the floating gate 28, the second 2-N type junction layer 23c is applied to the second junction region 24 adjacent to the second junction region. It plays a role to transfer the voltage.

A brief description will be made of a program and an erase operation of the EPyrom cell. The pass transistor unit selects a cell for the operation of the EPyrom cell. In order to erase the EPyROM cell, a pass transistor 29a applies a voltage to the pass gate 29a. Is selected and a high voltage is applied to the program gate 30b so that electrons from the 1-N type junction layer 23a tunnel through the tunnel oxide film 26 to the floating gate 28 to erase the cell.

When the cell is erased, since the P-type junction layer 23b does not form a channel, almost no current flows in the cell when the EPyrom cells are read.

In order to program the cell, a high voltage is applied to the pass gate 29b and the second junction region 24 so that a high voltage is applied to the junction layer and the junction region of the ypyrom cell. Pull out to the substrate.

After fully programming the ypyrom cell, the P-type junction layer 23b forms a channel to flow current due to the holes present in the floating gate 28 when the cell is read.

As such, by directly forming the tunnel oxide film on the semiconductor substrate without forming the buried oxide film, the area occupied by the buried oxide film can be reduced to achieve high integration.

3A to 3D are cross-sectional views illustrating a process for manufacturing the ypyrom cell according to the present invention. The process generally forms a cell portion followed by a pass transistor portion.

First, as shown in FIG. 3A, a first mask pattern is formed on a semiconductor substrate on which a device isolation layer and a well region (not shown) are previously formed to open a predetermined region of the cell portion through a photolithography process, and impurity ion implantation is performed on the entire structure. The process is performed to form the P-type bonding layer 31a in the region opened in the first mask pattern. Then, the first mask pattern is removed.

Subsequently, a second mask pattern is formed such that predetermined regions on both sides adjacent to the P-type bonding layer 31a are opened through a photographic process, and an impurity ion implantation process is performed on the entire structure to form the P-type bonding layer 31a. The first-N and second-N type bonding layers 31b and 31c of the cell portion are formed on the semiconductor substrate adjacent to the semiconductor substrate.

Subsequently, an oxide film (not shown) is deposited on the entire structure, and then the antioxidant film is etched to open the 2-N type bonding layer 31c through a photolithography process. Then, a thermal oxidation process is performed to form a buried oxide film 32 on the 2-N type bonding layer 31c, and to remove the antioxidant film.

Subsequently, a first gate oxide layer 33 is formed on the entire structure as shown in FIG. 3B, and the first gate oxide layer 33 in a predetermined region of the first-N type bonding layer 31b is formed by a photolithography process. A predetermined thickness is removed to form a tunnel oxide film 32a, which is a charge transfer passage during driving of the ypyrom cell.

Subsequently, after depositing a first polysilicon film on the entire structure, the first polysilicon film is etched in a direction crossing the array direction of the bonding layer through a photolithography process. Then, an ONO film and a second polysilicon film are sequentially deposited on the resultant.

Subsequently, the second polysilicon film, the ONO film, and the first polysilicon film are sequentially etched through a photolithography process, so that the second, first, and third bonding layers 31b, 31a, and 31c are adjacent to each other as shown in FIG. 3C. The program gate 36, the dielectric film 35, and the floating gate 34 of the Ipyrom cell are formed on the substrate.

Then, a second gate oxide film 37 and a third polysilicon film are deposited on the entire structure to form a pass transistor, and spaced apart from the first N-type junction layer 31b by a photolithography process. The pass gate 38 is formed on the region. Subsequently, the source / drain junction regions 39a and 39b of the ypyrom cell are formed through the impurity ion implantation process as shown in FIG. 3D.

As described above, the present invention can simplify the manufacturing process by forming the tunnel oxide film on the semiconductor substrate without forming the tunnel oxide film in the buried oxide film, and can also achieve high integration of the ypyrom memory cell.

While specific embodiments of the present invention have been described and illustrated, modifications and variations can be made by those skilled in the art. Accordingly, the following claims are to be understood as including all modifications and variations as long as they fall within the true spirit and scope of the present invention.

Claims (5)

In an ypyrom cell having a cell portion and a pass transistor portion, A first junction region formed on the semiconductor substrate and first, second, third junction layers, and second junction regions formed to be adjacent to each other at a predetermined interval from the first junction region; A buried oxide film formed on the third bonding layer; A tunnel oxide film formed on the first junction layer and a first gate oxide film formed on the second junction layer and the buried oxide film; A floating gate formed on the tunnel oxide film and the first gate oxide film; A second gate oxide film formed on the semiconductor substrate at a predetermined interval between the first junction region and the first junction layer and a third gate oxide film formed on the floating gate; And a pass gate formed on the second gate oxide layer and a program gate formed on the third gate oxide layer. The ypyrom cell according to claim 1, wherein the first junction layer is an N-type impurity layer. The ypyrom cell according to claim 1, wherein the second junction layer is a P-type impurity layer. The ypyrom cell according to claim 1, wherein the third junction layer is an N-type impurity layer. 2. The ypyrom cell according to claim 1, wherein the third gate oxide film is an ONO film.