KR19990003757A - Low noise amplifier (LNA) for high frequency (RF) transmitter and receiver and its design method - Google Patents

Abstract

The present invention relates to a low noise amplifier (LNA) for a high frequency (RF) transmitter / receiver and a design method thereof. The low noise amplifier and the variable gain amplifier, which are necessary for the RF unit, are input stage matching units and two stage cascode matching amplification. The present invention relates to a technology with economical benefits by applying three steps to miniaturization, light weight, and low power.

Description

Low noise amplifier (LNA) for high frequency (RF) transmitter and receiver and its design method

The present invention relates to a low noise amplifier (LNA) for a high frequency (RF) transmitter / receiver and a method of designing the same, wherein the low noise amplifier and the variable gain amplifier necessary for the RF unit are miniaturized, reduced in weight, and low in power, The present invention relates to a low noise amplifier (LNA) for a high frequency (RF) transmitter / receiver and a method of designing the same.

In modern society, the demand for mobile phones has increased and the need for data communication as well as voice has led to the transition from analog to large digital.

In order to successfully commercialize the 2nd generation mobile communication service, it is necessary to reduce the size, weight, power, and cost of the terminal.

However, the high frequency (RF) part of the terminal occupies a large design area and consumes a lot of current, and thus becomes a key factor in miniaturization of the terminal.

Generally, the RF part of the terminal is composed of a low noise amplifier (LNA), a mixer, a voltage controlled oscillator (VCO), a voltage amplifier, and the like, and when these are converted into a one-chip microwave integrated circuit (hereinafter referred to as MMIC), the RF part is It can be compact, light weight and low power, and can be mass-produced at a lower cost than the existing hybrid type.

In the present invention, in consideration of the above-described matters, the first stage is made of noise matching, and the second stage and the third stage are each designed in a cascode type so that the gate of the rear stage is subjected to voltage change so as to obtain variable gain characteristics. It aims to MMIC three stages of low gain amplifier and variable gain amplifier using foundry.

In order to achieve the above object, the present invention is to MMIC a low-noise amplifier that functions to minimize and amplify the additional noise of the signal received from the antenna of the RF transmitter and receiver of the terminal, wherein the low-voltage amplifier in the future public land In order to be used for a mobile communication system (FPLMTS) terminal, a variable gain is obtained so that the strength of the signal received at the antenna of the terminal is constant according to the relative position and time of the base station and the terminal in the cell. Variable gain amplifiers with characteristics are required.

Therefore, the present invention is to MMIC the low-noise amplifier and the variable gain amplifier in three stages by using the MMIC foundry to perform the above functions.

1 shows a lay-out of a low noise amplifier (LNA) implemented by the present invention.

* Explanation of symbols for main parts of the drawings

10: input stage matching unit

11: RF input pad

12, 13, 21, 22, 31, 32, 34: Grounding pad

20: first cascode matching amplifier

23, 33: DC control signal input pad

30: second cascode matching amplifier

The low-noise amplifier of the present invention which operates as described above implements an input stage matching section for amplifying the level of the signal input through the antenna and a plurality of field effect transistors (FETs) in a cascode manner to change the voltage at the rear stage. It is characterized in that it comprises a first and second cascode matching amplifier having a variable gain characteristic to make the strength of the signal received at the antenna of the terminal according to the relative position and time of the base station and the terminal.

In addition, the low noise amplifier design method of the present invention which operates as described above selects the inductance value of the drain of the field effect transistor and the gate bias inductor considering the input / output matching at the same time, and connects the inductor to the source to improve the matching characteristics. The input matching section is further stabilized to act as a low noise amplifier, and a plurality of stages are cascoded to obtain the maximum gain of the variable gain. By implementing the cascode matching amplifier of the to act as a variable gain amplifier, each stage is characterized by one chip.

The above objects, features, and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The input stage matching unit 10 which amplifies the level of the signal input through the antenna constantly and a plurality of field effect transistors (FETs) are implemented in a cascode manner to give a voltage change at the rear stage, so that the relative positions of the base station and the terminal and And first and second cascode matched amplifiers 20 and 30 having a variable gain characteristic to make the strength of the signal received by the antenna of the terminal constant over time.

The first stage of the three stage design serves as a low noise amplifier (LNA), and the second stage and third stage serve as a variable gain amplifier (VGA).

The input stage matching unit 10 includes an RF input port 11 implemented at an input terminal of the frequency converter, a grounding pad 12 implemented at both sides of the RF input port 11, and the RF input port 11. A first field effect transistor (FET1) connected to one side of the first field effect transistor (FET1) and the RF input port (11) and the first FET (FET1). A second inductor L2 connected to a grounding pad 13, which serves as a source bias of the first capacitor C1 and the first inductor L1 and the first field effect transistor FET1, and serves as a ground, is connected to one side. It is configured to include.

In the present invention, the matching circuit matches the gate terminal of the first FET FET1 to 50 Ω.

The first cascode matched amplifier 20 is connected to an output terminal of the input stage matcher, and is connected to a cascode type second and third FETs (FET2 and FET3), the second FET (FET2) and the first FET. A second capacitor C2 and a third inductor L3 connected between the first and second FETs FET1 and connected between the FET1s and respectively matching the output terminal of the first FET FET1 and the input terminal of the second FET FET2, respectively. And a fifth inductor L5, a fifth inductor L5 connected between the second capacitor C2 and the second FET FET2 to serve as a source bias of the second FET FET2, and the third A control part (not shown) in the terminal (not shown) connected to the third capacitor C3 and the first resistor R1 for the drain side matching of the FET FET3 and one side of the first resistor R1. And a DC control signal input pad 23 for receiving the DC control signal output from the third capacitor C3 and receiving the DC control signal. It is sex.

The grounding pads 21 and 22 of the ground role are connected to one side of the third inductor L3 and the fourth inductor L4.

The second cascode matched amplifier 30 is connected to an output terminal of the first cascode matched amplifier 20, and fourth and fifth FETs (FET4, FET5) connected in a cascode type, and the first The sixth, seventh, and eighth inductors L6 and fourth capacitors connected between the output terminal of the cascode matched amplifier 20 and the fourth FET (FET4) to match both sides while serving as DC blocking and DC feeder functions, respectively. C4), the fifth capacitor C5 and the second resistor R2 for the drain side matching of the fifth FET FET3, and one side of the first resistor R2, are connected to the terminal (not shown in the drawing). And a DC control signal input pad 33 for receiving a DC control signal output from a control unit (not shown in the drawing) and inputting it to the third capacitor C3, and one side of the fifth FET FET5. A sixth capacitor C6 and a ninth inductor L9 connected to each other to match an RF output signal, and connected to one side of the sixth capacitor C6; It is configured to include an RF output port 35 that forms the RF output terminal of the frequency converter, and a grounding pad 36 implemented on both sides of the RF output port 35.

The grounding pads 31, 32, and 34 are connected to one side of the seventh, eighth, and ninth inductors L7 to L9.

Referring to the design method of the frequency mixer of the present invention configured as described above are as follows.

The input signal received through the antenna at the input stage matching unit 10 passes through a duplexer (transmit / receive signal switching), and the first capacitor C1 connected to the input terminal of the first FET FET1 and the first inductor L1. Is received).

The signal is input to the first FET FET1 through the second inductor L2, which is the source bias of the first FET FET1, amplified to a predetermined level, and then output to the first cascode matched amplifier 20. .

For this function, the inductance value is determined by considering the input / output matching at the same time when selecting the inductor for the drain and the gate.

The stability characteristics of a given FET at its operating frequency are very unstable.

Therefore, the stability characteristics are improved by attaching the inductor to the source, and the parasitic resistance of the inductor used for input / output matching also improves the stability.

In addition, since the complex conjugate matching point of the input stage and the matching point for minimizing noise do not coincide, it is designed to match as low noise as possible in the range of S11-10dB.

In addition, the cascode matching amplifiers 20 and 30 are matched so as to obtain the maximum gain. The cascode type is configured in a cascode type so that the gate of the rear stage is changed to obtain a variable gain characteristic. do.

If each stage is designed for maximum gain at operating frequency, the gain characteristics of all three stages are very narrowband.

Therefore, the first stage is matched at the center of the operating frequency, and the second and third stages are matched at a frequency slightly away from the center frequency to obtain the flat gain characteristics of each of the three stages.

As described in detail above, the present invention implements the low noise amplifier and the variable gain amplifier required by the RF unit in three stages by applying an input stage matching unit and two cascode matching amplifiers, thereby miniaturizing, reducing weight, and reducing power, It is accompanied by economic advantages.

In addition, a preferred embodiment of the present invention is disclosed for the purpose of illustration, those skilled in the art will be able to make various modifications, changes, additions, etc. within the spirit and scope of the present invention, such modifications and modifications belong to the following claims You will have to look.

Claims (7)

An input stage matching section for amplifying the level of the signal input through the antenna and a plurality of field effect transistors (FETs) are cascoded to give a voltage change at the rear stage, depending on the relative position and time of the base station and the terminal. A low noise amplifier (LNA) for a high frequency (RF) transmitter / receiver, comprising first and second cascode matched amplifiers having variable gain characteristics for keeping the strength of the signal received at the antenna of the terminal constant. The method of claim 1, wherein the input stage matching unit RF input port implemented in the input terminal of the frequency converter, a grounding pad implemented on both sides of the RF input port, a first field effect transistor connected to one side of the RF input port, A first capacitor and a first inductor connected between the RF input port and the first FET, each of which functions as a DC blocking and a DC feeder, forming a matching circuit at an input terminal, and serves as a source bias of the first FET; The low noise amplifier (LNA) for a high frequency (RF) transmitting and receiving unit, characterized in that it comprises a second inductor connected to the grounding pad that serves as a ground. The low noise amplifier (LNA) according to claim 2, wherein the matching circuit matches the gate terminal of the first FET to 50 ohms. The method of claim 1, wherein the first cascode matched amplifier is connected to an output terminal of the input stage matcher, and is connected between the second and third FETs connected in a cascode type, and between the second FET and the first FET, respectively. A second capacitor, a third inductor and a fourth inductor, which match the output terminal of the first FET and the input terminal of the second FET, while blocking and directing a DC feeder, are connected between the second capacitor and the second FET to connect the second capacitor. A fifth inductor serving as a source bias, a third capacitor and a first resistor for matching the drain of the third FET, and a DC control signal connected to one side of the first resistor and output from a controller in the terminal; And a low noise amplifier (LNA) for a high frequency (RF) transmitter / receiver, comprising a DC control signal input pad input to the third capacitor. The method of claim 1, wherein the second cascode matched amplifier unit is connected to an output terminal of the first cascode matched amplifier unit, and the fourth and fifth FETs connected in a cascode type, the output terminal of the first cascode matched amplifier unit and a first A sixth, seventh and eighth inductor and a fourth capacitor connected between the four FETs, respectively, serving as DC blocking and DC feeder functions, and a fifth capacitor and a second resistor for drain-side matching of the fifth FET; And a DC control signal input pad connected to one side of the first resistor and output from the control unit in the terminal and input to the third capacitor, and an RF output signal connected to one side of the fifth FET. A sixth capacitor and a ninth inductor, an RF output port connected to one side of the sixth capacitor to form an RF output terminal of the frequency converter, and both sides of the RF output port High frequency (RF) transmission / reception part-forming a low noise amplifier (LNA) characterized in that comprises a grounding pad. Selecting the inductance value of the drain and gate bias inductor of the field effect transistor considering the input / output matching at the same time, and also implementing the input matching unit to further stabilize the matching characteristics by connecting the inductor to the source to act as a low noise amplifier, In order to obtain the maximum gain of the gain, a plurality of stages are formed in a cascode type, and each cascode matched amplification unit that provides a flat gain characteristic by applying a voltage change to the rear stage acts as a variable gain amplifier. A low noise amplifier (LNA) design method for a high frequency (RF) transmitter / receiver, characterized in that each stage is one chip. The method of claim 6, wherein the first stage in each stage is matched at the center of the operating frequency, the second stage and the third stage are matched at a frequency slightly away from the center frequency, respectively, to obtain a flat gain characteristics in the entire stage A low noise amplifier (LNA) design method for a high frequency (RF) transmitter / receiver.